hw/i386.reference/s15_07.htm

   1 <!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
   2 <HTML>
   3 <HEAD>
   4 <TITLE>80386 Programmer's Reference Manual -- Section 15.7</TITLE>
   5 </HEAD>
   6 <BODY>
   7 <B>up:</B> <A HREF="c15.htm">
   8 Chapter 15 -- Virtual 8086 Mode</A><BR>
   9 <B>prev:</B> <A HREF="s15_06.htm">15.6  Differences From 8086</A><BR>
  10 <B>next:</B> <A HREF="c16.htm">
  11 Chapter 16 -- Mixing 16-Bit and 32 Bit Code</A>
  12 <P>
  13 <HR>
  14 <P>
  15 <H1>15.7  Differences From 80286 Real-Address Mode</H1>
  16 The 80286 processor implements the bus lock function differently than the
  17 80386. This fact may or may not be apparent to 8086 programs, depending on
  18 how the V86 monitor handles the <A HREF="LOCK.htm">LOCK</A> prefix.
  19 <A HREF="LOCK.htm">LOCK</A>ed instructions are
  20 sensitive to IOPL; therefore, software designers can choose to emulate its
  21 function. If, however, 8086 programs are allowed to execute
  22 <A HREF="LOCK.htm">LOCK</A> directly,
  23 programs that use forms of memory locking specific to the 8086 may not
  24 execute properly when transported to a specific application of the 80386.
  25 <P>
  26 The <A HREF="LOCK.htm">LOCK</A>
  27 prefix and its corresponding output signal should only be used to
  28 prevent other bus masters from interrupting a data movement operation.
  29 <A HREF="LOCK.htm">LOCK</A>
  30 may only be used with the following 80386 instructions when they modify
  31 memory. An undefined-opcode exception results from using
  32 <A HREF="LOCK.htm">LOCK</A> before any
  33 other instruction.
  34 <UL>
  35 <LI> Bit test and change:
  36 <A HREF="BTS.htm">BTS</A>,
  37 <A HREF="BTR.htm">BTR</A>,
  38 <A HREF="BTC.htm">BTC</A>.
  39 <LI> Exchange:
  40 <A HREF="XCHG.htm">XCHG</A>.
  41 <LI> One-operand arithmetic and logical:
  42 <A HREF="INC.htm">INC</A>,
  43 <A HREF="DEC.htm">DEC</A>,
  44 <A HREF="NOT.htm">NOT</A>, and
  45 <A HREF="NEG.htm">NEG</A>.
  46 <LI> Two-operand arithmetic and logical:
  47 <A HREF="ADD.htm">ADD</A>,
  48 <A HREF="ADC.htm">ADC</A>,
  49 <A HREF="SUB.htm">SUB</A>,
  50 <A HREF="SBB.htm">SBB</A>,
  51 <A HREF="AND.htm">AND</A>,
  52 <A HREF="OR.htm">OR</A>,
  53 <A HREF="XOR.htm">XOR</A>.
  54 </UL>
  55 A locked instruction is guaranteed to lock only the area of memory defined
  56 by the destination operand, but may lock a larger memory area. For example,
  57 typical 8086 and 80286 configurations lock the entire physical memory space.
  58 With the 80386, the defined area of memory is guaranteed to be locked
  59 against access by a processor executing a locked instruction on exactly the
  60 same memory area, i.e., an operand with identical starting address and
  61 identical length.
  62 <P>
  63 <HR>
  64 <P>
  65 <B>up:</B> <A HREF="c15.htm">
  66 Chapter 15 -- Virtual 8086 Mode</A><BR>
  67 <B>prev:</B> <A HREF="s15_06.htm">15.6  Differences From 8086</A><BR>
  68 <B>next:</B> <A HREF="c16.htm">
  69 Chapter 16 -- Mixing 16-Bit and 32 Bit Code</A>
  70 </BODY>