hw/i386.reference/s11_01.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Section 11.1</TITLE>
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   7 <B>up:</B> <A HREF="c11.htm">
   8 Chapter 11 -- Coprocessing and Multiprocessing</A><BR>
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  10 <A HREF="c11.htm">Chapter 11 -- Coprocessing and Multiprocessing</A><BR>
  11 <B>next:</B> <A HREF="s11_02.htm">11.2  General Multiprocessing</A>
  12 <P>
  13 <HR>
  14 <P>
  15 <H1>11.1  Coprocessing</H1>
  16 The components of the coprocessor interface include:
  17 <UL>
  18 <LI> ET bit of control register zero (CR0)
  19 <LI> The EM, and MP bits of CR0
  20 <LI> The ESC instructions
  21 <LI> The <A HREF="WAIT.htm">WAIT</A> instruction
  22 <LI> The TS bit of CR0
  23 <LI> Exceptions
  24 </UL>
  25
  26 <H2>11.1.1  Coprocessor Identification</H2>
  27 The 80386 is designed to operate with either an 80287 or 80387 math
  28 coprocessor. The ET bit of CR0 indicates which type of coprocessor is
  29 present. ET is set automatically by the 80386 after RESET according to the
  30 level detected on the ERROR# input. If desired, ET may also be set or reset
  31 by loading CR0 with a <A HREF="MOVRS.htm">MOV</A> instruction. If ET is set, the 80386 uses the
  32 32-bit protocol of the 80387; if reset, the 80386 uses the 16-bit protocol
  33 of the 80287.
  34
  35 <H2>11.1.2  ESC and WAIT Instructions</H2>
  36 The 80386 interprets the pattern 11011B in the first five bits of an
  37 instruction as an opcode intended for a coprocessor. Instructions thus
  38 marked are called ESCAPE or ESC instructions. The CPU performs the following
  39 functions upon encountering an ESC instruction before sending the
  40 instruction to the coprocessor:
  41 <UL>
  42 <LI> Tests the emulation mode (EM) flag to determine whether coprocessor
  43 functions are being emulated by software.
  44 <LI> Tests the TS flag to determine whether there has been a context change
  45 since the last ESC instruction.
  46 <LI> For some ESC instructions, tests the ERROR# pin to determine whether
  47 the coprocessor detected an error in the previous ESC instruction.
  48 </UL>
  49 The <A HREF="WAIT.htm">WAIT</A> instruction is not an ESC instruction, but
  50 <A HREF="WAIT.htm">WAIT</A> causes the CPU to
  51 perform some of the same tests that it performs upon encountering an ESC
  52 instruction. The processor performs the following actions for a <A HREF="WAIT.htm">WAIT</A>
  53 instruction:
  54 <UL>
  55 <LI> Waits until the coprocessor no longer asserts the BUSY# pin.
  56 <LI> Tests the ERROR# pin (after BUSY# goes inactive). If ERROR# is active,
  57 the 80386 signals exception 16, which indicates that the coprocessor
  58 encountered an error in the previous ESC instruction.
  59 <LI> <A HREF="WAIT.htm">WAIT</A> can therefore be used to cause exception 16 if an error is
  60 pending from a previous ESC instruction. Note that, if no coprocessor
  61 is present, the ERROR# and BUSY# pins should be tied inactive to
  62 prevent <A HREF="WAIT.htm">WAIT</A> from waiting forever or causing spurious exceptions.
  63 </UL>
  64
  65 <H2>11.1.3  EM and MP Flags</H2>
  66 The EM and MP flags of CR0 control how the processor reacts to coprocessor
  67 instructions.
  68 <P>
  69 The EM bit indicates whether coprocessor functions are to be emulated. If
  70 the processor finds EM set when executing an ESC instruction, it signals
  71 exception 7, giving the exception handler an opportunity to emulate the ESC
  72 instruction.
  73 <P>
  74 The MP (monitor coprocessor) bit indicates whether a coprocessor is
  75 actually attached. The MP flag controls the function of the <A HREF="WAIT.htm">WAIT</A>
  76 instruction. If, when executing a <A HREF="WAIT.htm">WAIT</A> instruction, the CPU finds MP set,
  77 then it tests the TS flag; it does not otherwise test TS during a <A HREF="WAIT.htm">WAIT</A>
  78 instruction. If it finds TS set under these conditions, the CPU signals
  79 exception 7.
  80 <P>
  81 The EM and MP flags can be changed with the aid of a <A HREF="MOVRS.htm">MOV</A> instruction using
  82 CR0 as the destination operand and read with the aid of a <A HREF="MOVRS.htm">MOV</A> instruction
  83 with CR0 as the source operand. These forms of the <A HREF="MOVRS.htm">MOV</A> instruction can be
  84 executed only at privilege level zero.
  85
  86 <H2>11.1.4  The Task-Switched Flag</H2>
  87 The TS bit of CR0 helps to determine when the context of the coprocessor
  88 does not match that of the task being executed by the 80386 CPU. The 80386
  89 sets TS each time it performs a task switch (whether triggered by software
  90 or by hardware interrupt). If, when interpreting one of the ESC
  91 instructions, the CPU finds TS already set, it causes exception 7. The <A HREF="WAIT.htm">WAIT</A>
  92 instruction also causes exception 7 if both TS and MP are set. Operating
  93 systems can use this exception to switch the context of the coprocessor to
  94 correspond to the current task. Refer to the 80386 System Software Writer's
  95 Guide for an example.
  96 <P>
  97 The <A HREF="CLTS.htm">CLTS</A> instruction (legal only at privilege level zero) resets the TS
  98 flag.
  99
 100 <H2>11.1.5  Coprocessor Exceptions</H2>
 101 Three exceptions aid in interfacing to a coprocessor: interrupt 7
 102 (coprocessor not available), interrupt 9 (coprocessor segment overrun), and
 103 interrupt 16 (coprocessor error).
 104
 105 <H3>11.1.5.1 Interrupt 7 -- Coprocessor Not Available</H3>
 106 This exception occurs in either of two conditions:
 107 <OL>
 108 <LI> The CPU encounters an ESC instruction and EM is set. In this case,
 109 the exception handler should emulate the instruction that caused the
 110 exception. TS may also be set.
 111 <LI> The CPU encounters either the <A HREF="WAIT.htm">WAIT</A> instruction or an ESC instruction
 112 when both MP and TS are set. In this case, the exception handler
 113 should update the state of the coprocessor, if necessary.
 114 </OL>
 115
 116 <H3>11.1.5.2 Interrupt 9 -- Coprocessor Segment Overrun</H3>
 117 <UL>
 118 This exception occurs in protected mode under the following conditions:
 119 <LI> An operand of a coprocessor instruction wraps around an addressing
 120 limit (0FFFFH for small segments, 0FFFFFFFFH for big segments, zero for
 121 expand-down segments). An operand may wrap around an addressing limit
 122 when the segment limit is near an addressing limit and the operand is
 123 near the largest valid address in the segment. Because of the
 124 wrap-around, the beginning and ending addresses of such an operand
 125 will be near opposite ends of the segment.
 126 <LI> Both the first byte and the last byte of the operand (considering
 127 wrap-around) are at addresses located in the segment and in present and
 128 accessible pages.
 129 <LI> The operand spans inaccessible addresses. There are two ways that such
 130 an operand may also span inaccessible addresses:
 131 <OL>
 132 <LI> The segment limit is not equal to the addressing limit (e.g.,
 133 addressing limit is FFFFH and segment limit is FFFDH); therefore,
 134 the operand will span addresses that are not within the segment
 135 (e.g., an 8-byte operand that starts at valid offset FFFC will span
 136 addresses FFFC-FFFF and 0000-0003; however, addresses FFFE and FFFF
 137 are not valid, because they exceed the limit);
 138 <LI> The operand begins and ends in present and accessible pages but
 139 intermediate bytes of the operand fall either in a not-present page
 140 or in a page to which the current procedure does not have access
 141 rights.
 142 </OL>
 143 </UL>
 144 The address of the failing numerics instruction and data operand may be
 145 lost; an FSTENV does not return reliable addresses. As with the 80286/80287,
 146 the segment overrun exception should be handled by executing an FNINIT
 147 instruction (i.e., an FINIT without a preceding <A HREF="WAIT.htm">WAIT</A>). The return address on
 148 the stack does not necessarily point to the failing instruction nor to the
 149 following instruction. The failing numerics instruction is not restartable.
 150 <P>
 151 Case 2 can be avoided by either aligning all segments on page boundaries or
 152 by not starting them within 108 bytes of the start or end of a page. (The
 153 maximum size of a coprocessor operand is 108 bytes.) Case 1 can be avoided
 154 by making sure that the gap between the last valid offset and the first
 155 valid offset of a segment is either no less than 108 bytes or is zero (i.e.,
 156 the segment is of full size). If neither software system design constraint
 157 is acceptable, the exception handler should execute FNINIT and should
 158 probably terminate the task.
 159
 160 <H3>11.1.5.3 Interrupt 16 -- Coprocessor Error</H3>
 161 The numerics coprocessors can detect six different exception conditions
 162 during instruction execution. If the detected exception is not masked by a
 163 bit in the control word, the coprocessor communicates the fact that an error
 164 occurred to the CPU by a signal at the ERROR# pin. The CPU causes interrupt
 165 16 the next time it checks the ERROR# pin, which is only at the beginning of
 166 a subsequent <A HREF="WAIT.htm">WAIT</A> or certain ESC instructions. If the exception is masked,
 167 the numerics coprocessor handles the exception according to on-board logic;
 168 it does not assert the ERROR# pin in this case.
 169 <P>
 170 <HR>
 171 <P>
 172 <B>up:</B> <A HREF="c11.htm">
 173 Chapter 11 -- Coprocessing and Multiprocessing</A><BR>
 174 <B>prev:</B>
 175 <A HREF="c11.htm">Chapter 11 -- Coprocessing and Multiprocessing</A><BR>
 176 <B>next:</B> <A HREF="s11_02.htm">11.2  General Multiprocessing</A>
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