hw/i386.reference/s09_04.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Section 9.4</TITLE>
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   7 <B>up:</B> <A HREF="c09.htm">
   8 Chapter 9 -- Exceptions and Interrupts</A><BR>
   9 <B>prev:</B> <A HREF="s09_03.htm">9.3  Priority Among Simultaneous Interrupts and Exceptions</A><BR>
  10 <B>next:</B> <A HREF="s09_05.htm">9.5  IDT Descriptors</A>
  11 <P>
  12 <HR>
  13 <P>
  14 <H1>9.4  Interrupt Descriptor Table</H1>
  15 The interrupt descriptor table (IDT) associates each interrupt or exception
  16 identifier with a descriptor for the instructions that service the
  17 associated event. Like the GDT and LDTs, the IDT is an array of 8-byte
  18 descriptors. Unlike the GDT and LDTs, the first entry of the IDT may contain
  19 a descriptor. To form an index into the IDT, the processor multiplies the
  20 interrupt or exception identifier by eight. Because there are only 256
  21 identifiers, the IDT need not contain more than 256 descriptors. It can
  22 contain fewer than 256 entries; entries are required only for interrupt
  23 identifiers that are actually used.
  24 <P>
  25 The IDT may reside anywhere in physical memory. As
  26 <A HREF="#fig9-1">Figure 9-1</A>
  27   shows, the
  28 processor locates the IDT by means of the IDT register (IDTR). The
  29 instructions
  30 <A HREF="LGDT.htm">LIDT</A> and
  31 <A HREF="SGDT.htm">SIDT</A> operate on the IDTR. Both instructions have one
  32 explicit operand: the address in memory of a 6-byte area.
  33 <A HREF="#fig9-2">Figure 9-2</A>
  34   shows
  35 the format of this area.
  36 <P>
  37 <A HREF="LGDT.htm">LIDT</A> (Load IDT register)
  38 loads the IDT register with the linear base
  39 address and limit values contained in the memory operand.  This instruction
  40 can be executed only when the CPL is zero. It is normally used by the
  41 initialization logic of an operating system when creating an IDT.  An
  42 operating system may also use it to change from one IDT to another.
  43 <P>
  44 <A HREF="SGDT.htm">SIDT</A> (Store IDT register)
  45 copies the base and limit value stored in IDTR
  46 to a memory location. This instruction can be executed at any privilege
  47 level.
  48 <A NAME="Table 9-2">
  49 <PRE>
  50 Table 9-2. Priority Among Simultaneous Interrupts and Exceptions
  51
  52 Priority   Class of Interrupt or Exception
  53
  54 HIGHEST    Faults except debug faults
  55 Trap instructions INTO, INT n, INT 3
  56 Debug traps for this instruction
  57 Debug faults for next instruction
  58 NMI interrupt
  59 LOWEST     INTR interrupt
  60
  61 </PRE>
  62 </A>
  63
  64 <A NAME="fig9-1">
  65 <IMG align=center SRC="fig9-1.gif" border=0>
  66 <P>
  67 <A NAME="fig9-2">
  68 <IMG align=center SRC="fig9-2.gif" border=0>
  69 <P>
  70 <HR>
  71 <P>
  72 <B>up:</B> <A HREF="c09.htm">
  73 Chapter 9 -- Exceptions and Interrupts</A><BR>
  74 <B>prev:</B> <A HREF="s09_03.htm">9.3  Priority Among Simultaneous Interrupts and Exceptions</A><BR>
  75 <B>next:</B> <A HREF="s09_05.htm">9.5  IDT Descriptors</A>
  76 </BODY>