hw/i386.reference/s09_02.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Section 9.2</TITLE>
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   7 <B>up:</B> <A HREF="c09.htm">
   8 Chapter 9 -- Exceptions and Interrupts</A><BR>
   9 <B>prev:</B> <A HREF="s09_01.htm">9.1  Identifying Interrupts</A><BR>
  10 <B>next:</B> <A HREF="s09_03.htm">9.3  Priority Among Simultaneous Interrupts and Exceptions</A>
  11 <P>
  12 <HR>
  13 <P>
  14 <H1>9.2  Enabling and Disabling Interrupts</H1>
  15 The processor services interrupts and exceptions only between the end of
  16 one instruction and the beginning of the next. When the repeat prefix is
  17 used to repeat a string instruction, interrupts and exceptions may occur
  18 between repetitions. Thus, operations on long strings do not delay interrupt
  19 response.
  20 <P>
  21 Certain conditions and flag settings cause the processor to inhibit certain
  22 interrupts and exceptions at instruction boundaries.
  23
  24 <H2>9.2.1  NMI Masks Further NMIs</H2>
  25 While an NMI handler is executing, the processor ignores further interrupt
  26 signals at the NMI pin until the next <A HREF="IRET.htm">IRET</A> instruction is executed.
  27
  28 <H2>9.2.2  IF Masks INTR</H2>
  29 The IF (interrupt-enable flag) controls the acceptance of external
  30 interrupts signalled via the INTR pin. When IF=0, INTR interrupts are
  31 inhibited; when IF=1, INTR interrupts are enabled. As with the other flag
  32 bits, the processor clears IF in response to a RESET signal. The
  33 instructions <A HREF="CLI.htm">CLI</A> and
  34 <A HREF="STI.htm">STI</A> alter the setting of IF.
  35 <P>
  36 <A HREF="CLI.htm">CLI</A> (Clear Interrupt-Enable Flag) and
  37 <A HREF="STI.htm">STI</A> (Set Interrupt-Enable Flag)
  38 explicitly alter IF (bit 9 in the flag register). These instructions may be
  39 executed only if CPL <= IOPL. A protection exception occurs if they are
  40 executed when CPL > IOPL.
  41 <P>
  42 The IF is also affected implicitly by the following operations:
  43 <UL>
  44 <LI> The instruction
  45 <A HREF="PUSHF.htm">PUSHF</A> stores all flags, including IF, in the stack
  46 where they can be examined.
  47 <LI> Task switches and the instructions
  48 <A HREF="POPF.htm">POPF</A> and
  49 <A HREF="IRET.htm">IRET</A> load the flags
  50 register; therefore, they can be used to modify IF.
  51 <LI> Interrupts through interrupt gates automatically reset IF, disabling
  52 interrupts. (Interrupt gates are explained later in this chapter.)
  53 </UL>
  54
  55 <H2>9.2.3  RF Masks Debug Faults</H2>
  56 The RF bit in EFLAGS controls the recognition of debug faults. This permits
  57 debug faults to be raised for a given instruction at most once, no matter
  58 how many times the instruction is restarted . (Refer to
  59 <A HREF="c12.htm">Chapter 12</A>
  60    for more
  61 information on debugging.)
  62
  63 <H2>9.2.4  MOV or POP to SS Masks Some Interrupts and Exceptions</H2>
  64 Software that needs to change stack segments often uses a pair of
  65 instructions; for example:
  66 <PRE>
  67 <A HREF="MOV.htm">MOV</A> SS, AX
  68 <A HREF="MOV.htm">MOV</A> ESP, StackTop
  69 </PRE>
  70 If an interrupt or exception is processed after SS has been changed but
  71 before ESP has received the corresponding change, the two parts of the stack
  72 pointer SS:ESP are inconsistent for the duration of the interrupt handler or
  73 exception handler.
  74 <P>
  75 To prevent this situation, the 80386, after both a
  76 <A HREF="MOV.htm">MOV</A> to SS and a
  77 <A HREF="POP.htm">POP</A> to
  78 SS instruction, inhibits NMI, INTR, debug exceptions, and single-step traps
  79 at the instruction boundary following the instruction that changes SS. Some
  80 exceptions may still occur; namely, page fault and general protection fault.
  81 Always use the 80386
  82 <A HREF="LGS.htm">LSS</A> instruction, and the problem will not occur.
  83 <P>
  84 <HR>
  85 <P>
  86 <B>up:</B> <A HREF="c09.htm">
  87 Chapter 9 -- Exceptions and Interrupts</A><BR>
  88 <B>prev:</B> <A HREF="s09_01.htm">9.1  Identifying Interrupts</A><BR>
  89 <B>next:</B> <A HREF="s09_03.htm">9.3  Priority Among Simultaneous Interrupts and Exceptions</A>
  90 </BODY>