hw/i386.reference/s07_01.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Section 7.1</TITLE>
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   8 Chapter 7 -- Multitasking</A><BR>
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  13 <P>
  14 <H1>7.1  Task State Segment</H1>
  15 All the information the processor needs in order to manage a task is stored
  16 in a special type of segment, a task state segment (TSS).
  17 <A HREF="#fig7-1">Figure 7-1</A>
  18   shows
  19 the format of a TSS for executing 80386 tasks. (Another format is used for
  20 executing 80286 tasks; refer to
  21 <A HREF="c13.htm">Chapter 13</A>.)
  22 <P>
  23 The fields of a TSS belong to two classes:
  24 <OL>
  25 <LI> A dynamic set that the processor updates with each switch from the
  26 task. This set includes the fields that store:
  27 <UL>
  28 <LI> The general registers (EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI).
  29 <LI> The segment registers (ES, CS, SS, DS, FS, GS).
  30 <LI> The flags register (EFLAGS).
  31 <LI> The instruction pointer (EIP).
  32 <LI> The selector of the TSS of the previously executing task (updated
  33 only when a return is expected).
  34 </UL>
  35 <LI> A static set that the processor reads but does not change. This set
  36 includes the fields that store:
  37 <UL>
  38 <LI> The selector of the task's LDT.
  39 <LI> The register (PDBR) that contains the base address of the task's
  40 page directory (read only when paging is enabled).
  41 <LI> Pointers to the stacks for privilege levels 0-2.
  42 <LI> The T-bit (debug trap bit) which causes the processor to raise a
  43 debug exception when a task switch occurs . (Refer to
  44 <A HREF="c12.htm">Chapter 12</A>
  45
  46 for more information on debugging.)
  47 <LI> The I/O map base (refer to
  48 <A HREF="c08.htm">Chapter 8</A> for more information on the
  49 use of the I/O map).
  50 </UL>
  51 </OL>
  52 Task state segments may reside anywhere in the linear space. The only case
  53 that requires caution is when the TSS spans a page boundary and the
  54 higher-addressed page is not present. In this case, the processor raises an
  55 exception if it encounters the not-present page while reading the TSS during
  56 a task switch. Such an exception can be avoided by either of two strategies:
  57 <OL>
  58 <LI> By allocating the TSS so that it does not cross a page boundary.
  59 <LI> By ensuring that both pages are either both present or both
  60 not-present at the time of a task switch. If both pages are
  61 not-present, then the page-fault handler must make both pages present
  62 before restarting the instruction that caused the task switch.
  63 </OL>
  64
  65 <A NAME="fig7-1">
  66 <IMG align=center SRC="fig7-1.gif" border=0>
  67
  68 <P>
  69 <HR>
  70 <P>
  71 <B>up:</B> <A HREF="c07.htm">
  72 Chapter 7 -- Multitasking</A><BR>
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  74 <B>next:</B> <A HREF="s07_02.htm">7.2  TSS Descriptor</A>
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