hw/i386.reference/s05_02.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Section 5.2</TITLE>
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   8 Chapter 5 -- Memory Management</A><BR>
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  11 <P>
  12 <HR>
  13 <P>
  14 <H1>5.2  Page Translation</H1>
  15 In the second phase of address transformation, the 80386 transforms a
  16 linear address into a physical address. This phase of address transformation
  17 implements the basic features needed for page-oriented virtual-memory
  18 systems and page-level protection.
  19 <P>
  20 The page-translation step is optional. Page translation is in effect only
  21 when the PG bit of CR0 is set. This bit is typically set by the operating
  22 system during software initialization. The PG bit must be set if the
  23 operating system is to implement multiple virtual 8086 tasks, page-oriented
  24 protection, or page-oriented virtual memory.
  25
  26 <H2>5.2.1  Page Frame</H2>
  27 A page frame is a 4K-byte unit of contiguous addresses of physical memory.
  28 Pages begin onbyte boundaries and are fixed in size.
  29
  30 <H2>5.2.2  Linear Address</H2>
  31 A linear address refers indirectly to a physical address by specifying a
  32 page table, a page within that table, and an offset within that page.
  33 <A HREF="#fig5-8">Figure 5-8</A>
  34   shows the format of a linear address.
  35 <P>
  36
  37 <A HREF="#fig5-9">Figure 5-9</A>
  38   shows how the processor converts the DIR, PAGE, and OFFSET
  39 fields of a linear address into the physical address by consulting two
  40 levels of page tables. The addressing mechanism uses the DIR field as an
  41 index into a page directory, uses the PAGE field as an index into the page
  42 table determined by the page directory, and uses the OFFSET field to address
  43 a byte within the page determined by the page table.
  44 <P>
  45 <A NAME="fig5-8">
  46 <IMG align=center SRC="fig5-8.gif" border=0>
  47 <P>
  48 <HR>
  49 <P>
  50 <A NAME="fig5-9">
  51 <IMG align=center SRC="fig5-9.gif" border=0>
  52 <P>
  53 <H2>5.2.3  Page Tables</H2>
  54 A page table is simply an array of 32-bit page specifiers. A page table is
  55 itself a page, and therefore contains 4 Kilobytes of memory or at most 1K
  56 32-bit entries.
  57 <P>
  58 Two levels of tables are used to address a page of memory. At the higher
  59 level is a page directory. The page directory addresses up to 1K page tables
  60 of the second level. A page table of the second level addresses up to 1K
  61 pages. All the tables addressed by one page directory, therefore, can
  62 address 1M pages (2^(20)). Because each page contains 4K bytes 2^(12)
  63 bytes), the tables of one page directory can span the entire physical
  64 address space of the 80386 (2^(20) times 2^(12) = 2^(32)).
  65 <P>
  66 The physical address of the current page directory is stored in the CPU
  67 register CR3, also called the page directory base register (PDBR). Memory
  68 management software has the option of using one page directory for all
  69 tasks, one page directory for each task, or some combination of the two.
  70 Refer to
  71 <A HREF="c10.htm">Chapter 10</A>
  72    for information on initialization of CR3 . Refer to
  73
  74 <A HREF="c07.htm">Chapter 7</A>
  75    to see how CR3 can change for each task .
  76
  77 <H2>5.2.4  Page-Table Entries</H2>
  78 Entries in either level of page tables have the same format.
  79 <A HREF="#fig5-10">Figure 5-10</A>
  80
  81 illustrates this format.
  82
  83 <H3>5.2.4.1  Page Frame Address</H3>
  84 The page frame address specifies the physical starting address of a page.
  85 Because pages are located on 4K boundaries, the low-order 12 bits are always
  86 zero. In a page directory, the page frame address is the address of a page
  87 table. In a second-level page table, the page frame address is the address
  88 of the page frame that contains the desired memory operand.
  89
  90 <H3>5.2.4.2  Present Bit</H3>
  91 The Present bit indicates whether a page table entry can be used in address
  92 translation. P=1 indicates that the entry can be used.
  93 <P>
  94 When P=0 in either level of page tables, the entry is not valid for address
  95 translation, and the rest of the entry is available for software use; none
  96 of the other bits in the entry is tested by the hardware.
  97 <A HREF="#fig5-11">Figure 5-11</A>
  98
  99 illustrates the format of a page-table entry when P=0.
 100 <P>
 101 If P=0 in either level of page tables when an attempt is made to use a
 102 page-table entry for address translation, the processor signals a page
 103 exception. In software systems that support paged virtual memory, the
 104 page-not-present exception handler can bring the required page into physical
 105 memory. The instruction that caused the exception can then be reexecuted.
 106 Refer to
 107 <A HREF="c09.htm">Chapter 9</A>
 108    for more information on exception handlers .
 109 <P>
 110 Note that there is no present bit for the page directory itself. The page
 111 directory may be not-present while the associated task is suspended, but the
 112 operating system must ensure that the page directory indicated by the CR3
 113 image in the TSS is present in physical memory before the task is
 114 dispatched . Refer to
 115 <A HREF="c07.htm">Chapter 7</A>
 116    for an explanation of the TSS and task
 117 dispatching.
 118 <P>
 119 <A NAME="fig5-10">
 120 <IMG align=center SRC="fig5-10.gif" border=0>
 121 <P>
 122 <HR>
 123 <P>
 124 <A NAME="fig5-11">
 125 <IMG align=center SRC="fig5-11.gif" border=0>
 126 <P>
 127 <H3>5.2.4.3  Accessed and Dirty Bits</H3>
 128 These bits provide data about page usage in both levels of the page tables.
 129 With the exception of the dirty bit in a page directory entry, these bits
 130 are set by the hardware; however, the processor does not clear any of these
 131 bits.
 132 <P>
 133 The processor sets the corresponding accessed bits in both levels of page
 134 tables to one before a read or write operation to a page.
 135 <P>
 136 The processor sets the dirty bit in the second-level page table to one
 137 before a write to an address covered by that page table entry. The dirty bit
 138 in directory entries is undefined.
 139 <P>
 140 An operating system that supports paged virtual memory can use these bits
 141 to determine what pages to eliminate from physical memory when the demand
 142 for memory exceeds the physical memory available. The operating system is
 143 responsible for testing and clearing these bits.
 144 <P>
 145 Refer to
 146 <A HREF="c11.htm">Chapter 11</A>
 147    for how the 80386 coordinates updates to the accessed
 148 and dirty bits in multiprocessor systems.
 149
 150 <H3>5.2.4.4  Read/Write and User/Supervisor Bits</H3>
 151 These bits are not used for address translation, but are used for
 152 page-level protection, which the processor performs at the same time as
 153 address translation . Refer to
 154 <A HREF="c06.htm">Chapter 6</A>
 155    where protection is discussed in
 156 detail.
 157
 158 <H2>5.2.5  Page Translation Cache</H2>
 159 For greatest efficiency in address translation, the processor stores the
 160 most recently used page-table data in an on-chip cache. Only if the
 161 necessary paging information is not in the cache must both levels of page
 162 tables be referenced.
 163 <P>
 164 The existence of the page-translation cache is invisible to applications
 165 programmers but not to systems programmers; operating-system programmers
 166 must flush the cache whenever the page tables are changed. The
 167 page-translation cache can be flushed by either of two methods:
 168 <OL>
 169 <LI> By reloading CR3 with a <A HREF="MOVRS.htm">MOV</A> instruction;
 170 for example:
 171 <PRE>
 172 <A HREF="MOVRS.htm">MOV</A> CR3, EAX
 173 </PRE>
 174
 175 <LI> By performing a task switch to a TSS that has a different CR3 image
 176 than the current TSS . (Refer to
 177 <A HREF="c07.htm">Chapter 7</A>
 178    for more information on
 179 task switching.)
 180 </OL>
 181 <P>
 182 <HR>
 183 <P>
 184 <B>up:</B> <A HREF="c05.htm">
 185 Chapter 5 -- Memory Management</A><BR>
 186 <B>prev:</B> <A HREF="s05_01.htm">5.1  Segment Translation</A><BR>
 187 <B>next:</B> <A HREF="s05_03.htm">5.3  Combining Segment and Page Translation</A>
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