hw/i386.reference/s04_02.htm

   1 <!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
   2 <HTML>
   3 <HEAD>
   4 <TITLE>80386 Programmer's Reference Manual -- Section 4.2</TITLE>
   5 </HEAD>
   6 <BODY>
   7 <B>up:</B> <A HREF="c04.htm">
   8 Chapter 4 -- Systems Architecture</A><BR>
   9 <B>prev:</B> <A HREF="s04_01.htm">4.1  Systems Registers</A><BR>
  10 <B>next:</B> <A HREF="c05.htm">Chapter 5 -- Memory Management</A>
  11 <P>
  12 <HR>
  13 <P>
  14 <H1>4.2  Systems Instructions</H1>
  15 Systems instructions deal with such functions as:
  16 <OL>
  17 <LI> Verification of pointer parameters (refer to
  18 <A HREF="c06.htm">Chapter 6</A>):
  19 <UL>
  20 <LI><A HREF="ARPL.htm">ARPL> -- Adjust RPL</A>
  21 <LI><A HREF="LAR.htm">LAR -- Load Access Rights</A>
  22 <LI><A HREF="LSL.htm">LSL -- Load Segment Limit</A>
  23 <LI><A HREF="VERR.htm">VERR -- Verify for Reading</A>
  24 <LI><A HREF="VERR.htm">VERW -- Verify for Writing</A>
  25 </UL>
  26 <P>
  27 <LI> Addressing descriptor tables (refer to
  28 <A HREF="c05.htm">Chapter 5</A>):
  29 <UL>
  30 <LI><A HREF="LLDT.htm">LLDT -- Load LDT Register</A>
  31 <LI><A HREF="SLDT.htm">SLDT -- Store LDT Register</A>
  32 <LI><A HREF="LGDT.htm">LGDT -- Load GDT Register</A>
  33 <LI><A HREF="SGDT.htm">SGDT -- Store GDT Register</A>
  34 </UL>
  35 <P>
  36 <LI> Multitasking (refer to
  37 <A HREF="c07.htm">Chapter 7</A>):
  38 <UL>
  39 <LI><A HREF="LTR.htm">LTR -- Load Task Register</A>
  40 <LI><A HREF="STR.htm">STR -- Store Task Register</A>
  41 </UL>
  42 <P>
  43 <LI> Coprocessing and Multiprocessing (refer to
  44 <A HREF="c11.htm">Chapter 11</A>):
  45 <UL>
  46 <LI><A HREF="CLTS.htm">CLTS -- Clear Task-Switched Flag</A>
  47 <LI>ESC -- Escape instructions
  48 <LI><A HREF="WAIT.htm">WAIT -- Wait until Coprocessor not Busy</A>
  49 <LI><A HREF="LOCK.htm">LOCK -- Assert Bus-Lock Signal</A>
  50 </UL>
  51 <P>
  52 <LI> Input and Output (refer to
  53 <A HREF="c08.htm">Chapter 8</A>):
  54 <UL>
  55 <LI><A HREF="IN.htm">IN -- Input</A>
  56 <LI><A HREF="OUT.htm">OUT -- Output</A>
  57 <LI><A HREF="INS.htm">INS -- Input String</A>
  58 <LI><A HREF="OUTS.htm">OUTS -- Output String</A>
  59 </UL>
  60 <P>
  61 <LI> Interrupt control (refer to
  62 <A HREF="c09.htm">Chapter 9</A>):
  63 <UL>
  64 <LI><A HREF="CLI.htm">CLI -- Clear Interrupt-Enable Flag</A>
  65 <LI><A HREF="STI.htm">STI -- Set Interrupt-Enable Flag</A>
  66 <LI><A HREF="LGDT.htm">LIDT -- Load IDT Register</A>
  67 <LI><A HREF="SGDT.htm">SIDT -- Store IDT Register</A>
  68 </UL>
  69 <P>
  70 <LI> Debugging (refer to
  71 <A HREF="c12.htm">Chapter 12</A>):
  72 <UL>
  73 <LI><A HREF="MOVRS.htm">MOV -- Move to and from debug registers</A>
  74 </UL>
  75 <P>
  76 <LI> TLB testing (refer to
  77 <A HREF="c10.htm">Chapter 10</A>):
  78 <UL>
  79 <LI><A HREF="MOVRS.htm">MOV -- Move to and from test registers</A>
  80 </UL>
  81 <P>
  82 <LI> System Control:
  83 <UL>
  84 <LI><A HREF="SMSW.htm">SMSW -- Set MSW</A>
  85 <LI><A HREF="LMSW.htm">LMSW -- Load MSW</A>
  86 <LI><A HREF="HLT.htm">HLT -- Halt Processor</A>
  87 <LI><A HREF="MOVRS.htm">MOV -- Move to and from control registers</A>
  88 </UL>
  89 </OL>
  90 The instructions <A HREF="SMSW.htm">SMSW</A> and <A HREF="LMSW.htm">LMSW</A>
  91 are provided for compatibility with the
  92 80286 processor.  80386 programs access the MSW in CR0 via variants of the
  93 <A HREF="MOVRS.htm">MOV</A> instruction.
  94 <A HREF="HLT.htm">HLT</A> stops the processor until receipt of an INTR or RESET
  95 signal.
  96 <P>
  97 In addition to the chapters cited above, detailed information about each of
  98 these instructions can be found in the instruction reference chapter,
  99
 100 <A HREF="c17.htm">Chapter 17</A>
 101 <P>
 102 <HR>
 103 <P>
 104 <B>up:</B> <A HREF="c04.htm">
 105 Chapter 4 -- Systems Architecture</A><BR>
 106 <B>prev:</B> <A HREF="s04_01.htm">4.1  Systems Registers</A><BR>
 107 <B>next:</B> <A HREF="c05.htm">Chapter 5 -- Memory Management</A>
 108 </BODY>