firmware/target/mips/ingenic_jz47xx/usb-jz4740.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2008 by Maurus Cuelenaere
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "config.h"
  23 /*#define LOGF_ENABLE*/
  24 #include "logf.h"
  25 #include "system.h"
  26 #include "usb_ch9.h"
  27 #include "usb_drv.h"
  28 #include "usb_core.h"
  29 #include "jz4740.h"
  30 #include "thread.h"
  31
  32 /*
  33     The Jz4740 USB controller is called MUSBHSFC in the datasheet.
  34     It also seems to be a more generic controller, with support for
  35     up to 15 endpoints (the Jz4740 only has 5).
  36 */
  37
  38 #define EP_BUF_LEFT(ep)  ((ep)->length - (ep)->sent)
  39 #define EP_PTR(ep)       ((void*)((unsigned int)(ep)->buf + (ep)->sent))
  40 #define EP_NUMBER(ep)    (((int)(ep) - (int)&endpoints[0])/sizeof(struct usb_endpoint))
  41 #define EP_NUMBER2(ep)   (EP_NUMBER((ep))/2)
  42 #define TOTAL_EP()       (sizeof(endpoints)/sizeof(struct usb_endpoint))
  43 #define EP_IS_IN(ep)     (EP_NUMBER((ep))%2)
  44
  45 enum ep_type
  46 {
  47     ep_control,
  48     ep_bulk,
  49     ep_interrupt,
  50     ep_isochronous
  51 };
  52
  53 struct usb_endpoint
  54 {
  55     void *buf;
  56     size_t length;
  57     union
  58     {
  59         size_t sent;
  60         size_t received;
  61     };
  62     bool busy;
  63
  64     const enum ep_type type;
  65     const bool use_dma;
  66
  67     const long fifo_addr;
  68     unsigned short fifo_size;
  69
  70     bool wait;
  71     struct semaphore complete;
  72 };
  73
  74 static unsigned char ep0_rx_buf[64];
  75 static struct usb_endpoint endpoints[] =
  76 {
  77     { .type = ep_control,   .fifo_addr = USB_FIFO_EP0, .fifo_size = 64 },
  78     { .type = ep_control,   .fifo_addr = USB_FIFO_EP0, .buf = &ep0_rx_buf },
  79     { .type = ep_bulk,      .fifo_addr = USB_FIFO_EP1, .fifo_size = 512 },
  80     { .type = ep_bulk,      .fifo_addr = USB_FIFO_EP1, .fifo_size = 512 },
  81     { .type = ep_interrupt, .fifo_addr = USB_FIFO_EP2, .fifo_size = 64 },
  82 };
  83
  84 static inline void select_endpoint(int ep)
  85 {
  86     REG_USB_REG_INDEX = ep;
  87 }
  88
  89 static void readFIFO(struct usb_endpoint *ep, unsigned int size)
  90 {
  91     logf("%s(EP%d, %d)", __func__, EP_NUMBER2(ep), size);
  92
  93     register unsigned char *ptr = (unsigned char*)EP_PTR(ep);
  94     register unsigned int *ptr32 = (unsigned int*)ptr;
  95     register unsigned int s = size >> 2;
  96     register unsigned int x;
  97
  98     if(size > 0)
  99     {
 100         if( ((unsigned int)ptr & 3) == 0 )
 101         {
 102             while(s--)
 103                 *ptr32++ = REG32(ep->fifo_addr);
 104
 105             ptr = (unsigned char*)ptr32;
 106         }
 107         else
 108         {
 109             while(s--)
 110             {
 111                 x = REG32(ep->fifo_addr);
 112                 *ptr++ = x & 0xFF; x >>= 8;
 113                 *ptr++ = x & 0xFF; x >>= 8;
 114                 *ptr++ = x & 0xFF; x >>= 8;
 115                 *ptr++ = x;
 116             }
 117         }
 118
 119         s = size & 3;
 120         while(s--)
 121             *ptr++ = REG8(ep->fifo_addr);
 122     }
 123 }
 124
 125 static void writeFIFO(struct usb_endpoint *ep, size_t size)
 126 {
 127     logf("%s(EP%d, %d)", __func__, EP_NUMBER2(ep), size);
 128
 129     register unsigned int *d32 = (unsigned int *)EP_PTR(ep);
 130     register size_t s = size >> 2;
 131
 132     if(size > 0)
 133     {
 134         while (s--)
 135             REG32(ep->fifo_addr) = *d32++;
 136
 137         if( (s = size & 3) )
 138         {
 139             register unsigned char *d8 = (unsigned char *)d32;
 140             while (s--)
 141                 REG8(ep->fifo_addr) = *d8++;
 142         }
 143     }
 144 }
 145
 146 static void flushFIFO(struct usb_endpoint *ep)
 147 {
 148     logf("%s(%d)", __func__, EP_NUMBER(ep));
 149
 150     switch (ep->type)
 151     {
 152         case ep_control:
 153         break;
 154
 155         case ep_bulk:
 156         case ep_interrupt:
 157         case ep_isochronous:
 158             if(EP_IS_IN(ep))
 159                 REG_USB_REG_INCSR |= (USB_INCSR_FF | USB_INCSR_CDT);
 160             else
 161                 REG_USB_REG_OUTCSR |= (USB_OUTCSR_FF | USB_OUTCSR_CDT);
 162         break;
 163     }
 164 }
 165
 166 static inline void ep_transfer_completed(struct usb_endpoint* ep)
 167 {
 168     ep->sent   = 0;
 169     ep->length = 0;
 170     ep->buf    = NULL;
 171     ep->busy   = false;
 172     if(ep->wait)
 173         semaphore_release(&ep->complete);
 174 }
 175
 176 static void EP0_send(void)
 177 {
 178     struct usb_endpoint* ep = &endpoints[0];
 179     unsigned int length;
 180     unsigned char csr0;
 181
 182     select_endpoint(0);
 183     csr0 = REG_USB_REG_CSR0;
 184
 185     if(ep->sent == 0)
 186         length = MIN(ep->length, ep->fifo_size);
 187     else
 188         length = MIN(EP_BUF_LEFT(ep), ep->fifo_size);
 189
 190     writeFIFO(ep, length);
 191     ep->sent += length;
 192
 193     if(ep->sent >= ep->length)
 194     {
 195         REG_USB_REG_CSR0 = (csr0 | USB_CSR0_INPKTRDY | USB_CSR0_DATAEND); /* Set data end! */
 196         usb_core_transfer_complete(0, USB_DIR_IN, 0, ep->sent);
 197         ep_transfer_completed(ep);
 198     }
 199     else
 200         REG_USB_REG_CSR0 = (csr0 | USB_CSR0_INPKTRDY);
 201 }
 202
 203 static void EP0_handler(void)
 204 {
 205     logf("%s()", __func__);
 206
 207     unsigned char csr0;
 208     struct usb_endpoint *ep_send = &endpoints[0];
 209     struct usb_endpoint *ep_recv = &endpoints[1];
 210
 211     /* Read CSR0 */
 212     select_endpoint(0);
 213     csr0 = REG_USB_REG_CSR0;
 214
 215     /* Check for SentStall:
 216         This bit is set when a STALL handshake is transmitted. The CPU should clear this bit.
 217      */
 218     if(csr0 & USB_CSR0_SENTSTALL)
 219     {
 220         REG_USB_REG_CSR0 = csr0 & ~USB_CSR0_SENTSTALL;
 221         return;
 222     }
 223
 224     /* Check for SetupEnd:
 225         This bit will be set when a control transaction ends before the DataEnd bit has been set.
 226         An interrupt will be generated and the FIFO flushed at this time.
 227         The bit is cleared by the CPU writing a 1 to the ServicedSetupEnd bit.
 228      */
 229     if(csr0 & USB_CSR0_SETUPEND)
 230     {
 231         REG_USB_REG_CSR0 = csr0 | USB_CSR0_SVDSETUPEND;
 232         return;
 233     }
 234
 235     /* Call relevant routines for endpoint 0 state */
 236     if(ep_send->busy)
 237         EP0_send();
 238     else if(csr0 & USB_CSR0_OUTPKTRDY)   /* There is a packet in the fifo */
 239     {
 240         readFIFO(ep_recv, REG_USB_REG_COUNT0);
 241         REG_USB_REG_CSR0 = csr0 | USB_CSR0_SVDOUTPKTRDY; /* clear OUTPKTRDY bit */
 242         usb_core_control_request((struct usb_ctrlrequest*)ep_recv->buf);
 243     }
 244 }
 245
 246 static void EPIN_handler(unsigned int endpoint)
 247 {
 248     struct usb_endpoint* ep = &endpoints[endpoint*2];
 249     unsigned int length, csr;
 250
 251     select_endpoint(endpoint);
 252     csr = REG_USB_REG_INCSR;
 253     logf("%s(%d): 0x%x", __func__, endpoint, csr);
 254
 255     if(!ep->busy)
 256     {
 257         logf("Entered EPIN handler without work!");
 258         return;
 259     }
 260
 261     if(csr & USB_INCSR_SENTSTALL)
 262     {
 263         REG_USB_REG_INCSR = csr & ~USB_INCSR_SENTSTALL;
 264         return;
 265     }
 266
 267     if(ep->use_dma)
 268         return;
 269
 270     if(csr & USB_INCSR_FFNOTEMPT)
 271     {
 272         logf("FIFO is not empty! 0x%x", csr);
 273         return;
 274     }
 275
 276     logf("EP%d: %d -> %d", endpoint, ep->sent, ep->length);
 277
 278     if(ep->sent == 0)
 279         length = MIN(ep->length, ep->fifo_size);
 280     else
 281         length = MIN(EP_BUF_LEFT(ep), ep->fifo_size);
 282
 283     writeFIFO(ep, length);
 284     REG_USB_REG_INCSR = csr | USB_INCSR_INPKTRDY;
 285     ep->sent += length;
 286
 287     if(ep->sent >= ep->length)
 288     {
 289         usb_core_transfer_complete(endpoint, USB_DIR_IN, 0, ep->sent);
 290         ep_transfer_completed(ep);
 291         logf("sent complete");
 292     }
 293 }
 294
 295 static void EPOUT_handler(unsigned int endpoint)
 296 {
 297     struct usb_endpoint* ep = &endpoints[endpoint*2+1];
 298     unsigned int size, csr;
 299
 300     if(!ep->busy)
 301     {
 302         logf("Entered EPOUT handler without work!");
 303         return;
 304     }
 305
 306     select_endpoint(endpoint);
 307     while((csr = REG_USB_REG_OUTCSR) & (USB_OUTCSR_SENTSTALL|USB_OUTCSR_OUTPKTRDY))
 308     {
 309         logf("%s(%d): 0x%x", __func__, endpoint, csr);
 310         if(csr & USB_OUTCSR_SENTSTALL)
 311         {
 312             logf("stall sent, flushing fifo..");
 313             flushFIFO(ep);
 314             REG_USB_REG_OUTCSR = csr & ~USB_OUTCSR_SENTSTALL;
 315             return;
 316         }
 317
 318         if(ep->use_dma)
 319             return;
 320
 321         if(csr & USB_OUTCSR_OUTPKTRDY) /* There is a packet in the fifo */
 322         {
 323             size = REG_USB_REG_OUTCOUNT;
 324
 325             readFIFO(ep, size);
 326             ep->received += size;
 327
 328             /*if(csr & USB_OUTCSR_FFFULL)
 329                 csr &= ~USB_OUTCSR_FFFULL;*/
 330
 331             REG_USB_REG_OUTCSR = csr & ~USB_OUTCSR_OUTPKTRDY;
 332
 333             logf("received: %d max length: %d", ep->received, ep->length);
 334
 335             if(size < ep->fifo_size || ep->received >= ep->length)
 336             {
 337                 usb_core_transfer_complete(endpoint, USB_DIR_OUT, 0, ep->received);
 338                 ep_transfer_completed(ep);
 339                 logf("receive transfer_complete");
 340             }
 341         }
 342     }
 343 }
 344
 345 static void EPDMA_handler(int number)
 346 {
 347     int endpoint = -1;
 348     unsigned int size = 0;
 349
 350     if(number == USB_INTR_DMA_BULKIN)
 351         endpoint = (REG_USB_REG_CNTL1 >> 4) & 0xF;
 352     else if(number == USB_INTR_DMA_BULKOUT)
 353         endpoint = (REG_USB_REG_CNTL2 >> 4) & 0xF;
 354
 355     struct usb_endpoint* ep = &endpoints[endpoint];
 356     logf("DMA_BULK%d %d", number, endpoint);
 357
 358     if(number == USB_INTR_DMA_BULKIN)
 359         size = (unsigned int)ep->buf - REG_USB_REG_ADDR1;
 360     else if(number == USB_INTR_DMA_BULKOUT)
 361         size = (unsigned int)ep->buf - REG_USB_REG_ADDR2;
 362
 363     if(number == USB_INTR_DMA_BULKOUT)
 364     {
 365         /* Disable DMA */
 366         REG_USB_REG_CNTL2 = 0;
 367
 368         __dcache_invalidate_all();
 369
 370         select_endpoint(endpoint);
 371         /* Read out last packet manually */
 372         unsigned int lpack_size = REG_USB_REG_OUTCOUNT;
 373         if(lpack_size > 0)
 374         {
 375             ep->buf += ep->length - lpack_size;
 376             readFIFO(ep, lpack_size);
 377             REG_USB_REG_OUTCSR &= ~USB_OUTCSR_OUTPKTRDY;
 378         }
 379     }
 380     else if(number == USB_INTR_DMA_BULKIN && size % ep->fifo_size)
 381     {
 382         /* If the last packet is less than MAXP, set INPKTRDY manually */
 383         REG_USB_REG_INCSR |= USB_INCSR_INPKTRDY;
 384     }
 385
 386     usb_core_transfer_complete(endpoint, EP_IS_IN(ep) ? USB_DIR_IN : USB_DIR_OUT,
 387                                0, ep->length);
 388     ep_transfer_completed(ep);
 389 }
 390
 391 static void setup_endpoint(struct usb_endpoint *ep)
 392 {
 393     int csr, csrh;
 394
 395     select_endpoint(EP_NUMBER2(ep));
 396
 397     ep->busy = false;
 398     ep->wait = false;
 399     ep->sent = 0;
 400     ep->length = 0;
 401
 402     if(ep->type == ep_bulk)
 403     {
 404         if(REG_USB_REG_POWER & USB_POWER_HSMODE)
 405             ep->fifo_size = 512;
 406         else
 407             ep->fifo_size = 64;
 408     }
 409
 410     if(EP_IS_IN(ep))
 411     {
 412         csr = (USB_INCSR_FF | USB_INCSR_CDT);
 413         csrh = USB_INCSRH_MODE;
 414
 415         if(ep->use_dma)
 416             csrh |= (USB_INCSRH_DMAREQENAB | USB_INCSRH_AUTOSET | USB_INCSRH_DMAREQMODE);
 417
 418         if(ep->type == ep_interrupt)
 419             csrh |= USB_INCSRH_FRCDATATOG;
 420
 421         REG_USB_REG_INMAXP   = ep->fifo_size;
 422         REG_USB_REG_INCSR    = csr;
 423         REG_USB_REG_INCSRH   = csrh;
 424         REG_USB_REG_INTRINE |= USB_INTR_EP(EP_NUMBER2(ep));
 425     }
 426     else
 427     {
 428         csr = (USB_OUTCSR_FF | USB_OUTCSR_CDT);
 429         csrh = 0;
 430
 431         if(ep->type == ep_interrupt)
 432             csrh |= USB_OUTCSRH_DNYT;
 433
 434         if(ep->use_dma)
 435             csrh |= (USB_OUTCSRH_DMAREQENAB | USB_OUTCSRH_AUTOCLR | USB_OUTCSRH_DMAREQMODE);
 436
 437         REG_USB_REG_OUTMAXP   = ep->fifo_size;
 438         REG_USB_REG_OUTCSR    = csr;
 439         REG_USB_REG_OUTCSRH   = csrh;
 440         REG_USB_REG_INTROUTE |= USB_INTR_EP(EP_NUMBER2(ep));
 441     }
 442 }
 443
 444 static void udc_reset(void)
 445 {
 446     /* From the datasheet:
 447
 448        When a reset condition is detected on the USB, the controller performs the following actions:
 449            * Sets FAddr to 0.
 450            * Sets Index to 0.
 451            * Flushes all endpoint FIFOs.
 452            * Clears all control/status registers.
 453            * Enables all endpoint interrupts.
 454            * Generates a Reset interrupt.
 455     */
 456
 457     logf("%s()", __func__);
 458
 459     unsigned int i;
 460
 461     /* Disable interrupts */
 462     REG_USB_REG_INTRINE  = 0;
 463     REG_USB_REG_INTROUTE = 0;
 464     REG_USB_REG_INTRUSBE = 0;
 465
 466     /* Disable DMA */
 467     REG_USB_REG_CNTL1 = 0;
 468     REG_USB_REG_CNTL2 = 0;
 469
 470     /* High speed, softconnect and suspend/resume */
 471     REG_USB_REG_POWER = (USB_POWER_SOFTCONN | USB_POWER_HSENAB | USB_POWER_SUSPENDM);
 472
 473     /* Reset EP0 */
 474     select_endpoint(0);
 475     REG_USB_REG_CSR0 = (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_SVDSETUPEND);
 476
 477     /* Reset other endpoints */
 478     for(i=2; i<TOTAL_EP(); i++)
 479         setup_endpoint(&endpoints[i]);
 480
 481     /* Enable interrupts */
 482     REG_USB_REG_INTRINE  |= USB_INTR_EP0;
 483     REG_USB_REG_INTRUSBE |= USB_INTR_RESET;
 484
 485     usb_core_bus_reset();
 486 }
 487
 488 /* Interrupt handler */
 489 void UDC(void)
 490 {
 491     /* Read interrupt registers */
 492     unsigned char    intrUSB = REG_USB_REG_INTRUSB & 0x07; /* Mask SOF */
 493     unsigned short   intrIn  = REG_USB_REG_INTRIN;
 494     unsigned short   intrOut = REG_USB_REG_INTROUT;
 495     unsigned char    intrDMA = REG_USB_REG_INTR;
 496
 497     logf("%x %x %x %x", intrUSB, intrIn, intrOut, intrDMA);
 498
 499     /* EPIN & EPOUT are all handled in DMA */
 500     if(intrIn & USB_INTR_EP0)
 501         EP0_handler();
 502     if(intrIn & USB_INTR_INEP1)
 503         EPIN_handler(1);
 504     if(intrIn & USB_INTR_INEP2)
 505         EPIN_handler(2);
 506     if(intrOut & USB_INTR_OUTEP1)
 507         EPOUT_handler(1);
 508     if(intrOut & USB_INTR_OUTEP2)
 509         EPOUT_handler(2);
 510     if(intrUSB & USB_INTR_RESET)
 511         udc_reset();
 512     if(intrUSB & USB_INTR_SUSPEND)
 513     {
 514         logf("USB suspend");
 515     }
 516     if(intrUSB & USB_INTR_RESUME)
 517     {
 518         logf("USB resume");
 519     }
 520     if(intrDMA & USB_INTR_DMA_BULKIN)
 521         EPDMA_handler(USB_INTR_DMA_BULKIN);
 522     if(intrDMA & USB_INTR_DMA_BULKOUT)
 523         EPDMA_handler(USB_INTR_DMA_BULKOUT);
 524 }
 525
 526 bool usb_drv_stalled(int endpoint, bool in)
 527 {
 528     endpoint &= 0x7F;
 529
 530     logf("%s(%d, %s)", __func__, endpoint, in?"IN":"OUT");
 531
 532     select_endpoint(endpoint);
 533
 534     if(endpoint == EP_CONTROL)
 535         return (REG_USB_REG_CSR0 & USB_CSR0_SENDSTALL) != 0;
 536     else
 537     {
 538         if(in)
 539             return (REG_USB_REG_INCSR & USB_INCSR_SENDSTALL) != 0;
 540         else
 541             return (REG_USB_REG_OUTCSR & USB_OUTCSR_SENDSTALL) != 0;
 542     }
 543 }
 544
 545 void usb_drv_stall(int endpoint, bool stall, bool in)
 546 {
 547     endpoint &= 0x7F;
 548
 549     logf("%s(%d,%s,%s)", __func__, endpoint, stall?"Y":"N", in?"IN":"OUT");
 550
 551     select_endpoint(endpoint);
 552
 553     if(endpoint == EP_CONTROL)
 554     {
 555         if(stall)
 556             REG_USB_REG_CSR0 |= USB_CSR0_SENDSTALL;
 557         else
 558             REG_USB_REG_CSR0 &= ~USB_CSR0_SENDSTALL;
 559     }
 560     else
 561     {
 562         if(in)
 563         {
 564             if(stall)
 565                 REG_USB_REG_INCSR |= USB_INCSR_SENDSTALL;
 566             else
 567                 REG_USB_REG_INCSR = (REG_USB_REG_INCSR & ~USB_INCSR_SENDSTALL) | USB_INCSR_CDT;
 568         }
 569         else
 570         {
 571             if(stall)
 572                 REG_USB_REG_OUTCSR |= USB_OUTCSR_SENDSTALL;
 573             else
 574                 REG_USB_REG_OUTCSR = (REG_USB_REG_OUTCSR & ~USB_OUTCSR_SENDSTALL) | USB_OUTCSR_CDT;
 575         }
 576     }
 577 }
 578
 579 #define GPIO_UDC_DETE      (32 * 3 + 28) /* A18 = ADP_CHK */
 580 #define IRQ_GPIO_UDC_DETE  (IRQ_GPIO_0 + GPIO_UDC_DETE)
 581 #ifndef ONDA_VX767
 582 # define USB_GPIO_IRQ GPIO124
 583 #endif
 584
 585 int usb_detect(void)
 586 {
 587     return (__gpio_get_pin(GPIO_UDC_DETE) == 1)
 588         ? USB_INSERTED : USB_EXTRACTED;
 589 }
 590
 591 void usb_init_device(void)
 592 {
 593 #ifdef ONDA_VX767
 594     REG_GPIO_PXFUNS(3) = 0x10000000;
 595     REG_GPIO_PXSELS(3) = 0x10000000;
 596     REG_GPIO_PXPES(3)  = 0x10000000;
 597     __gpio_as_input(GPIO_UDC_DETE);
 598 #else
 599     REG_GPIO_PXPES(3)  = 0x10000000;
 600     __gpio_as_irq_rise_edge(GPIO_UDC_DETE);
 601 #endif
 602
 603 #ifdef USB_GPIO_IRQ
 604     system_enable_irq(IRQ_GPIO_UDC_DETE);
 605 #endif
 606     system_enable_irq(IRQ_UDC);
 607
 608     for(unsigned i=0; i<TOTAL_EP(); i++)
 609         semaphore_init(&endpoints[i].complete, 1, 0);
 610 }
 611
 612 #ifdef USB_GPIO_IRQ
 613 static unsigned long last_tick;
 614 void USB_GPIO_IRQ(void)
 615 {
 616     /* Prevent enabled-disabled bouncing */
 617     if(current_tick - last_tick > HZ/16)
 618     {
 619         usb_status_event(usb_detect());
 620         last_tick = current_tick;
 621     }
 622 }
 623 #endif
 624
 625 void usb_enable(bool on)
 626 {
 627     if(on)
 628         usb_core_init();
 629     else
 630         usb_core_exit();
 631 }
 632
 633 void usb_attach(void)
 634 {
 635     usb_enable(true);
 636 }
 637
 638 void usb_drv_init(void)
 639 {
 640     logf("%s()", __func__);
 641
 642     /* Set this bit to allow the UDC entering low-power mode when
 643      * there are no actions on the USB bus.
 644      * UDC still works during this bit was set.
 645      */
 646     //__cpm_stop_udc();
 647     __cpm_start_udc();
 648
 649     /* Enable the USB PHY */
 650     REG_CPM_SCR |= CPM_SCR_USBPHY_ENABLE;
 651
 652     /* Dis- and reconnect from USB */
 653     REG_USB_REG_POWER &= ~USB_POWER_SOFTCONN;
 654     REG_USB_REG_POWER |= USB_POWER_SOFTCONN;
 655
 656     udc_reset();
 657 }
 658
 659 void usb_drv_exit(void)
 660 {
 661     logf("%s()", __func__);
 662
 663     /* Disable interrupts */
 664     REG_USB_REG_INTRINE  = 0;
 665     REG_USB_REG_INTROUTE = 0;
 666     REG_USB_REG_INTRUSBE = 0;
 667
 668     /* Disable DMA */
 669     REG_USB_REG_CNTL1 = 0;
 670     REG_USB_REG_CNTL2 = 0;
 671
 672     /* Disconnect from USB */
 673     REG_USB_REG_POWER &= ~USB_POWER_SOFTCONN;
 674
 675     /* Disable the USB PHY */
 676     REG_CPM_SCR &= ~CPM_SCR_USBPHY_ENABLE;
 677
 678     __cpm_stop_udc();
 679 }
 680
 681 void usb_drv_set_address(int address)
 682 {
 683     logf("%s(%d)", __func__, address);
 684
 685     REG_USB_REG_FADDR = address;
 686 }
 687
 688 static void usb_drv_send_internal(struct usb_endpoint* ep, void* ptr, int length, bool blocking)
 689 {
 690     if(ep->type == ep_control && ptr == NULL && length == 0)
 691         return; /* ACK request, handled in the ISR */
 692
 693     int flags = disable_irq_save();
 694
 695     ep->buf = ptr;
 696     ep->sent = 0;
 697     ep->length = length;
 698     ep->busy = true;
 699     if(blocking)
 700         ep->wait = true;
 701
 702     if(ep->type == ep_control)
 703     {
 704         EP0_send();
 705     }
 706     else
 707     {
 708         if(ep->use_dma)
 709         {
 710             //dma_cache_wback_inv((unsigned long)ptr, length);
 711             __dcache_writeback_all();
 712             REG_USB_REG_ADDR1 = PHYSADDR((unsigned long)ptr);
 713             REG_USB_REG_COUNT1 = length;
 714             REG_USB_REG_CNTL1 = (USB_CNTL_INTR_EN | USB_CNTL_MODE_1 |
 715                                  USB_CNTL_DIR_IN  | USB_CNTL_ENA |
 716                                  USB_CNTL_EP(EP_NUMBER2(ep)) | USB_CNTL_BURST_16);
 717         }
 718         else
 719             EPIN_handler(EP_NUMBER2(ep));
 720     }
 721
 722     restore_irq(flags);
 723
 724     if(blocking)
 725     {
 726         semaphore_wait(&ep->complete, TIMEOUT_BLOCK);
 727         ep->wait = false;
 728     }
 729 }
 730
 731 int usb_drv_send_nonblocking(int endpoint, void* ptr, int length)
 732 {
 733     logf("%s(%d, 0x%x, %d)", __func__, endpoint, (int)ptr, length);
 734
 735     usb_drv_send_internal(&endpoints[(endpoint & 0x7F)*2], ptr, length, false);
 736
 737     return 0;
 738 }
 739
 740 int usb_drv_send(int endpoint, void* ptr, int length)
 741 {
 742     logf("%s(%d, 0x%x, %d)", __func__, endpoint, (int)ptr, length);
 743
 744     usb_drv_send_internal(&endpoints[(endpoint & 0x7F)*2], ptr, length, true);
 745
 746     return 0;
 747 }
 748
 749 int usb_drv_recv(int endpoint, void* ptr, int length)
 750 {
 751     int flags;
 752     struct usb_endpoint *ep;
 753     endpoint &= 0x7F;
 754
 755     logf("%s(%d, 0x%x, %d)", __func__, endpoint, (int)ptr, length);
 756
 757     if(endpoint == EP_CONTROL)
 758         return 0; /* all EP0 OUT transactions are handled within the ISR */
 759     else
 760     {
 761         flags = disable_irq_save();
 762         ep = &endpoints[endpoint*2+1];
 763
 764         ep->buf = ptr;
 765         ep->received = 0;
 766         ep->length = length;
 767         ep->busy = true;
 768         if(ep->use_dma)
 769         {
 770             //dma_cache_wback_inv((unsigned long)ptr, length);
 771             __dcache_writeback_all();
 772             REG_USB_REG_ADDR2 = PHYSADDR((unsigned long)ptr);
 773             REG_USB_REG_COUNT2 = length;
 774             REG_USB_REG_CNTL2 = (USB_CNTL_INTR_EN | USB_CNTL_MODE_1 |
 775                                  USB_CNTL_ENA | USB_CNTL_EP(endpoint) |
 776                                  USB_CNTL_BURST_16);
 777         }
 778         else
 779             EPOUT_handler(endpoint);
 780
 781         restore_irq(flags);
 782         return 0;
 783     }
 784 }
 785
 786 void usb_drv_set_test_mode(int mode)
 787 {
 788     logf("%s(%d)", __func__, mode);
 789
 790     switch(mode)
 791     {
 792         case 0:
 793             REG_USB_REG_TESTMODE &= ~USB_TEST_ALL;
 794             break;
 795         case 1:
 796             REG_USB_REG_TESTMODE |= USB_TEST_J;
 797             break;
 798         case 2:
 799             REG_USB_REG_TESTMODE |= USB_TEST_K;
 800             break;
 801         case 3:
 802             REG_USB_REG_TESTMODE |= USB_TEST_SE0NAK;
 803             break;
 804         case 4:
 805             REG_USB_REG_TESTMODE |= USB_TEST_PACKET;
 806             break;
 807     }
 808 }
 809
 810 int usb_drv_port_speed(void)
 811 {
 812     return (REG_USB_REG_POWER & USB_POWER_HSMODE) ? 1 : 0;
 813 }
 814
 815 void usb_drv_cancel_all_transfers(void)
 816 {
 817     logf("%s()", __func__);
 818
 819     unsigned int i, flags;
 820     flags = disable_irq_save();
 821
 822     for(i=0; i<TOTAL_EP(); i++)
 823     {
 824         if(i != 1) /* ep0 out needs special handling */
 825             endpoints[i].buf = NULL;
 826
 827         endpoints[i].sent = 0;
 828         endpoints[i].length = 0;
 829
 830         select_endpoint(i/2);
 831         flushFIFO(&endpoints[i]);
 832     }
 833     restore_irq(flags);
 834 }
 835
 836 void usb_drv_release_endpoint(int ep)
 837 {
 838     (void)ep;
 839     logf("%s(%d, %s)", __func__, (ep & 0x7F), (ep >> 7) ? "IN" : "OUT");
 840 }
 841
 842 int usb_drv_request_endpoint(int type, int dir)
 843 {
 844     logf("%s(%d, %s)", __func__, type, (dir == USB_DIR_IN) ? "IN" : "OUT");
 845
 846     dir  &= USB_ENDPOINT_DIR_MASK;
 847     type &= USB_ENDPOINT_XFERTYPE_MASK;
 848
 849     /* There are only 3+2 endpoints, so hardcode this ... */
 850     switch(type)
 851     {
 852         case USB_ENDPOINT_XFER_BULK:
 853             if(dir == USB_DIR_IN)
 854                 return (1 | USB_DIR_IN);
 855             else
 856                 return (1 | USB_DIR_OUT);
 857
 858         case USB_ENDPOINT_XFER_INT:
 859             if(dir == USB_DIR_IN)
 860                 return (2 | USB_DIR_IN);
 861
 862         default:
 863             return -1;
 864     }
 865 }