firmware/target/arm/imx233/power-imx233.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2011 by Amaury Pouly
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef __POWER_IMX233__
  22 #define __POWER_IMX233__
  23
  24 #include "system.h"
  25 #include "system-target.h"
  26 #include "cpu.h"
  27
  28 #define HW_POWER_BASE           0x80044000
  29
  30 #define HW_POWER_CTRL           (*(volatile uint32_t *)(HW_POWER_BASE + 0x0))
  31 #define HW_POWER_CTRL__ENIRQ_VBUS_VALID     (1 << 3)
  32 #define HW_POWER_CTRL__VBUSVALID_IRQ        (1 << 4)
  33 #define HW_POWER_CTRL__POLARITY_VBUSVALID   (1 << 5)
  34 #define HW_POWER_CTRL__ENIRQ_DC_OK          (1 << 14)
  35 #define HW_POWER_CTRL__DC_OK_IRQ            (1 << 15)
  36
  37 #define HW_POWER_5VCTRL         (*(volatile uint32_t *)(HW_POWER_BASE + 0x10))
  38 #define HW_POWER_5VCTRL__ENABLE_DCDC        (1 << 0)
  39 #define HW_POWER_5VCTRL__PWRUP_VBUS_CMPS    (1 << 1)
  40 #define HW_POWER_5VCTRL__VBUSVALID_5VDETECT (1 << 4)
  41 #define HW_POWER_5VCTRL__DCDC_XFER          (1 << 5)
  42 #define HW_POWER_5VCTRL__VBUSVALID_TRSH_BP  8
  43 #define HW_POWER_5VCTRL__VBUSVALID_TRSH_BM  (0x7 << 8)
  44 #define HW_POWER_5VCTRL__VBUSVALID_TRSH_2p9 (0 << 8)
  45 #define HW_POWER_5VCTRL__VBUSVALID_TRSH_4V  (1 << 8)
  46 #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT_BP   12
  47 #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT_BM   (0x3f << 12)
  48 #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__10mA    (1 << 12)
  49 #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__20mA    (1 << 13)
  50 #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__50mA    (1 << 14)
  51 #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__100mA   (1 << 15)
  52 #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__200mA   (1 << 16)
  53 #define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__400mA   (1 << 17)
  54 #define HW_POWER_5VCTRL__PWD_CHARGE_4P2     (1 << 20)
  55
  56 #define HW_POWER_MINPWR         (*(volatile uint32_t *)(HW_POWER_BASE + 0x20))
  57 #define HW_POWER_MINPWR__HALF_FETS  (1 << 5)
  58 #define HW_POWER_MINPWR__DOUBLE_FETS    (1 << 6)
  59
  60 #define HW_POWER_CHARGE         (*(volatile uint32_t *)(HW_POWER_BASE + 0x30))
  61 #define HW_POWER_CHARGE__BATTCHRG_I_BP  0
  62 #define HW_POWER_CHARGE__BATTCHRG_I_BM  0x3f
  63 #define HW_POWER_CHARGE__BATTCHRG_I__10mA   (1 << 0)
  64 #define HW_POWER_CHARGE__BATTCHRG_I__20mA   (1 << 1)
  65 #define HW_POWER_CHARGE__BATTCHRG_I__50mA   (1 << 2)
  66 #define HW_POWER_CHARGE__BATTCHRG_I__100mA  (1 << 3)
  67 #define HW_POWER_CHARGE__BATTCHRG_I__200mA  (1 << 4)
  68 #define HW_POWER_CHARGE__BATTCHRG_I__400mA  (1 << 5)
  69 #define HW_POWER_CHARGE__STOP_ILIMIT_BP 8
  70 #define HW_POWER_CHARGE__STOP_ILIMIT_BM 0xf00
  71 #define HW_POWER_CHARGE__STOP_ILIMIT__10mA  (1 << 8)
  72 #define HW_POWER_CHARGE__STOP_ILIMIT__20mA  (1 << 9)
  73 #define HW_POWER_CHARGE__STOP_ILIMIT__50mA  (1 << 10)
  74 #define HW_POWER_CHARGE__STOP_ILIMIT__100mA (1 << 11)
  75 #define HW_POWER_CHARGE__PWD_BATTCHRG   (1 << 16)
  76 #define HW_POWER_CHARGE__CHRG_STS_OFF   (1 << 19)
  77 #define HW_POWER_CHARGE__ENABLE_LOAD    (1 << 22)
  78
  79 #define HW_POWER_VDDDCTRL       (*(volatile uint32_t *)(HW_POWER_BASE + 0x40))
  80 #define HW_POWER_VDDDCTRL__TRG_BP   0
  81 #define HW_POWER_VDDDCTRL__TRG_BM   0x1f
  82 #define HW_POWER_VDDDCTRL__BO_OFFSET_BP 8
  83 #define HW_POWER_VDDDCTRL__BO_OFFSET_BM (0x7 << 8)
  84 #define HW_POWER_VDDDCTRL__TRG_STEP 25 /* mV */
  85 #define HW_POWER_VDDDCTRL__TRG_MIN  800 /* mV */
  86 #define HW_POWER_VDDDCTRL__LINREG_OFFSET_BP 16
  87 #define HW_POWER_VDDDCTRL__LINREG_OFFSET_BM (0x3 << 16)
  88 #define HW_POWER_VDDDCTRL__ENABLE_LINREG    (1 << 21)
  89
  90 #define HW_POWER_VDDACTRL       (*(volatile uint32_t *)(HW_POWER_BASE + 0x50))
  91 #define HW_POWER_VDDACTRL__TRG_BP   0
  92 #define HW_POWER_VDDACTRL__TRG_BM   0x1f
  93 #define HW_POWER_VDDACTRL__BO_OFFSET_BP 8
  94 #define HW_POWER_VDDACTRL__BO_OFFSET_BM (0x7 << 8)
  95 #define HW_POWER_VDDACTRL__TRG_STEP 25 /* mV */
  96 #define HW_POWER_VDDACTRL__TRG_MIN  1500 /* mV */
  97 #define HW_POWER_VDDACTRL__LINREG_OFFSET_BP 12
  98 #define HW_POWER_VDDACTRL__LINREG_OFFSET_BM (0x3 << 12)
  99 #define HW_POWER_VDDACTRL__ENABLE_LINREG    (1 << 17)
 100
 101 #define HW_POWER_VDDIOCTRL      (*(volatile uint32_t *)(HW_POWER_BASE + 0x60))
 102 #define HW_POWER_VDDIOCTRL__TRG_BP  0
 103 #define HW_POWER_VDDIOCTRL__TRG_BM  0x1f
 104 #define HW_POWER_VDDIOCTRL__BO_OFFSET_BP 8
 105 #define HW_POWER_VDDIOCTRL__BO_OFFSET_BM (0x7 << 8)
 106 #define HW_POWER_VDDIOCTRL__TRG_STEP    25 /* mV */
 107 #define HW_POWER_VDDIOCTRL__TRG_MIN 2800 /* mV */
 108 #define HW_POWER_VDDIOCTRL__LINREG_OFFSET_BP    12
 109 #define HW_POWER_VDDIOCTRL__LINREG_OFFSET_BM    (0x3 << 12)
 110
 111 #define HW_POWER_VDDMEMCTRL     (*(volatile uint32_t *)(HW_POWER_BASE + 0x70))
 112 #define HW_POWER_VDDMEMCTRL__TRG_BP  0
 113 #define HW_POWER_VDDMEMCTRL__TRG_BM  0x1f
 114 #define HW_POWER_VDDMEMCTRL__TRG_STEP    50 /* mV */
 115 #define HW_POWER_VDDMEMCTRL__TRG_MIN 1700 /* mV */
 116 #define HW_POWER_VDDMEMCTRL__ENABLE_LINREG  (1 << 8)
 117
 118 #define HW_POWER_DCDC4P2        (*(volatile uint32_t *)(HW_POWER_BASE + 0x80))
 119 #define HW_POWER_DCDC4P2__CMPTRIP_BP    0
 120 #define HW_POWER_DCDC4P2__CMPTRIP_BM    0x1f
 121 #define HW_POWER_DCDC4P2__CMPTRIP__0p85 0
 122 #define HW_POWER_DCDC4P2__ENABLE_DCDC   (1 << 22)
 123 #define HW_POWER_DCDC4P2__ENABLE_4P2    (1 << 23)
 124 #define HW_POWER_DCDC4P2__DROPOUT_CTRL_BP   28
 125 #define HW_POWER_DCDC4P2__DROPOUT_CTRL_BM   (0xf << 28)
 126 #define HW_POWER_DCDC4P2__DROPOUT_CTRL__200mV   (3 << 30)
 127 #define HW_POWER_DCDC4P2__DROPOUT_CTRL__HIGHER  (2 << 28)
 128
 129 #define HW_POWER_MISC           (*(volatile uint32_t *)(HW_POWER_BASE + 0x90))
 130 #define HW_POWER_MISC__SEL_PLLCLK   1
 131 #define HW_POWER_MISC__FREQSEL_BP   4
 132 #define HW_POWER_MISC__FREQSEL_BM   (0x7 << 4)
 133 #define HW_POWER_MISC__FREQSEL__RES         0
 134 #define HW_POWER_MISC__FREQSEL__20MHz       1
 135 #define HW_POWER_MISC__FREQSEL__24MHz       2
 136 #define HW_POWER_MISC__FREQSEL__19p2MHz     3
 137 #define HW_POWER_MISC__FREQSEL__14p4MHz     4
 138 #define HW_POWER_MISC__FREQSEL__18MHz       5
 139 #define HW_POWER_MISC__FREQSEL__21p6MHz     6
 140 #define HW_POWER_MISC__FREQSEL__17p28MHz    7
 141
 142 #define HW_POWER_LOOPCTRL       (*(volatile uint32_t *)(HW_POWER_BASE + 0xb0))
 143 #define HW_POWER_LOOPCTRL__DC_C_BP  0
 144 #define HW_POWER_LOOPCTRL__DC_C_BM  0x3
 145 #define HW_POWER_LOOPCTRL__DC_R_BP  4
 146 #define HW_POWER_LOOPCTRL__DC_R_BM  0xf0
 147 #define HW_POWER_LOOPCTRL__DC_FF_BP 8
 148 #define HW_POWER_LOOPCTRL__DC_FF_BM (0x7 << 8)
 149 #define HW_POWER_LOOPCTRL__EN_RCSCALE_BP    12
 150 #define HW_POWER_LOOPCTRL__EN_RCSCALE_BM    (0x3 << 12)
 151 #define HW_POWER_LOOPCTRL__EN_RCSCALE__DISABLED 0
 152 #define HW_POWER_LOOPCTRL__EN_RCSCALE__2X       1
 153 #define HW_POWER_LOOPCTRL__EN_RCSCALE__4X       2
 154 #define HW_POWER_LOOPCTRL__EN_RCSCALE__8X       3
 155 #define HW_POWER_LOOPCTRL__RCSCALE_THRESH   (1 << 14)
 156 #define HW_POWER_LOOPCTRL__DF_HYST_THRESH   (1 << 15)
 157 #define HW_POWER_LOOPCTRL__CM_HYST_THRESH   (1 << 16)
 158 #define HW_POWER_LOOPCTRL__EN_DF_HYST       (1 << 17)
 159 #define HW_POWER_LOOPCTRL__EN_CM_HYST       (1 << 18)
 160 #define HW_POWER_LOOPCTRL__HYST_SIGN        (1 << 19)
 161 #define HW_POWER_LOOPCTRL__TOGGLE_DIF       (1 << 20)
 162
 163 #define HW_POWER_STS            (*(volatile uint32_t *)(HW_POWER_BASE + 0xc0))
 164 #define HW_POWER_STS__VBUSVALID     (1 << 1)
 165 #define HW_POWER_STS__CHRGSTS       (1 << 11)
 166 #define HW_POWER_STS__PSWITCH_BP    20
 167 #define HW_POWER_STS__PSWITCH_BM    (3 << 20)
 168 #define HW_POWER_STS__PWRUP_SOURCE_BP   24
 169 #define HW_POWER_STS__PWRUP_SOURCE_BM   (0x3f << 24)
 170
 171 #define HW_POWER_BATTMONITOR    (*(volatile uint32_t *)(HW_POWER_BASE + 0xe0))
 172 #define HW_POWER_BATTMONITOR__ENBATADJ      (1 << 10)
 173 #define HW_POWER_BATTMONITOR__BATT_VAL_BP   16
 174 #define HW_POWER_BATTMONITOR__BATT_VAL_BM   (0x3ff << 16)
 175
 176 #define HW_POWER_RESET          (*(volatile uint32_t *)(HW_POWER_BASE + 0x100))
 177 #define HW_POWER_RESET__UNLOCK  0x3E770000
 178 #define HW_POWER_RESET__PWD     0x1
 179
 180 void imx233_power_set_charge_current(unsigned current); /* in mA */
 181 void imx233_power_set_stop_current(unsigned current); /* in mA */
 182 void imx233_power_enable_batadj(bool enable);
 183
 184 enum imx233_regulator_t
 185 {
 186     REGULATOR_VDDD, /* target, brownout, linreg, linreg offset */
 187     REGULATOR_VDDA, /* target, brownout, linreg, linreg offset */
 188     REGULATOR_VDDIO, /* target, brownout, linreg offset */
 189     REGULATOR_VDDMEM, /* target, linreg */
 190     REGULATOR_COUNT,
 191 };
 192
 193 void imx233_power_get_regulator(enum imx233_regulator_t reg, unsigned *target_mv,
 194     unsigned *brownout_mv);
 195
 196 // WARNING this call will block until voltage is stable
 197 void imx233_power_set_regulator(enum imx233_regulator_t reg, unsigned target_mv,
 198     unsigned brownout_mv);
 199
 200 // offset is -1,0 or 1
 201 void imx233_power_get_regulator_linreg(enum imx233_regulator_t reg,
 202     bool *enabled, int *linreg_offset);
 203
 204 // offset is -1,0 or 1
 205 void imx233_power_set_regulator_linreg(enum imx233_regulator_t reg,
 206     bool enabled, int linreg_offset);
 207
 208 static inline void imx233_power_set_dcdc_freq(bool pll, unsigned freq)
 209 {
 210     HW_POWER_MISC &= ~(HW_POWER_MISC__SEL_PLLCLK | HW_POWER_MISC__FREQSEL_BM);
 211     /* WARNING: HW_POWER_MISC does not have a SET/CLR variant ! */
 212     if(pll)
 213     {
 214         HW_POWER_MISC |= freq << HW_POWER_MISC__FREQSEL_BP;
 215         HW_POWER_MISC |= HW_POWER_MISC__SEL_PLLCLK;
 216     }
 217 }
 218
 219 struct imx233_power_info_t
 220 {
 221     bool dcdc_sel_pllclk; /* clock source of DC-DC: pll or 24MHz xtal */
 222     int dcdc_freqsel;
 223     int charge_current;
 224     int stop_current;
 225     bool charging;
 226     bool batt_adj;
 227     bool _4p2_enable;
 228     bool _4p2_dcdc;
 229     int _4p2_cmptrip;
 230     int _4p2_dropout;
 231     bool _5v_pwd_charge_4p2;
 232     int _5v_charge_4p2_limit;
 233     bool _5v_dcdc_xfer;
 234     bool _5v_enable_dcdc;
 235     int _5v_vbusvalid_thr;
 236     bool _5v_vbusvalid_detect;
 237     bool _5v_vbus_cmps;
 238 };
 239
 240 #define POWER_INFO_DCDC     (1 << 4)
 241 #define POWER_INFO_CHARGE   (1 << 5)
 242 #define POWER_INFO_4P2      (1 << 6)
 243 #define POWER_INFO_5V       (1 << 7)
 244 #define POWER_INFO_ALL      0xff
 245
 246 struct imx233_power_info_t imx233_power_get_info(unsigned flags);
 247
 248 #endif /* __POWER_IMX233__ */