firmware/target/arm/imx233/clkctrl-imx233.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2011 by Amaury Pouly
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef CLKCTRL_IMX233_H
  22 #define CLKCTRL_IMX233_H
  23
  24 #include "config.h"
  25 #include "system.h"
  26 #include "cpu.h"
  27
  28 #define HW_CLKCTRL_BASE     0x80040000
  29
  30 #define HW_CLKCTRL_PLLCTRL0 (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x0))
  31 #define HW_CLKCTRL_PLLCTRL0__POWER          (1 << 16)
  32 #define HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS    (1 << 18)
  33 #define HW_CLKCTRL_PLLCTRL0__DIV_SEL_BP     20
  34 #define HW_CLKCTRL_PLLCTRL0__DIV_SEL_BM     (3 << 20)
  35
  36 #define HW_CLKCTRL_PLLCTRL1 (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x10))
  37 #define HW_CLKCTRL_PLLCTRL1__LOCK       (1 << 31)
  38
  39 #define HW_CLKCTRL_CPU      (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x20))
  40 #define HW_CLKCTRL_CPU__DIV_CPU_BP  0
  41 #define HW_CLKCTRL_CPU__DIV_CPU_BM  0x3f
  42 #define HW_CLKCTRL_CPU__INTERRUPT_WAIT  (1 << 12)
  43 #define HW_CLKCTRL_CPU__DIV_XTAL_BP 16
  44 #define HW_CLKCTRL_CPU__DIV_XTAL_BM (0x3ff << 16)
  45 #define HW_CLKCTRL_CPU__DIV_XTAL_FRAC_EN    (1 << 26)
  46 #define HW_CLKCTRL_CPU__BUSY_REF_CPU    (1 << 28)
  47
  48 #define HW_CLKCTRL_HBUS     (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x30))
  49 #define HW_CLKCTRL_HBUS__DIV_BP         0
  50 #define HW_CLKCTRL_HBUS__DIV_BM         0x1f
  51 #define HW_CLKCTRL_HBUS__DIV_FRAC_EN    (1 << 5)
  52 #define HW_CLKCTRL_HBUS__SLOW_DIV_BP    16
  53 #define HW_CLKCTRL_HBUS__SLOW_DIV_BM    (0x7 << 16)
  54 #define HW_CLKCTRL_HBUS__AUTO_SLOW_MODE (1 << 20)
  55
  56 /* warning: this register doesn't have a CLR/SET variant ! */
  57 #define HW_CLKCTRL_XBUS     (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x40))
  58 #define HW_CLKCTRL_XBUS__DIV_BP     0
  59 #define HW_CLKCTRL_XBUS__DIV_BM     0x3ff
  60 #define HW_CLKCTRL_XBUS__BUSY       (1 << 31)
  61
  62 #define HW_CLKCTRL_XTAL     (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x50))
  63 #define HW_CLKCTRL_XTAL__TIMROT_CLK32K_GATE (1 << 26)
  64 #define HW_CLKCTRL_XTAL__DRI_CLK24M_GATE    (1 << 28)
  65 #define HW_CLKCTRL_XTAL__FILT_CLK24M_GATE   (1 << 30)
  66
  67 /* warning: this register doesn't have a CLR/SET variant ! */
  68 #define HW_CLKCTRL_PIX      (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x60))
  69 #define HW_CLKCTRL_PIX__DIV_BP  0
  70 #define HW_CLKCTRL_PIX__DIV_BM  0xfff
  71
  72 /* warning: this register doesn't have a CLR/SET variant ! */
  73 #define HW_CLKCTRL_SSP      (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x70))
  74 #define HW_CLKCTRL_SSP__DIV_BP  0
  75 #define HW_CLKCTRL_SSP__DIV_BM  0x1ff
  76
  77 /* warning: this register doesn't have a CLR/SET variant ! */
  78 #define HW_CLKCTRL_EMI      (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0xa0))
  79 #define HW_CLKCTRL_EMI__DIV_EMI_BP  0
  80 #define HW_CLKCTRL_EMI__DIV_EMI_BM  0x3f
  81 #define HW_CLKCTRL_EMI__DIV_XTAL_BP 8
  82 #define HW_CLKCTRL_EMI__DIV_XTAL_BM (0xf << 8)
  83 #define HW_CLKCTRL_EMI__BUSY_REF_EMI    (1 << 28)
  84 #define HW_CLKCTRL_EMI__SYNC_MODE_EN    (1 << 30)
  85 #define HW_CLKCTRL_EMI__CLKGATE     (1 << 31)
  86
  87 #define HW_CLKCTRL_CLKSEQ   (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x110))
  88 #define HW_CLKCTRL_CLKSEQ__BYPASS_PIX   (1 << 1)
  89 #define HW_CLKCTRL_CLKSEQ__BYPASS_SSP   (1 << 5)
  90 #define HW_CLKCTRL_CLKSEQ__BYPASS_EMI   (1 << 6)
  91 #define HW_CLKCTRL_CLKSEQ__BYPASS_CPU   (1 << 7)
  92
  93 #define HW_CLKCTRL_FRAC     (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0xf0))
  94 #define HW_CLKCTRL_FRAC_CPU (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf0))
  95 #define HW_CLKCTRL_FRAC_EMI (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf1))
  96 #define HW_CLKCTRL_FRAC_PIX (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf2))
  97 #define HW_CLKCTRL_FRAC_IO  (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf3))
  98 #define HW_CLKCTRL_FRAC_XX__XXDIV_BM    0x3f
  99 #define HW_CLKCTRL_FRAC_XX__XX_STABLE   (1 << 6)
 100 #define HW_CLKCTRL_FRAC_XX__CLKGATEXX   (1 << 7)
 101
 102 /* warning: this register doesn't have a CLR/SET variant ! */
 103 #define HW_CLKCTRL_RESET    (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x120))
 104 #define HW_CLKCTRL_RESET_CHIP   0x2
 105 #define HW_CLKCTRL_RESET_DIG    0x1
 106
 107 static inline void core_sleep(void)
 108 {
 109     __REG_SET(HW_CLKCTRL_CPU) = HW_CLKCTRL_CPU__INTERRUPT_WAIT;
 110     asm volatile (
 111         "mcr p15, 0, %0, c7, c0, 4 \n" /* Wait for interrupt */
 112         "nop\n" /* Datasheet unclear: "The lr sent to handler points here after RTI"*/
 113         : : "r"(0)
 114     );
 115     enable_irq();
 116 }
 117
 118 enum imx233_clock_t
 119 {
 120     CLK_PIX, /* freq, div, frac, bypass, enable */
 121     CLK_SSP, /* freq, div, bypass, enable */
 122     CLK_IO, /* freq, frac */
 123     CLK_CPU, /* freq, div, frac, bypass */
 124     CLK_HBUS, /* freq, div, frac */
 125     CLK_PLL, /* freq, enable */
 126     CLK_XTAL, /* freq */
 127     CLK_EMI, /* freq, div, frac, bypass */
 128     CLK_XBUS, /* freq, div */
 129 };
 130
 131 enum imx233_xtal_clk_t
 132 {
 133     XTAL_FILT = 1 << 30,
 134     XTAL_DRI = 1 << 28,
 135     XTAL_TIMROT = 1 << 26,
 136     XTAM_PWM =  1 << 29,
 137 };
 138
 139 /* Auto-Slow monitoring */
 140 enum imx233_as_monitor_t
 141 {
 142     AS_NONE = 0, /* Do not monitor any activity */
 143     AS_CPU_INSTR = 1 << 21, /* Monitor CPU instruction access to AHB */
 144     AS_CPU_DATA = 1 << 22, /* Monitor CPU data access to AHB */
 145     AS_TRAFFIC = 1 << 23, /* Monitor AHB master activity */
 146     AS_TRAFFIC_JAM = 1 << 24, /* Monitor AHB masters (>=3) activity */
 147     AS_APBXDMA = 1 << 25, /* Monitor APBX DMA activity */
 148     AS_APBHDMA = 1 << 26, /* Monitor APBH DMA activity */
 149     AS_PXP = 1 << 27, /* Monitor PXP activity */
 150     AS_DCP = 1 << 28, /* Monitor DCP activity */
 151     AS_ALL = 0xff << 21, /* Monitor all activity */
 152 };
 153
 154 enum imx233_as_div_t
 155 {
 156     AS_DIV_1 = 0,
 157     AS_DIV_2 = 1,
 158     AS_DIV_4 = 2,
 159     AS_DIV_8 = 3,
 160     AS_DIV_16 = 4,
 161     AS_DIV_32 = 5
 162 };
 163
 164 /* can use a mask of clocks */
 165 void imx233_clkctrl_enable_xtal(enum imx233_xtal_clk_t xtal_clk, bool enable);
 166 void imx233_clkctrl_is_xtal_enabled(enum imx233_xtal_clk_t xtal_clk, bool enable);
 167 /* only use it for non-fractional clocks (ie not for IO) */
 168 void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable);
 169 bool imx233_clkctrl_is_clock_enabled(enum imx233_clock_t cl);
 170 void imx233_clkctrl_set_clock_divisor(enum imx233_clock_t clk, int div);
 171 int imx233_clkctrl_get_clock_divisor(enum imx233_clock_t clk);
 172 /* call with fracdiv=0 to disable it */
 173 void imx233_clkctrl_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv);
 174 /* 0 means fractional dividor disable */
 175 int imx233_clkctrl_get_fractional_divisor(enum imx233_clock_t clk);
 176 void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass);
 177 bool imx233_clkctrl_get_bypass_pll(enum imx233_clock_t clk);
 178 void imx233_clkctrl_enable_usb_pll(bool enable);
 179 bool imx233_clkctrl_is_usb_pll_enabled(void);
 180 unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk);
 181
 182 bool imx233_clkctrl_is_emi_sync_enabled(void);
 183
 184 void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div);
 185 enum imx233_as_div_t imx233_clkctrl_get_auto_slow_divisor(void);
 186 void imx233_clkctrl_enable_auto_slow(bool enable);
 187 bool imx233_clkctrl_is_auto_slow_enabled(void);
 188 /* can use a mask of clocks */
 189 void imx233_clkctrl_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable);
 190 bool imx233_clkctrl_is_auto_slow_monitor_enabled(enum imx233_as_monitor_t monitor);
 191
 192 #endif /* CLKCTRL_IMX233_H */