firmware/drivers/rtc/rtc_s35380a.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * adopted for HD300 by Marcin Bukat
  11  * Copyright (C) 2009 by Bertrik Sikken
  12  * Copyright (C) 2008 by Robert Kukla
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License
  16  * as published by the Free Software Foundation; either version 2
  17  * of the License, or (at your option) any later version.
  18  *
  19  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  20  * KIND, either express or implied.
  21  *
  22  ****************************************************************************/
  23 #include "config.h"
  24 #include "rtc.h"
  25 #include "i2c-coldfire.h"
  26
  27 #include "lcd.h"
  28 #include "font.h"
  29 /*  Driver for the Seiko S35380A real-time clock chip with i2c interface
  30
  31     This driver was derived from rtc_s3539a.c and adapted for the MPIO HD300
  32  */
  33
  34 #define RTC_ADDR   0x60
  35
  36 #define STATUS_REG1     0
  37 #define STATUS_REG2     1
  38 #define REALTIME_DATA1  2
  39 #define REALTIME_DATA2  3
  40 #define INT1_REG        4
  41 #define INT2_REG        5
  42 #define CLOCK_CORR_REG  6
  43 #define FREE_REG        7
  44
  45 /* STATUS_REG1 flags
  46  * bits order is reversed
  47  */
  48 #define STATUS_REG1_POC   0x01
  49 #define STATUS_REG1_BLD   0x02
  50 #define STATUS_REG1_INT2  0x04
  51 #define STATUS_REG1_INT1  0x08
  52 #define STATUS_REG1_SC1   0x10
  53 #define STATUS_REG1_SC0   0x20
  54 #define STATUS_REG1_H1224 0x40
  55 #define STATUS_REG1_RESET 0x80
  56
  57 /* STATUS_REG2 flags
  58  * bits order is reversed
  59  */
  60 #define STATUS_REG2_TEST   0x01
  61 #define STATUS_REG2_INT2AE 0x02
  62 #define STATUS_REG2_INT2ME 0x04
  63 #define STATUS_REG2_INT2FE 0x08
  64 #define STATUS_REG2_32kE   0x10
  65 #define STATUS_REG2_INT1AE 0x20
  66 #define STATUS_REG2_INT1ME 0x40
  67 #define STATUS_REG2_INT1FE 0x80
  68
  69 static void reverse_bits(unsigned char* v, int size)
  70 {
  71     static const unsigned char flipnibble[] =
  72         {0x00, 0x08, 0x04, 0x0C, 0x02, 0x0A, 0x06, 0x0E,
  73          0x01, 0x09, 0x05, 0x0D, 0x03, 0x0B, 0x07, 0x0F};
  74     int i;
  75
  76     for (i = 0; i < size; i++) {
  77         v[i] = (flipnibble[v[i] & 0x0F] << 4) |
  78                 flipnibble[(v[i] >> 4) & 0x0F];
  79     }
  80 }
  81
  82 void rtc_init(void)
  83 {
  84     unsigned char status_reg;
  85     i2c_read(I2C_IFACE_1, RTC_ADDR | (STATUS_REG1<<1), &status_reg, 1);
  86
  87     if ( (status_reg & STATUS_REG1_POC) ||
  88          (status_reg & STATUS_REG1_BLD) )
  89     {
  90         /* perform rtc reset*/
  91         status_reg |= STATUS_REG1_RESET;
  92         i2c_write(I2C_IFACE_1, RTC_ADDR | (STATUS_REG1<<1), &status_reg, 1);
  93     }
  94
  95     /* setup 24h time format */
  96     status_reg = STATUS_REG1_H1224;
  97     i2c_write(I2C_IFACE_1, RTC_ADDR | (STATUS_REG1<<1), &status_reg, 1);
  98
  99 #ifdef HAVE_RTC_ALARM
 100     rtc_check_alarm_started(false);
 101 #endif
 102     /* disable all alarms */
 103     status_reg = 0;
 104     i2c_write(I2C_IFACE_1, RTC_ADDR | (STATUS_REG2<<1), &status_reg, 1);
 105 }
 106
 107 int rtc_read_datetime(struct tm *tm)
 108 {
 109     unsigned char buf[7];
 110     unsigned int i;
 111     int ret;
 112
 113     ret = i2c_read(I2C_IFACE_1, RTC_ADDR | (REALTIME_DATA1<<1), buf, sizeof(buf));
 114     reverse_bits(buf, sizeof(buf));
 115
 116     buf[4] &= 0x3f; /* mask out p.m. flag */
 117
 118     for (i = 0; i < sizeof(buf); i++)
 119         buf[i] = BCD2DEC(buf[i]);
 120
 121     tm->tm_sec = buf[6];
 122     tm->tm_min = buf[5];
 123     tm->tm_hour = buf[4];
 124     tm->tm_wday = buf[3];
 125     tm->tm_mday = buf[2];
 126     tm->tm_mon = buf[1] - 1;
 127     tm->tm_year = buf[0] + 100;
 128
 129     return ret;
 130 }
 131
 132 int rtc_write_datetime(const struct tm *tm)
 133 {
 134     unsigned char buf[7];
 135     unsigned int i;
 136     int ret;
 137
 138     buf[6] = tm->tm_sec;
 139     buf[5] = tm->tm_min;
 140     buf[4] = tm->tm_hour;
 141     buf[3] = tm->tm_wday;
 142     buf[2] = tm->tm_mday;
 143     buf[1] = tm->tm_mon + 1;
 144     buf[0] = tm->tm_year - 100;
 145
 146     for (i = 0; i < sizeof(buf); i++)
 147         buf[i] = DEC2BCD(buf[i]);
 148
 149     reverse_bits(buf, sizeof(buf));
 150     ret = i2c_write(I2C_IFACE_1, RTC_ADDR | (REALTIME_DATA1<<1), buf, sizeof(buf));
 151
 152     return ret;
 153 }
 154
 155 #ifdef HAVE_RTC_ALARM
 156 void rtc_set_alarm(int h, int m)
 157 {
 158     /* 1) get the date
 159      * 2) compare h:m with current time
 160           if alarm time < current time set day += 1
 161        3) check day if it is not needed to wrap around
 162        4) set the validity bits
 163        5) write to alarm register
 164      */
 165
 166     unsigned char buf[3];
 167     unsigned char reg;
 168
 169     /* 0x80 - validity flag */
 170     buf[2] = DEC2BCD(m) | 0x80;
 171     buf[1] = DEC2BCD(h) | 0x80;
 172     buf[0] = 0;
 173
 174     reverse_bits(buf, sizeof(buf));
 175
 176     reg = STATUS_REG2_INT1AE;
 177     i2c_write(I2C_IFACE_1, RTC_ADDR | (STATUS_REG2<<1), &reg, 1);
 178     i2c_write(I2C_IFACE_1, RTC_ADDR | (INT1_REG<<1), buf, sizeof(buf));
 179 }
 180
 181 void rtc_get_alarm(int *h, int *m)
 182 {
 183     unsigned char buf[3];
 184     unsigned char reg,reg2;
 185
 186     i2c_read(I2C_IFACE_1, RTC_ADDR | (STATUS_REG2<<1), &reg, 1);
 187
 188     reg2 = reg | STATUS_REG2_INT1AE;
 189     i2c_write(I2C_IFACE_1, RTC_ADDR | (STATUS_REG2<<1), &reg2, 1);
 190     i2c_read(I2C_IFACE_1, RTC_ADDR | (INT1_REG<<1), buf, sizeof(buf));
 191     i2c_write(I2C_IFACE_1, RTC_ADDR | (STATUS_REG2<<1), &reg, 1);
 192
 193     reverse_bits(buf, sizeof(buf));
 194
 195     *h = BCD2DEC(buf[1] & 0x3f); /* mask out A1HE and PM/AM flag */
 196     *m = BCD2DEC(buf[2] & 0x7f); /* mask out A1mE */
 197 }
 198
 199 bool rtc_check_alarm_flag(void)
 200 {
 201     unsigned char status_reg;
 202     i2c_read(I2C_IFACE_1, RTC_ADDR | (STATUS_REG1<<1), &status_reg, 1);
 203
 204     return (status_reg & (STATUS_REG1_INT1 | STATUS_REG1_INT2));
 205 }
 206
 207 void rtc_enable_alarm(bool enable)
 208 {
 209     unsigned char status_reg2;
 210     status_reg2 = enable ? STATUS_REG2_INT1AE:0;
 211     i2c_write(I2C_IFACE_1, RTC_ADDR | (STATUS_REG2<<1), &status_reg2, 1);
 212 }
 213
 214 bool rtc_check_alarm_started(bool release_alarm)
 215 {
 216     static bool run_before = false, alarm_state;
 217     bool rc;
 218
 219     if (run_before)
 220     {
 221         rc = alarm_state;
 222         alarm_state &= ~release_alarm;
 223     }
 224     else
 225     {
 226         rc = rtc_check_alarm_flag();
 227         run_before = true;
 228     }
 229
 230     return rc;
 231 }
 232 #endif