Ignore HAVE_BACKLIGHT for plugins, as they build without the check and makes life...
[maemo-rb.git] / firmware / rolo.c
blob7ff5195318f03465785323bd5a8ec9b355daf3c2
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
10 * Copyright (C) 2002 Randy D. Wood
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
18 ****************************************************************************/
20 #include "config.h"
21 #include "lcd.h"
22 #include "lcd-remote.h"
23 #include "kernel.h"
24 #include "sprintf.h"
25 #include "button.h"
26 #include "file.h"
27 #include "audio.h"
28 #include "system.h"
29 #include "i2c.h"
30 #include "string.h"
31 #include "buffer.h"
33 #ifdef MI4_FORMAT
34 #include "crc32-mi4.h"
35 #undef FIRMWARE_OFFSET_FILE_CRC
36 #undef FIRMWARE_OFFSET_FILE_DATA
37 #define FIRMWARE_OFFSET_FILE_CRC 0xC
38 #define FIRMWARE_OFFSET_FILE_DATA 0x200
39 #endif
41 #if !defined(IRIVER_IFP7XX_SERIES) && \
42 (CONFIG_CPU != PP5002) && (CONFIG_CPU != S3C2440)
43 /* FIX: this doesn't work on iFP, 3rd Gen ipods */
45 #define IRQ0_EDGE_TRIGGER 0x80
47 #ifdef CPU_PP
48 /* Handle the COP properly - it needs to jump to a function outside SDRAM while
49 * the new firmware is being loaded, and then jump to the start of SDRAM
50 * TODO: Use the mailboxes built into the PP processor for this
53 volatile unsigned char IDATA_ATTR cpu_message = 0;
54 volatile unsigned char IDATA_ATTR cpu_reply = 0;
56 void rolo_restart_cop(void) ICODE_ATTR;
57 void rolo_restart_cop(void)
59 /* Invalidate cache */
60 invalidate_icache();
62 /* Disable cache */
63 CACHE_CTL = CACHE_DISABLE;
65 /* Tell the main core that we're ready to reload */
66 cpu_reply = 2;
68 /* Wait while RoLo loads the image into SDRAM */
69 /* TODO: Accept checksum failure gracefully */
70 while(cpu_message == 1) {}
72 /* Acknowledge the CPU and then reload */
73 cpu_reply = 1;
75 asm volatile(
76 "mov r0, #0x10000000 \n"
77 "mov pc, r0 \n"
80 #endif
82 static void rolo_error(const char *text)
84 lcd_clear_display();
85 lcd_puts(0, 0, "ROLO error:");
86 lcd_puts_scroll(0, 1, text);
87 lcd_update();
88 button_get(true);
89 button_get(true);
90 button_get(true);
91 lcd_stop_scroll();
94 #if CONFIG_CPU == SH7034
95 /* these are in assembler file "descramble.S" */
96 extern unsigned short descramble(const unsigned char* source,
97 unsigned char* dest, int length);
98 extern void rolo_restart(const unsigned char* source, unsigned char* dest,
99 int length);
100 #else
102 /* explicitly put this code in iram, ICODE_ATTR is defined to be null for some
103 targets that are low on iram, like the gigabeat F/X */
104 void rolo_restart(const unsigned char* source, unsigned char* dest,
105 long length) __attribute__ ((section(".icode")));
106 void rolo_restart(const unsigned char* source, unsigned char* dest,
107 long length)
109 long i;
110 unsigned char* localdest = dest;
111 #ifdef CPU_PP502x
112 unsigned long* memmapregs = (unsigned long*)0xf000f000;
113 #endif
115 /* This is the equivalent of a call to memcpy() but this must be done from
116 iram to avoid overwriting itself and we don't want to depend on memcpy()
117 always being in iram */
118 for(i = 0;i < length;i++)
119 *localdest++ = *source++;
121 #if defined(CPU_COLDFIRE)
122 asm (
123 "movec.l %0,%%vbr \n"
124 "move.l (%0)+,%%sp \n"
125 "move.l (%0),%0 \n"
126 "jmp (%0) \n"
127 : : "a"(dest)
129 #elif defined(CPU_PP502x)
131 /* Tell the COP that we've finished loading and started rebooting */
132 cpu_message = 0;
134 /* Flush cache */
135 flush_icache();
137 /* Disable cache */
138 CACHE_CTL = CACHE_DISABLE;
140 /* Reset the memory mapping registers to zero */
141 for (i=0;i<8;i++)
142 memmapregs[i]=0;
144 /* Wait for the COP to tell us it is rebooting */
145 while(cpu_reply != 1) {}
147 asm volatile(
148 "mov r0, #0x10000000 \n"
149 "mov pc, r0 \n"
151 #endif
153 #endif
155 /* This is assigned in the linker control file */
156 extern unsigned long loadaddress;
158 /***************************************************************************
160 * Name: rolo_load_app(char *filename,int scrambled)
161 * Filename must be a fully defined filename including the path and extension
163 ***************************************************************************/
164 int rolo_load(const char* filename)
166 int fd;
167 long length;
168 #if defined(CPU_COLDFIRE) || defined(CPU_PP)
169 #if !defined(MI4_FORMAT)
170 int i;
171 #endif
172 unsigned long checksum,file_checksum;
173 #else
174 long file_length;
175 unsigned short checksum,file_checksum;
176 #endif
177 unsigned char* ramstart = (void*)&loadaddress;
179 lcd_clear_display();
180 lcd_puts(0, 0, "ROLO...");
181 lcd_puts(0, 1, "Loading");
182 lcd_update();
183 #ifdef HAVE_REMOTE_LCD
184 lcd_remote_clear_display();
185 lcd_remote_puts(0, 0, "ROLO...");
186 lcd_remote_puts(0, 1, "Loading");
187 lcd_remote_update();
188 #endif
190 audio_stop();
192 fd = open(filename, O_RDONLY);
193 if(-1 == fd) {
194 rolo_error("File not found");
195 return -1;
198 length = filesize(fd) - FIRMWARE_OFFSET_FILE_DATA;
200 #if defined(CPU_COLDFIRE) || defined(CPU_PP)
201 /* Read and save checksum */
202 lseek(fd, FIRMWARE_OFFSET_FILE_CRC, SEEK_SET);
203 if (read(fd, &file_checksum, 4) != 4) {
204 rolo_error("Error Reading checksum");
205 return -1;
208 #if !defined(MI4_FORMAT)
209 /* Rockbox checksums are big-endian */
210 file_checksum = betoh32(file_checksum);
211 #endif
213 #ifdef CPU_PP
214 cpu_message = COP_REBOOT;
215 COP_CTL = PROC_WAKE;
216 lcd_puts(0, 2, "Waiting for coprocessor...");
217 lcd_update();
218 while(cpu_reply != 2) {}
219 lcd_puts(0, 2, " ");
220 lcd_update();
221 #endif
223 lseek(fd, FIRMWARE_OFFSET_FILE_DATA, SEEK_SET);
225 if (read(fd, audiobuf, length) != length) {
226 rolo_error("Error Reading File");
227 return -1;
230 #ifdef MI4_FORMAT
231 /* Check CRC32 to see if we have a valid file */
232 chksum_crc32gentab();
233 checksum = chksum_crc32 (audiobuf, length);
234 #else
235 checksum = MODEL_NUMBER;
237 for(i = 0;i < length;i++) {
238 checksum += audiobuf[i];
240 #endif
242 /* Verify checksum against file header */
243 if (checksum != file_checksum) {
244 rolo_error("Checksum Error");
245 return -1;
248 lcd_puts(0, 1, "Executing");
249 lcd_update();
250 #ifdef HAVE_REMOTE_LCD
251 lcd_remote_puts(0, 1, "Executing");
252 lcd_remote_update();
253 #endif
255 set_irq_level(HIGHEST_IRQ_LEVEL);
256 #elif CONFIG_CPU == SH7034
257 /* Read file length from header and compare to real file length */
258 lseek(fd, FIRMWARE_OFFSET_FILE_LENGTH, SEEK_SET);
259 if(read(fd, &file_length, 4) != 4) {
260 rolo_error("Error Reading File Length");
261 return -1;
263 if (length != file_length) {
264 rolo_error("File length mismatch");
265 return -1;
268 /* Read and save checksum */
269 lseek(fd, FIRMWARE_OFFSET_FILE_CRC, SEEK_SET);
270 if (read(fd, &file_checksum, 2) != 2) {
271 rolo_error("Error Reading checksum");
272 return -1;
274 lseek(fd, FIRMWARE_OFFSET_FILE_DATA, SEEK_SET);
276 /* verify that file can be read and descrambled */
277 if ((audiobuf + (2*length)+4) >= audiobufend) {
278 rolo_error("Not enough room to load file");
279 return -1;
282 if (read(fd, &audiobuf[length], length) != (int)length) {
283 rolo_error("Error Reading File");
284 return -1;
287 lcd_puts(0, 1, "Descramble");
288 lcd_update();
290 checksum = descramble(audiobuf + length, audiobuf, length);
292 /* Verify checksum against file header */
293 if (checksum != file_checksum) {
294 rolo_error("Checksum Error");
295 return -1;
298 lcd_puts(0, 1, "Executing ");
299 lcd_update();
301 set_irq_level(HIGHEST_IRQ_LEVEL);
303 /* Calling these 2 initialization routines was necessary to get the
304 the origional Archos version of the firmware to load and execute. */
305 system_init(); /* Initialize system for restart */
306 i2c_init(); /* Init i2c bus - it seems like a good idea */
307 ICR = IRQ0_EDGE_TRIGGER; /* Make IRQ0 edge triggered */
308 TSTR = 0xE0; /* disable all timers */
309 /* model-specific de-init, needed when flashed */
310 /* Especially the Archos software is picky about this */
311 #if defined(ARCHOS_RECORDER) || defined(ARCHOS_RECORDERV2) || \
312 defined(ARCHOS_FMRECORDER)
313 PAIOR = 0x0FA0;
314 #endif
315 #endif
316 rolo_restart(audiobuf, ramstart, length);
318 return 0; /* this is never reached */
320 #else /* !defined(IRIVER_IFP7XX_SERIES) */
321 int rolo_load(const char* filename)
323 /* dummy */
324 (void)filename;
325 return 0;
328 #endif /* !defined(IRIVER_IFP7XX_SERIES) */