1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2008 by Marcoen Hirschberg, Bart van Adrichem
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
24 #define REG8_PTR_T volatile uint8_t *
25 #define REG16_PTR_T volatile uint16_t *
26 #define REG32_PTR_T volatile uint32_t *
28 #define TIMER_FREQ (1843200 * 4 * 26 / 1 / 4) /* 47923200 Hz */
30 #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
34 /* Following registers are mapped on IO Area in data memory area of Calm. */
35 #define CONFIG0 (*(REG16_PTR_T)(0x3F000000)) /* configuration/control register 0 */
36 #define CONFIG1 (*(REG16_PTR_T)(0x3F000002)) /* configuration/control register 1*/
37 #define COMMUN (*(REG16_PTR_T)(0x3F000004)) /* Communication Control Register */
38 #define DDATA0 (*(REG16_PTR_T)(0x3F000006)) /* Communication data from host to ADM */
39 #define DDATA1 (*(REG16_PTR_T)(0x3F000008)) /* Communication data from host to ADM */
40 #define DDATA2 (*(REG16_PTR_T)(0x3F00000A)) /* Communication data from host to ADM */
41 #define DDATA3 (*(REG16_PTR_T)(0x3F00000C)) /* Communication data from host to ADM */
42 #define DDATA4 (*(REG16_PTR_T)(0x3F00000E)) /* Communication data from host to ADM */
43 #define DDATA5 (*(REG16_PTR_T)(0x3F000010)) /* Communication data from host to ADM */
44 #define DDATA6 (*(REG16_PTR_T)(0x3F000012)) /* Communication data from host to ADM */
45 #define DDATA7 (*(REG16_PTR_T)(0x3F000014)) /* Communication data from host to ADM */
46 #define UDATA0 (*(REG16_PTR_T)(0x3F000016)) /* Communication data from ADM to host */
47 #define UDATA1 (*(REG16_PTR_T)(0x3F000018)) /* Communication data from ADM to host */
48 #define UDATA2 (*(REG16_PTR_T)(0x3F00001A)) /* Communication data from ADM to host */
49 #define UDATA3 (*(REG16_PTR_T)(0x3F00001C)) /* Communication data from ADM to host */
50 #define UDATA4 (*(REG16_PTR_T)(0x3F00001E)) /* Communication data from ADM to host */
51 #define UDATA5 (*(REG16_PTR_T)(0x3F000020)) /* Communication data from ADM to host */
52 #define UDATA6 (*(REG16_PTR_T)(0x3F000022)) /* Communication data from ADM to host */
53 #define UDATA7 (*(REG16_PTR_T)(0x3F000024)) /* Communication data from ADM to host */
54 #define IBASE_H (*(REG16_PTR_T)(0x3F000026)) /* Higher half of start address for ADM instruction area */
55 #define IBASE_L (*(REG16_PTR_T)(0x3F000028)) /* Lower half of start address for ADM instruction area */
56 #define DBASE_H (*(REG16_PTR_T)(0x3F00002A)) /* Higher half of start address for CalmRISC data area */
57 #define DBASE_L (*(REG16_PTR_T)(0x3F00002C)) /* Lower half of start address for CalmRISC data area */
58 #define XBASE_H (*(REG16_PTR_T)(0x3F00002E)) /* Higher half of start address for Mac X area */
59 #define XBASE_L (*(REG16_PTR_T)(0x3F000030)) /* Lower half of start address for Mac X area */
60 #define YBASE_H (*(REG16_PTR_T)(0x3F000032)) /* Higher half of start address for Mac Y area */
61 #define YBASE_L (*(REG16_PTR_T)(0x3F000034)) /* Lower half of start address for Mac Y area */
62 #define S0BASE_H (*(REG16_PTR_T)(0x3F000036)) /* Higher half of start address for sequential buffer 0 area */
63 #define S0BASE_L (*(REG16_PTR_T)(0x3F000038)) /* Lower half of start address for sequential buffer 0 area */
64 #define S1BASE_H (*(REG16_PTR_T)(0x3F00003A)) /* Higher half of start address for sequential buffer 1 area */
65 #define S1BASE_L (*(REG16_PTR_T)(0x3F00003C)) /* Lower half of start address for sequential buffer 1 area */
66 #define CACHECON (*(REG16_PTR_T)(0x3F00003E)) /* Cache Control Register */
67 #define CACHESTAT (*(REG16_PTR_T)(0x3F000040)) /* Cache status register */
68 #define SBFCON (*(REG16_PTR_T)(0x3F000042)) /* Sequential Buffer Control Register */
69 #define SBFSTAT (*(REG16_PTR_T)(0x3F000044)) /* Sequential Buffer Status Register */
70 #define SBL0OFF_H (*(REG16_PTR_T)(0x3F000046)) /* Higher bits of Offset register of sequential block 0 area */
71 #define SBL0OFF_L (*(REG16_PTR_T)(0x3F000048)) /* Lower bits of Offset register of sequential block 0 area */
72 #define SBL1OFF_H (*(REG16_PTR_T)(0x3F00004A)) /* Higher bits of Offset register of sequential block 1 area */
73 #define SBL1OFF_L (*(REG16_PTR_T)(0x3F00004C)) /* Lower bits of Offset register of sequential block 1 area */
74 #define SBL0BEGIN_H (*(REG16_PTR_T)(0x3F00004E)) /* Higher bits of Begin Offset of sequential block 0 area in ring mode */
75 #define SBL0BEGIN_L (*(REG16_PTR_T)(0x3F000050)) /* Lower bits of Begin Offset of sequential block 0 area in ring mode */
76 #define SBL1BEGIN_H (*(REG16_PTR_T)(0x3F000052)) /* Higher bits of Begin Offset of sequential block 1 area in ring mode */
77 #define SBL1BEGIN_L (*(REG16_PTR_T)(0x3F000054)) /* Lower bits of Begin Offset of sequential block 1 area in ring mode */
78 #define SBL0END_H (*(REG16_PTR_T)(0x3F000056)) /* Lower bits of End Offset of sequential block 0 area in ring mode */
79 #define SBL0END_L (*(REG16_PTR_T)(0x3F000058)) /* Higher bits of End Offset of sequential block 0 area in ring mode */
80 #define SBL1END_H (*(REG16_PTR_T)(0x3F00005A)) /* Lower bits of End Offset of sequential block 1 area in ring mode */
81 #define SBL1END_L (*(REG16_PTR_T)(0x3F00005C)) /* Higher bits of End Offset of sequential block 1 area in ring mode */
83 /* Following registers are components of SFRS of the target system */
84 #define ADM_CONFIG (*(REG32_PTR_T)(0x39000000)) /* Configuration/Control Register */
85 #define ADM_COMMUN (*(REG32_PTR_T)(0x39000004)) /* Communication Control Register */
86 #define ADM_DDATA0 (*(REG32_PTR_T)(0x39000010)) /* Communication data from host to ADM */
87 #define ADM_DDATA1 (*(REG32_PTR_T)(0x39000014)) /* Communication data from host to ADM */
88 #define ADM_DDATA2 (*(REG32_PTR_T)(0x39000018)) /* Communication data from host to ADM */
89 #define ADM_DDATA3 (*(REG32_PTR_T)(0x3900001C)) /* Communication data from host to ADM */
90 #define ADM_DDATA4 (*(REG32_PTR_T)(0x39000020)) /* Communication data from host to ADM */
91 #define ADM_DDATA5 (*(REG32_PTR_T)(0x39000024)) /* Communication data from host to ADM */
92 #define ADM_DDATA6 (*(REG32_PTR_T)(0x39000028)) /* Communication data from host to ADM */
93 #define ADM_DDATA7 (*(REG32_PTR_T)(0x3900002C)) /* Communication data from host to ADM */
94 #define ADM_UDATA0 (*(REG32_PTR_T)(0x39000030)) /* Communication data from ADM to host */
95 #define ADM_UDATA1 (*(REG32_PTR_T)(0x39000034)) /* Communication data from ADM to host */
96 #define ADM_UDATA2 (*(REG32_PTR_T)(0x39000038)) /* Communication data from ADM to host */
97 #define ADM_UDATA3 (*(REG32_PTR_T)(0x3900003C)) /* Communication data from ADM to host */
98 #define ADM_UDATA4 (*(REG32_PTR_T)(0x39000040)) /* Communication data from ADM to host */
99 #define ADM_UDATA5 (*(REG32_PTR_T)(0x39000044)) /* Communication data from ADM to host */
100 #define ADM_UDATA6 (*(REG32_PTR_T)(0x39000048)) /* Communication data from ADM to host */
101 #define ADM_UDATA7 (*(REG32_PTR_T)(0x3900004C)) /* Communication data from ADM to host */
102 #define ADM_IBASE (*(REG32_PTR_T)(0x39000050)) /* Start Address for ADM Instruction Area */
103 #define ADM_DBASE (*(REG32_PTR_T)(0x39000054)) /* Start Address for CalmRISC Data Area */
104 #define ADM_XBASE (*(REG32_PTR_T)(0x39000058)) /* Start Address for Mac X Area */
105 #define ADM_YBASE (*(REG32_PTR_T)(0x3900005C)) /* Start Address for Mac Y Area */
106 #define ADM_S0BASE (*(REG32_PTR_T)(0x39000060)) /* Start Address for Sequential Block 0 Area */
107 #define ADM_S1BASE (*(REG32_PTR_T)(0x39000064)) /* Start Address for Sequential Block 1 Area */
109 /* 05. CLOCK & POWER MANAGEMENT */
110 #define CLKCON (*(REG32_PTR_T)(0x3C500000)) /* Clock control register */
111 #define PLL0PMS (*(REG32_PTR_T)(0x3C500004)) /* PLL PMS value register */
112 #define PLL1PMS (*(REG32_PTR_T)(0x3C500008)) /* PLL PMS value register */
113 #define PLL2PMS (*(REG32_PTR_T)(0x3C50000C)) /* PLL PMS value register - S5L8701 only? */
114 #define CLKCON3 (*(REG32_PTR_T)(0x3C500010)) /* Clock control register 3 */
115 #define PLL0LCNT (*(REG32_PTR_T)(0x3C500014)) /* PLL0 lock count register */
116 #define PLL1LCNT (*(REG32_PTR_T)(0x3C500018)) /* PLL1 lock count register */
117 #define PLL2LCNT (*(REG32_PTR_T)(0x3C50001C)) /* PLL2 lock count register - S5L8701 only? */
118 #define PLLLOCK (*(REG32_PTR_T)(0x3C500020)) /* PLL lock status register */
119 #define PLLCON (*(REG32_PTR_T)(0x3C500024)) /* PLL control register */
120 #define PWRCON (*(REG32_PTR_T)(0x3C500028)) /* Clock power control register */
121 #define PWRMODE (*(REG32_PTR_T)(0x3C50002C)) /* Power mode control register */
122 #define SWRCON (*(REG32_PTR_T)(0x3C500030)) /* Software reset control register */
123 #define RSTSR (*(REG32_PTR_T)(0x3C500034)) /* Reset status register */
124 #define DSPCLKMD (*(REG32_PTR_T)(0x3C500038)) /* DSP clock mode register */
125 #define CLKCON2 (*(REG32_PTR_T)(0x3C50003C)) /* Clock control register 2 */
126 #define PWRCONEXT (*(REG32_PTR_T)(0x3C500040)) /* Clock power control register 2 */
128 /* 06. INTERRUPT CONTROLLER UNIT */
129 #define SRCPND (*(REG32_PTR_T)(0x39C00000)) /* Indicates the interrupt request status. */
130 #define INTMOD (*(REG32_PTR_T)(0x39C00004)) /* Interrupt mode register. */
131 #define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */
132 #if CONFIG_CPU==S5L8701
133 #define INTMSK_TIMERA (1<<5)
134 #define INTMSK_TIMERB (1<<5)
135 #define INTMSK_TIMERC (1<<5)
136 #define INTMSK_TIMERD (1<<5)
137 #define INTMSK_ECC (1<<19)
138 #define INTMSK_USB_OTG (1<<16)
140 #define INTMSK_TIMERA (1<<5)
141 #define INTMSK_TIMERB (1<<7)
142 #define INTMSK_TIMERC (1<<8)
143 #define INTMSK_TIMERD (1<<9)
145 #define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */
146 #define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */
147 #define INTOFFSET (*(REG32_PTR_T)(0x39C00014)) /* Indicates the IRQ interrupt request source */
148 #define EINTPOL (*(REG32_PTR_T)(0x39C00018)) /* Indicates external interrupt polarity */
149 #define EINTPEND (*(REG32_PTR_T)(0x39C0001C)) /* Indicates whether external interrupts are pending. */
150 #define EINTMSK (*(REG32_PTR_T)(0x39C00020)) /* Indicates whether external interrupts are masked */
152 /* 07. MEMORY INTERFACE UNIT (MIU) */
155 #define MIUCON (*(REG32_PTR_T)(0x38200000)) /* External Memory configuration register */
156 #define MIUCOM (*(REG32_PTR_T)(0x38200004)) /* Command and status register */
157 #define MIUAREF (*(REG32_PTR_T)(0x38200008)) /* Auto-refresh control register */
158 #define MIUMRS (*(REG32_PTR_T)(0x3820000C)) /* SDRAM Mode Register Set Value Register */
159 #define MIUSDPARA (*(REG32_PTR_T)(0x38200010)) /* SDRAM parameter register */
162 #define MEMCONF (*(REG32_PTR_T)(0x38200020)) /* External Memory configuration register */
163 #define USRCMD (*(REG32_PTR_T)(0x38200024)) /* Command and Status register */
164 #define AREF (*(REG32_PTR_T)(0x38200028)) /* Auto-refresh control register */
165 #define MRS (*(REG32_PTR_T)(0x3820002C)) /* DRAM mode register set value register */
166 #define DPARAM (*(REG32_PTR_T)(0x38200030)) /* DRAM parameter register (Unit of ‘tXXX’ : tCK */
167 #define SMEMCONF (*(REG32_PTR_T)(0x38200034)) /* Static memory mode register set value register */
168 #define MIUS01PARA (*(REG32_PTR_T)(0x38200038)) /* SRAM0, SRAM1 static memory parameter register (In S5L8700, SRAM0 is Nor Flash) */
169 #define MIUS23PARA (*(REG32_PTR_T)(0x3820003C)) /* SRAM2 and SRAM3 static memory parameter register */
171 #define MIUORG (*(REG32_PTR_T)(0x38200040)) /* SDR/DDR selection */
172 #define MIUDLYDQS (*(REG32_PTR_T)(0x38200044)) /* DQS/DQS-rst delay parameter */
173 #define MIUDLYCLK (*(REG32_PTR_T)(0x38200048)) /* SDR/DDR Clock delay parameter */
174 #define MIU_DSS_SEL_B (*(REG32_PTR_T)(0x3820004C)) /* SSTL2 Drive Strength parameter for Bi-direction signal */
175 #define MIU_DSS_SEL_O (*(REG32_PTR_T)(0x38200050)) /* SSTL2 Drive Strength parameter for Output signal */
176 #define MIU_DSS_SEL_C (*(REG32_PTR_T)(0x38200054)) /* SSTL2 Drive Strength parameter for Clock signal */
177 #define PAD_DSS_SEL_NOR (*(REG32_PTR_T)(0x38200058)) /* Wide range I/O Drive Strength parameter for NOR interface */
178 #define PAD_DSS_SEL_ATA (*(REG32_PTR_T)(0x3820005C)) /* Wide range I/O Drive Strength parameter for ATA interface */
179 #define SSTL2_PAD_ON (*(REG32_PTR_T)(0x38200060)) /* SSTL2 pad ON/OFF select */
181 /* 08. IODMA CONTROLLER */
182 #define DMABASE0 (*(REG32_PTR_T)(0x38400000)) /* Base address register for channel 0 */
183 #define DMACON0 (*(REG32_PTR_T)(0x38400004)) /* Configuration register for channel 0 */
184 #define DMATCNT0 (*(REG32_PTR_T)(0x38400008)) /* Transfer count register for channel 0 */
185 #define DMACADDR0 (*(REG32_PTR_T)(0x3840000C)) /* Current memory address register for channel 0 */
186 #define DMACTCNT0 (*(REG32_PTR_T)(0x38400010)) /* Current transfer count register for channel 0 */
187 #define DMACOM0 (*(REG32_PTR_T)(0x38400014)) /* Channel 0 command register */
188 #define DMANOFF0 (*(REG32_PTR_T)(0x38400018)) /* Channel 0 offset2 register */
189 #define DMABASE1 (*(REG32_PTR_T)(0x38400020)) /* Base address register for channel 1 */
190 #define DMACON1 (*(REG32_PTR_T)(0x38400024)) /* Configuration register for channel 1 */
191 #define DMATCNT1 (*(REG32_PTR_T)(0x38400028)) /* Transfer count register for channel 1 */
192 #define DMACADDR1 (*(REG32_PTR_T)(0x3840002C)) /* Current memory address register for channel 1 */
193 #define DMACTCNT1 (*(REG32_PTR_T)(0x38400030)) /* Current transfer count register for channel 1 */
194 #define DMACOM1 (*(REG32_PTR_T)(0x38400034)) /* Channel 1 command register */
195 #define DMABASE2 (*(REG32_PTR_T)(0x38400040)) /* Base address register for channel 2 */
196 #define DMACON2 (*(REG32_PTR_T)(0x38400044)) /* Configuration register for channel 2 */
197 #define DMATCNT2 (*(REG32_PTR_T)(0x38400048)) /* Transfer count register for channel 2 */
198 #define DMACADDR2 (*(REG32_PTR_T)(0x3840004C)) /* Current memory address register for channel 2 */
199 #define DMACTCNT2 (*(REG32_PTR_T)(0x38400050)) /* Current transfer count register for channel 2 */
200 #define DMACOM2 (*(REG32_PTR_T)(0x38400054)) /* Channel 2 command register */
201 #define DMABASE3 (*(REG32_PTR_T)(0x38400060)) /* Base address register for channel 3 */
202 #define DMACON3 (*(REG32_PTR_T)(0x38400064)) /* Configuration register for channel 3 */
203 #define DMATCNT3 (*(REG32_PTR_T)(0x38400068)) /* Transfer count register for channel 3 */
204 #define DMACADDR3 (*(REG32_PTR_T)(0x3840006C)) /* Current memory address register for channel 3 */
205 #define DMACTCNT3 (*(REG32_PTR_T)(0x38400070)) /* Current transfer count register for channel 3 */
206 #define DMACOM3 (*(REG32_PTR_T)(0x38400074)) /* Channel 3 command register */
207 #if CONFIG_CPU==S5L8701
208 #define DMABASE4 (*(REG32_PTR_T)(0x38400080)) /* Base address register for channel 4 */
209 #define DMACON4 (*(REG32_PTR_T)(0x38400084)) /* Configuration register for channel 4 */
210 #define DMATCNT4 (*(REG32_PTR_T)(0x38400088)) /* Transfer count register for channel 4 */
211 #define DMACADDR4 (*(REG32_PTR_T)(0x3840008C)) /* Current memory address register for channel 4 */
212 #define DMACTCNT4 (*(REG32_PTR_T)(0x38400090)) /* Current transfer count register for channel 4 */
213 #define DMACOM4 (*(REG32_PTR_T)(0x38400094)) /* Channel 4 command register */
214 #define DMABASE5 (*(REG32_PTR_T)(0x384000A0)) /* Base address register for channel 5 */
215 #define DMACON5 (*(REG32_PTR_T)(0x384000A4)) /* Configuration register for channel 5 */
216 #define DMATCNT5 (*(REG32_PTR_T)(0x384000A8)) /* Transfer count register for channel 5 */
217 #define DMACADDR5 (*(REG32_PTR_T)(0x384000AC)) /* Current memory address register for channel 5 */
218 #define DMACTCNT5 (*(REG32_PTR_T)(0x384000B0)) /* Current transfer count register for channel 5 */
219 #define DMACOM5 (*(REG32_PTR_T)(0x384000B4)) /* Channel 5 command register */
220 #define DMABASE6 (*(REG32_PTR_T)(0x384000C0)) /* Base address register for channel 6 */
221 #define DMACON6 (*(REG32_PTR_T)(0x384000C4)) /* Configuration register for channel 6 */
222 #define DMATCNT6 (*(REG32_PTR_T)(0x384000C8)) /* Transfer count register for channel 6 */
223 #define DMACADDR6 (*(REG32_PTR_T)(0x384000CC)) /* Current memory address register for channel 6 */
224 #define DMACTCNT6 (*(REG32_PTR_T)(0x384000D0)) /* Current transfer count register for channel 6 */
225 #define DMACOM6 (*(REG32_PTR_T)(0x384000D4)) /* Channel 6 command register */
226 #define DMABASE7 (*(REG32_PTR_T)(0x384000E0)) /* Base address register for channel 7 */
227 #define DMACON7 (*(REG32_PTR_T)(0x384000E4)) /* Configuration register for channel 7 */
228 #define DMATCNT7 (*(REG32_PTR_T)(0x384000E8)) /* Transfer count register for channel 7 */
229 #define DMACADDR7 (*(REG32_PTR_T)(0x384000EC)) /* Current memory address register for channel 7 */
230 #define DMACTCNT7 (*(REG32_PTR_T)(0x384000F0)) /* Current transfer count register for channel 7 */
231 #define DMACOM7 (*(REG32_PTR_T)(0x384000F4)) /* Channel 7 command register */
232 #define DMABASE8 (*(REG32_PTR_T)(0x38400100)) /* Base address register for channel 8 */
233 #define DMACON8 (*(REG32_PTR_T)(0x38400104)) /* Configuration register for channel 8 */
234 #define DMATCNT8 (*(REG32_PTR_T)(0x38400108)) /* Transfer count register for channel 8 */
235 #define DMACADDR8 (*(REG32_PTR_T)(0x3840010C)) /* Current memory address register for channel 8 */
236 #define DMACTCNT8 (*(REG32_PTR_T)(0x38400110)) /* Current transfer count register for channel 8 */
237 #define DMACOM8 (*(REG32_PTR_T)(0x38400114)) /* Channel 8 command register */
238 #define DMAALLST (*(REG32_PTR_T)(0x38400180)) /* All channel status register */
240 #define DMAALLST (*(REG32_PTR_T)(0x38400100)) /* All channel status register */
242 #define DMACON_DEVICE_SHIFT 30
243 #define DMACON_DIRECTION_SHIFT 29
244 #define DMACON_DATA_SIZE_SHIFT 22
245 #define DMACON_BURST_LEN_SHIFT 19
246 #define DMACOM_START 4
247 #define DMACOM_CLEARBOTHDONE 7
248 #define DMAALLST_WCOM0 (1 << 0)
249 #define DMAALLST_HCOM0 (1 << 1)
250 #define DMAALLST_DMABUSY0 (1 << 2)
251 #define DMAALLST_HOLD_SKIP (1 << 3)
252 #define DMAALLST_WCOM1 (1 << 4)
253 #define DMAALLST_HCOM1 (1 << 5)
254 #define DMAALLST_DMABUSY1 (1 << 6)
255 #define DMAALLST_WCOM2 (1 << 8)
256 #define DMAALLST_HCOM2 (1 << 9)
257 #define DMAALLST_DMABUSY2 (1 << 10)
258 #define DMAALLST_WCOM3 (1 << 12)
259 #define DMAALLST_HCOM3 (1 << 13)
260 #define DMAALLST_DMABUSY3 (1 << 14)
261 #define DMAALLST_CHAN0_MASK (0xF << 0)
262 #define DMAALLST_CHAN1_MASK (0xF << 4)
263 #define DMAALLST_CHAN2_MASK (0xF << 8)
264 #define DMAALLST_CHAN3_MASK (0xF << 12)
266 /* 10. REAL TIMER CLOCK (RTC) */
267 #define RTCCON (*(REG32_PTR_T)(0x3D200000)) /* RTC Control Register */
268 #define RTCRST (*(REG32_PTR_T)(0x3D200004)) /* RTC Round Reset Register */
269 #define RTCALM (*(REG32_PTR_T)(0x3D200008)) /* RTC Alarm Control Register */
270 #define ALMSEC (*(REG32_PTR_T)(0x3D20000C)) /* Alarm Second Data Register */
271 #define ALMMIN (*(REG32_PTR_T)(0x3D200010)) /* Alarm Minute Data Register */
272 #define ALMHOUR (*(REG32_PTR_T)(0x3D200014)) /* Alarm Hour Data Register */
273 #define ALMDATE (*(REG32_PTR_T)(0x3D200018)) /* Alarm Date Data Register */
274 #define ALMDAY (*(REG32_PTR_T)(0x3D20001C)) /* Alarm Day of Week Data Register */
275 #define ALMMON (*(REG32_PTR_T)(0x3D200020)) /* Alarm Month Data Register */
276 #define ALMYEAR (*(REG32_PTR_T)(0x3D200024)) /* Alarm Year Data Register */
277 #define BCDSEC (*(REG32_PTR_T)(0x3D200028)) /* BCD Second Register */
278 #define BCDMIN (*(REG32_PTR_T)(0x3D20002C)) /* BCD Minute Register */
279 #define BCDHOUR (*(REG32_PTR_T)(0x3D200030)) /* BCD Hour Register */
280 #define BCDDATE (*(REG32_PTR_T)(0x3D200034)) /* BCD Date Register */
281 #define BCDDAY (*(REG32_PTR_T)(0x3D200038)) /* BCD Day of Week Register */
282 #define BCDMON (*(REG32_PTR_T)(0x3D20003C)) /* BCD Month Register */
283 #define BCDYEAR (*(REG32_PTR_T)(0x3D200040)) /* BCD Year Register */
284 #define RTCIM (*(REG32_PTR_T)(0x3D200044)) /* RTC Interrupt Mode Register */
285 #define RTCPEND (*(REG32_PTR_T)(0x3D200048)) /* RTC Interrupt Pending Register */
287 /* 09. WATCHDOG TIMER*/
288 #define WDTCON (*(REG32_PTR_T)(0x3C800000)) /* Control Register */
289 #define WDTCNT (*(REG32_PTR_T)(0x3C800004)) /* 11-bits internal counter */
291 /* 11. 16 BIT TIMER */
292 #define TACON (*(REG32_PTR_T)(0x3C700000)) /* Control Register for timer A */
293 #define TACMD (*(REG32_PTR_T)(0x3C700004)) /* Command Register for timer A */
294 #define TADATA0 (*(REG32_PTR_T)(0x3C700008)) /* Data0 Register */
295 #define TADATA1 (*(REG32_PTR_T)(0x3C70000C)) /* Data1 Register */
296 #define TAPRE (*(REG32_PTR_T)(0x3C700010)) /* Pre-scale register */
297 #define TACNT (*(REG32_PTR_T)(0x3C700014)) /* Counter register */
298 #define TBCON (*(REG32_PTR_T)(0x3C700020)) /* Control Register for timer B */
299 #define TBCMD (*(REG32_PTR_T)(0x3C700024)) /* Command Register for timer B */
300 #define TBDATA0 (*(REG32_PTR_T)(0x3C700028)) /* Data0 Register */
301 #define TBDATA1 (*(REG32_PTR_T)(0x3C70002C)) /* Data1 Register */
302 #define TBPRE (*(REG32_PTR_T)(0x3C700030)) /* Pre-scale register */
303 #define TBCNT (*(REG32_PTR_T)(0x3C700034)) /* Counter register */
304 #define TCCON (*(REG32_PTR_T)(0x3C700040)) /* Control Register for timer C */
305 #define TCCMD (*(REG32_PTR_T)(0x3C700044)) /* Command Register for timer C */
306 #define TCDATA0 (*(REG32_PTR_T)(0x3C700048)) /* Data0 Register */
307 #define TCDATA1 (*(REG32_PTR_T)(0x3C70004C)) /* Data1 Register */
308 #define TCPRE (*(REG32_PTR_T)(0x3C700050)) /* Pre-scale register */
309 #define TCCNT (*(REG32_PTR_T)(0x3C700054)) /* Counter register */
310 #define TDCON (*(REG32_PTR_T)(0x3C700060)) /* Control Register for timer D */
311 #define TDCMD (*(REG32_PTR_T)(0x3C700064)) /* Command Register for timer D */
312 #define TDDATA0 (*(REG32_PTR_T)(0x3C700068)) /* Data0 Register */
313 #define TDDATA1 (*(REG32_PTR_T)(0x3C70006C)) /* Data1 Register */
314 #define TDPRE (*(REG32_PTR_T)(0x3C700070)) /* Pre-scale register */
315 #define TDCNT (*(REG32_PTR_T)(0x3C700074)) /* Counter register */
316 #define FIVE_USEC_TIMER (((uint64_t)(*(REG32_PTR_T)(0x3C700080)) << 32) \
317 | (*(REG32_PTR_T)(0x3C700084))) /* 64bit 5usec timer */
318 #define USEC_TIMER (FIVE_USEC_TIMER * 5) /* usecs */
320 /* 12. NAND FLASH CONTROLER */
321 #if CONFIG_CPU==S5L8701
322 #define FMC_BASE 0x39400000
324 #define FMC_BASE 0x3C200000
326 #define FMCTRL0 (*(REG32_PTR_T)(FMC_BASE + 0x0000)) /* Control Register0 */
327 #define FMCTRL1 (*(REG32_PTR_T)(FMC_BASE + 0x0004)) /* Control Register1 */
328 #define FMCMD (*(REG32_PTR_T)(FMC_BASE + 0x0008)) /* Command Register */
329 #define FMADDR0 (*(REG32_PTR_T)(FMC_BASE + 0x000C)) /* Address Register0 */
330 #define FMADDR1 (*(REG32_PTR_T)(FMC_BASE + 0x0010)) /* Address Register1 */
331 #define FMADDR2 (*(REG32_PTR_T)(FMC_BASE + 0x0014)) /* Address Register2 */
332 #define FMADDR3 (*(REG32_PTR_T)(FMC_BASE + 0x0018)) /* Address Register3 */
333 #define FMADDR4 (*(REG32_PTR_T)(FMC_BASE + 0x001C)) /* Address Register4 */
334 #define FMADDR5 (*(REG32_PTR_T)(FMC_BASE + 0x0020)) /* Address Register5 */
335 #define FMADDR6 (*(REG32_PTR_T)(FMC_BASE + 0x0024)) /* Address Register6 */
336 #define FMADDR7 (*(REG32_PTR_T)(FMC_BASE + 0x0028)) /* Address Register7 */
337 #define FMANUM (*(REG32_PTR_T)(FMC_BASE + 0x002C)) /* Address Counter Register */
338 #define FMDNUM (*(REG32_PTR_T)(FMC_BASE + 0x0030)) /* Data Counter Register */
339 #define FMDATAW0 (*(REG32_PTR_T)(FMC_BASE + 0x0034)) /* Write Data Register0 */
340 #define FMDATAW1 (*(REG32_PTR_T)(FMC_BASE + 0x0038)) /* Write Data Register1 */
341 #define FMDATAW2 (*(REG32_PTR_T)(FMC_BASE + 0x003C)) /* Write Data Register2 */
342 #define FMDATAW3 (*(REG32_PTR_T)(FMC_BASE + 0x0040)) /* Write Data Register3 */
343 #define FMCSTAT (*(REG32_PTR_T)(FMC_BASE + 0x0048)) /* Status Register */
344 #define FMSYND0 (*(REG32_PTR_T)(FMC_BASE + 0x004C)) /* Hamming Syndrome0 */
345 #define FMSYND1 (*(REG32_PTR_T)(FMC_BASE + 0x0050)) /* Hamming Syndrome1 */
346 #define FMSYND2 (*(REG32_PTR_T)(FMC_BASE + 0x0054)) /* Hamming Syndrome2 */
347 #define FMSYND3 (*(REG32_PTR_T)(FMC_BASE + 0x0058)) /* Hamming Syndrome3 */
348 #define FMSYND4 (*(REG32_PTR_T)(FMC_BASE + 0x005C)) /* Hamming Syndrome4 */
349 #define FMSYND5 (*(REG32_PTR_T)(FMC_BASE + 0x0060)) /* Hamming Syndrome5 */
350 #define FMSYND6 (*(REG32_PTR_T)(FMC_BASE + 0x0064)) /* Hamming Syndrome6 */
351 #define FMSYND7 (*(REG32_PTR_T)(FMC_BASE + 0x0068)) /* Hamming Syndrome7 */
352 #define FMFIFO (*(REG32_PTR_T)(FMC_BASE + 0x0080)) /* WRITE/READ FIFO FIXME */
353 #define RSCRTL (*(REG32_PTR_T)(FMC_BASE + 0x0100)) /* Reed-Solomon Control Register */
354 #define RSPARITY0_0 (*(REG32_PTR_T)(FMC_BASE + 0x0110)) /* On-the-fly Parity Register0[31:0] */
355 #define RSPARITY0_1 (*(REG32_PTR_T)(FMC_BASE + 0x0114)) /* On-the-fly Parity Register0[63:32] */
356 #define RSPARITY0_2 (*(REG32_PTR_T)(FMC_BASE + 0x0118)) /* On-the-fly Parity Register0[71:64] */
357 #define RSPARITY1_0 (*(REG32_PTR_T)(FMC_BASE + 0x0120)) /* On-the-fly Parity Register1[31:0] */
358 #define RSPARITY1_1 (*(REG32_PTR_T)(FMC_BASE + 0x0124)) /* On-the-fly Parity Register1[63:32] */
359 #define RSPARITY1_2 (*(REG32_PTR_T)(FMC_BASE + 0x0128)) /* On-the-fly Parity Register1[71:64] */
360 #define RSPARITY2_0 (*(REG32_PTR_T)(FMC_BASE + 0x0130)) /* On-the-fly Parity Register2[31:0] */
361 #define RSPARITY2_1 (*(REG32_PTR_T)(FMC_BASE + 0x0134)) /* On-the-fly Parity Register2[63:32] */
362 #define RSPARITY2_2 (*(REG32_PTR_T)(FMC_BASE + 0x0138)) /* On-the-fly Parity Register2[71:64] */
363 #define RSPARITY3_0 (*(REG32_PTR_T)(FMC_BASE + 0x0140)) /* On-the-fly Parity Register3[31:0] */
364 #define RSPARITY3_1 (*(REG32_PTR_T)(FMC_BASE + 0x0144)) /* On-the-fly Parity Register3[63:32] */
365 #define RSPARITY3_2 (*(REG32_PTR_T)(FMC_BASE + 0x0148)) /* On-the-fly Parity Register3[71:64] */
366 #define RSSYND0_0 (*(REG32_PTR_T)(FMC_BASE + 0x0150)) /* On-the-fly Synd Register0[31:0] */
367 #define RSSYND0_1 (*(REG32_PTR_T)(FMC_BASE + 0x0154)) /* On-the-fly Synd Register0[63:32] */
368 #define RSSYND0_2 (*(REG32_PTR_T)(FMC_BASE + 0x0158)) /* On-the-fly Synd Register0[71:64] */
369 #define RSSYND1_0 (*(REG32_PTR_T)(FMC_BASE + 0x0160)) /* On-the-fly Synd Register1[31:0] */
370 #define RSSYND1_1 (*(REG32_PTR_T)(FMC_BASE + 0x0164)) /* On-the-fly Synd Register1[63:32] */
371 #define RSSYND1_2 (*(REG32_PTR_T)(FMC_BASE + 0x0168)) /* On-the-fly Synd Register1[71:64] */
372 #define RSSYND2_0 (*(REG32_PTR_T)(FMC_BASE + 0x0170)) /* On-the-fly Synd Register2[31:0] */
373 #define RSSYND2_1 (*(REG32_PTR_T)(FMC_BASE + 0x0174)) /* On-the-fly Synd Register2[63:32] */
374 #define RSSYND2_2 (*(REG32_PTR_T)(FMC_BASE + 0x0178)) /* On-the-fly Synd Register2[71:64] */
375 #define RSSYND3_0 (*(REG32_PTR_T)(FMC_BASE + 0x0180)) /* On-the-fly Synd Register3[31:0] */
376 #define RSSYND3_1 (*(REG32_PTR_T)(FMC_BASE + 0x0184)) /* On-the-fly Synd Register3[63:32] */
377 #define RSSYND3_2 (*(REG32_PTR_T)(FMC_BASE + 0x0188)) /* On-the-fly Synd Register3[71:64] */
378 #define FLAGSYND (*(REG32_PTR_T)(FMC_BASE + 0x0190)) /* On-the-fly ECC Result Flag */
379 #define FMCTRL0_ENABLEDMA (1 << 10)
380 #define FMCTRL0_UNK1 (1 << 11)
381 #define FMCTRL1_DOTRANSADDR (1 << 0)
382 #define FMCTRL1_DOREADDATA (1 << 1)
383 #define FMCTRL1_DOWRITEDATA (1 << 2)
384 #define FMCTRL1_CLEARWFIFO (1 << 6)
385 #define FMCTRL1_CLEARRFIFO (1 << 7)
386 #define FMCSTAT_RBB (1 << 0)
387 #define FMCSTAT_RBBDONE (1 << 1)
388 #define FMCSTAT_CMDDONE (1 << 2)
389 #define FMCSTAT_ADDRDONE (1 << 3)
390 #define FMCSTAT_BANK0READY (1 << 4)
391 #define FMCSTAT_BANK1READY (1 << 5)
392 #define FMCSTAT_BANK2READY (1 << 6)
393 #define FMCSTAT_BANK3READY (1 << 7)
395 /* 13. SECURE DIGITAL CARD INTERFACE (SDCI) */
396 #define SDCI_CTRL (*(REG32_PTR_T)(0x3C300000)) /* Control Register */
397 #define SDCI_DCTRL (*(REG32_PTR_T)(0x3C300004)) /* Data Control Register */
398 #define SDCI_CMD (*(REG32_PTR_T)(0x3C300008)) /* Command Register */
399 #define SDCI_ARGU (*(REG32_PTR_T)(0x3C30000C)) /* Argument Register */
400 #define SDCI_STATE (*(REG32_PTR_T)(0x3C300010)) /* State Register */
401 #define SDCI_STAC (*(REG32_PTR_T)(0x3C300014)) /* Status Clear Register */
402 #define SDCI_DSTA (*(REG32_PTR_T)(0x3C300018)) /* Data Status Register */
403 #define SDCI_FSTA (*(REG32_PTR_T)(0x3C30001C)) /* FIFO Status Register */
404 #define SDCI_RESP0 (*(REG32_PTR_T)(0x3C300020)) /* Response0 Register */
405 #define SDCI_RESP1 (*(REG32_PTR_T)(0x3C300024)) /* Response1 Register */
406 #define SDCI_RESP2 (*(REG32_PTR_T)(0x3C300028)) /* Response2 Register */
407 #define SDCI_RESP3 (*(REG32_PTR_T)(0x3C30002C)) /* Response3 Register */
408 #define SDCI_CLKDIV (*(REG32_PTR_T)(0x3C300030)) /* Clock Divider Register */
409 #define SDIO_CSR (*(REG32_PTR_T)(0x3C300034)) /* SDIO Control & Status Register */
410 #define SDIO_IRQ (*(REG32_PTR_T)(0x3C300038)) /* Interrupt Source Register */
412 /* 14. MEMORY STICK HOST CONTROLLER */
413 #define MSPRE (*(REG32_PTR_T)(0x3C600000)) /* Prescaler Register */
414 #define MSINTEN (*(REG32_PTR_T)(0x3C600004)) /* Interrupt Enable Register */
415 #define MSCMD (*(REG32_PTR_T)(0x3C601000)) /* Command Register */
416 #define MSFIFO (*(REG32_PTR_T)(0x3C601008)) /* Receive/Transmit Register */
417 #define MSPP (*(REG32_PTR_T)(0x3C601010)) /* Parallel Port Control/Data Register */
418 #define MSCTRL2 (*(REG32_PTR_T)(0x3C601014)) /* Control Register 2 */
419 #define MSACD (*(REG32_PTR_T)(0x3C601018)) /* ACD Command Register */
421 /* 15. SPDIF TRANSMITTER (SPDIFOUT) */
422 #define SPDCLKCON (*(REG32_PTR_T)(0x3CB00000)) /* Clock Control Register */
423 #define SPDCON (*(REG32_PTR_T)(0x3CB00004)) /* Control Register 0020 */
424 #define SPDBSTAS (*(REG32_PTR_T)(0x3CB00008)) /* Burst Status Register */
425 #define SPDCSTAS (*(REG32_PTR_T)(0x3CB0000C)) /* Channel Status Register 0x2000 8000 */
426 #define SPDDAT (*(REG32_PTR_T)(0x3CB00010)) /* SPDIFOUT Data Buffer */
427 #define SPDCNT (*(REG32_PTR_T)(0x3CB00014)) /* Repetition Count Register */
429 /* 16. REED-SOLOMON ECC CODEC */
430 #define ECC_DATA_PTR (*(REG32_PTR_T)(0x39E00004)) /* Data Area Start Pointer */
431 #define ECC_SPARE_PTR (*(REG32_PTR_T)(0x39E00008)) /* Spare Area Start Pointer */
432 #define ECC_CTRL (*(REG32_PTR_T)(0x39E0000C)) /* ECC Control Register */
433 #define ECC_RESULT (*(REG32_PTR_T)(0x39E00010)) /* ECC Result */
434 #define ECC_UNK1 (*(REG32_PTR_T)(0x39E00014)) /* No idea what this is, but the OFW uses it on S5L8701 */
435 #define ECC_EVAL0 (*(REG32_PTR_T)(0x39E00020)) /* Error Eval0 Poly */
436 #define ECC_EVAL1 (*(REG32_PTR_T)(0x39E00024)) /* Error Eval1 Poly */
437 #define ECC_LOC0 (*(REG32_PTR_T)(0x39E00028)) /* Error Loc0 Poly */
438 #define ECC_LOC1 (*(REG32_PTR_T)(0x39E0002C)) /* Error Loc1 Poly */
439 #define ECC_PARITY0 (*(REG32_PTR_T)(0x39E00030)) /* Encode Parity0 Poly */
440 #define ECC_PARITY1 (*(REG32_PTR_T)(0x39E00034)) /* Encode Pariyt1 Poly */
441 #define ECC_PARITY2 (*(REG32_PTR_T)(0x39E00038)) /* Encode Parity2 Poly */
442 #define ECC_INT_CLR (*(REG32_PTR_T)(0x39E00040)) /* Interrupt Clear Register */
443 #define ECC_SYND0 (*(REG32_PTR_T)(0x39E00044)) /* Syndrom0 Poly */
444 #define ECC_SYND1 (*(REG32_PTR_T)(0x39E00048)) /* Syndrom1 Poly */
445 #define ECC_SYND2 (*(REG32_PTR_T)(0x39E0004C)) /* Syndrom2 Poly */
446 #define ECCCTRL_STARTDECODING (1 << 0)
447 #define ECCCTRL_STARTENCODING (1 << 1)
448 #define ECCCTRL_STARTDECNOSYND (1 << 2)
450 /* 17. IIS Tx/Rx INTERFACE */
451 #define I2SCLKCON (*(REG32_PTR_T)(0x3CA00000)) /* Clock Control Register */
452 #define I2STXCON (*(REG32_PTR_T)(0x3CA00004)) /* Tx configuration Register */
453 #define I2STXCOM (*(REG32_PTR_T)(0x3CA00008)) /* Tx command Register */
454 #define I2STXDB0 (*(REG32_PTR_T)(0x3CA00010)) /* Tx data buffer */
455 #define I2SRXCON (*(REG32_PTR_T)(0x3CA00030)) /* Rx configuration Register */
456 #define I2SRXCOM (*(REG32_PTR_T)(0x3CA00034)) /* Rx command Register */
457 #define I2SRXDB (*(REG32_PTR_T)(0x3CA00038)) /* Rx data buffer */
458 #define I2SSTATUS (*(REG32_PTR_T)(0x3CA0003C)) /* status register */
460 /* 18. IIC BUS INTERFACE */
461 #define IICCON (*(REG32_PTR_T)(0x3C900000)) /* Control Register */
462 #define IICSTAT (*(REG32_PTR_T)(0x3C900004)) /* Control/Status Register */
463 #define IICADD (*(REG32_PTR_T)(0x3C900008)) /* Bus Address Register */
464 #define IICDS (*(REG32_PTR_T)(0x3C90000C))
466 /* 19. SPI (SERIAL PERHIPERAL INTERFACE) */
467 #define SPCLKCON (*(REG32_PTR_T)(0x3CD00000)) /* Clock Control Register */
468 #define SPCON (*(REG32_PTR_T)(0x3CD00004)) /* Control Register */
469 #define SPSTA (*(REG32_PTR_T)(0x3CD00008)) /* Status Register */
470 #define SPPIN (*(REG32_PTR_T)(0x3CD0000C)) /* Pin Control Register */
471 #define SPTDAT (*(REG32_PTR_T)(0x3CD00010)) /* Tx Data Register */
472 #define SPRDAT (*(REG32_PTR_T)(0x3CD00014)) /* Rx Data Register */
473 #define SPPRE (*(REG32_PTR_T)(0x3CD00018)) /* Baud Rate Prescaler Register */
475 /* 20. ADC CONTROLLER */
476 #define ADCCON (*(REG32_PTR_T)(0x3CE00000)) /* ADC Control Register */
477 #define ADCTSC (*(REG32_PTR_T)(0x3CE00004)) /* ADC Touch Screen Control Register */
478 #define ADCDLY (*(REG32_PTR_T)(0x3CE00008)) /* ADC Start or Interval Delay Register */
479 #define ADCDAT0 (*(REG32_PTR_T)(0x3CE0000C)) /* ADC Conversion Data Register */
480 #define ADCDAT1 (*(REG32_PTR_T)(0x3CE00010)) /* ADC Conversion Data Register */
481 #define ADCUPDN (*(REG32_PTR_T)(0x3CE00014)) /* Stylus Up or Down Interrpt Register */
483 /* 21. USB 2.0 FUNCTION CONTROLER SPECIAL REGISTER */
484 #define USB_IR (*(REG32_PTR_T)(0x38800000)) /* Index Register */
485 #define USB_EIR (*(REG32_PTR_T)(0x38800004)) /* Endpoint Interrupt Register */
486 #define USB_EIER (*(REG32_PTR_T)(0x38800008)) /* Endpoint Interrupt Enable Register */
487 #define USB_FAR (*(REG32_PTR_T)(0x3880000C)) /* Function Address Register */
488 #define USB_FNR (*(REG32_PTR_T)(0x38800010)) /* Frame Number Register */
489 #define USB_EDR (*(REG32_PTR_T)(0x38800014)) /* Endpoint Direction Register */
490 #define USB_TR (*(REG32_PTR_T)(0x38800018)) /* Test Register */
491 #define USB_SSR (*(REG32_PTR_T)(0x3880001C)) /* System Status Register */
492 #define USB_SCR (*(REG32_PTR_T)(0x38800020)) /* System Control Register */
493 #define USB_EP0SR (*(REG32_PTR_T)(0x38800024)) /* EP0 Status Register */
494 #define USB_EP0CR (*(REG32_PTR_T)(0x38800028)) /* EP0 Control Register */
495 #define USB_ESR (*(REG32_PTR_T)(0x3880002C)) /* Endpoints Status Register */
496 #define USB_ECR (*(REG32_PTR_T)(0x38800030)) /* Endpoints Control Register */
497 #define USB_BRCR (*(REG32_PTR_T)(0x38800034)) /* Byte Read Count Register */
498 #define USB_BWCR (*(REG32_PTR_T)(0x38800038)) /* Byte Write Count Register */
499 #define USB_MPR (*(REG32_PTR_T)(0x3880003C)) /* Max Packet Register */
500 #define USB_MCR (*(REG32_PTR_T)(0x38800040)) /* Master Control Register */
501 #define USB_MTCR (*(REG32_PTR_T)(0x38800044)) /* Master Transfer Counter Register */
502 #define USB_MFCR (*(REG32_PTR_T)(0x38800048)) /* Master FIFO Counter Register */
503 #define USB_MTTCR1 (*(REG32_PTR_T)(0x3880004C)) /* Master Total Transfer Counter1 Register */
504 #define USB_MTTCR2 (*(REG32_PTR_T)(0x38800050)) /* Master Total Transfer Counter2 Register */
505 #define USB_EP0BR (*(REG32_PTR_T)(0x38800060)) /* EP0 Buffer Register */
506 #define USB_EP1BR (*(REG32_PTR_T)(0x38800064)) /* EP1 Buffer Register */
507 #define USB_EP2BR (*(REG32_PTR_T)(0x38800068)) /* EP2 Buffer Register */
508 #define USB_EP3BR (*(REG32_PTR_T)(0x3880006C)) /* EP3 Buffer Register */
509 #define USB_EP4BR (*(REG32_PTR_T)(0x38800070)) /* EP4 Buffer Register */
510 #define USB_EP5BR (*(REG32_PTR_T)(0x38800074)) /* EP5 Buffer Register */
511 #define USB_EP6BR (*(REG32_PTR_T)(0x38800078)) /* EP6 Buffer Register */
512 #define USB_MICR (*(REG32_PTR_T)(0x38800084)) /* Master Interface Counter Register */
513 #define USB_MBAR1 (*(REG32_PTR_T)(0x38800088)) /* Memory Base Address Register1 */
514 #define USB_MBAR2 (*(REG32_PTR_T)(0x3880008C)) /* Memory Base Address Register2 */
515 #define USB_MCAR1 (*(REG32_PTR_T)(0x38800094)) /* Memory Current Address Register1 */
516 #define USB_MCAR2 (*(REG32_PTR_T)(0x38800098)) /* Memory Current Address Register2 */
518 /* 22. USB 1.1 HOST CONTROLLER SPECIAL REGISTER */
519 #define HcRevision (*(REG32_PTR_T)(0x38600000))
520 #define HcControl (*(REG32_PTR_T)(0x38600004))
521 #define HcCommandStatus (*(REG32_PTR_T)(0x38600008))
522 #define HcInterruptStatus (*(REG32_PTR_T)(0x3860000C))
523 #define HcInterruptEnable (*(REG32_PTR_T)(0x38600010))
524 #define HcInterruptDisable (*(REG32_PTR_T)(0x38600014))
525 #define HcHCCA (*(REG32_PTR_T)(0x38600018))
526 #define HcPeriodCurrentED (*(REG32_PTR_T)(0x3860001C))
527 #define HcControlHeadED (*(REG32_PTR_T)(0x38600020))
528 #define HcControlCurrentED (*(REG32_PTR_T)(0x38600024))
529 #define HcBulkHeadED (*(REG32_PTR_T)(0x38600028))
530 #define HcBulkCurrentED (*(REG32_PTR_T)(0x3860002C))
531 #define HcDoneHead (*(REG32_PTR_T)(0x38600030))
532 #define HcFmInterval (*(REG32_PTR_T)(0x38600034))
533 #define HcFmRemaining (*(REG32_PTR_T)(0x38600038))
534 #define HcFmNumber (*(REG32_PTR_T)(0x3860003C))
535 #define HcPeriodicStart (*(REG32_PTR_T)(0x38600040))
536 #define HcLSThreshold (*(REG32_PTR_T)(0x38600044))
537 #define HcRhDescriptorA (*(REG32_PTR_T)(0x38600048))
538 #define HcRhDescriptorB (*(REG32_PTR_T)(0x3860004C))
539 #define HcRhStatus (*(REG32_PTR_T)(0x38600050))
540 #define HcRhPortStatus (*(REG32_PTR_T)(0x38600054))
542 /* 23. USB 2.0 PHY CONTROL */
543 #define PHYCTRL (*(REG32_PTR_T)(0x3C400000)) /* USB2.0 PHY Control Register */
544 #define PHYPWR (*(REG32_PTR_T)(0x3C400004)) /* USB2.0 PHY Power Control Register */
545 #define URSTCON (*(REG32_PTR_T)(0x3C400008)) /* USB Reset Control Register */
546 #define UCLKCON (*(REG32_PTR_T)(0x3C400010)) /* USB Clock Control Register */
548 /* 24. GPIO PORT CONTROL */
549 #define PCON0 (*(REG32_PTR_T)(0x3CF00000)) /* Configures the pins of port 0 */
550 #define PDAT0 (*(REG32_PTR_T)(0x3CF00004)) /* The data register for port 0 */
551 #define PCON1 (*(REG32_PTR_T)(0x3CF00010)) /* Configures the pins of port 1 */
552 #define PDAT1 (*(REG32_PTR_T)(0x3CF00014)) /* The data register for port 1 */
553 #define PCON2 (*(REG32_PTR_T)(0x3CF00020)) /* Configures the pins of port 2 */
554 #define PDAT2 (*(REG32_PTR_T)(0x3CF00024)) /* The data register for port 2 */
555 #define PCON3 (*(REG32_PTR_T)(0x3CF00030)) /* Configures the pins of port 3 */
556 #define PDAT3 (*(REG32_PTR_T)(0x3CF00034)) /* The data register for port 3 */
557 #define PCON4 (*(REG32_PTR_T)(0x3CF00040)) /* Configures the pins of port 4 */
558 #define PDAT4 (*(REG32_PTR_T)(0x3CF00044)) /* The data register for port 4 */
559 #define PCON5 (*(REG32_PTR_T)(0x3CF00050)) /* Configures the pins of port 5 */
560 #define PDAT5 (*(REG32_PTR_T)(0x3CF00054)) /* The data register for port 5 */
561 #define PUNK5 (*(REG32_PTR_T)(0x3CF0005C)) /* Unknown thing for port 5 */
562 #define PCON6 (*(REG32_PTR_T)(0x3CF00060)) /* Configures the pins of port 6 */
563 #define PDAT6 (*(REG32_PTR_T)(0x3CF00064)) /* The data register for port 6 */
564 #define PCON7 (*(REG32_PTR_T)(0x3CF00070)) /* Configures the pins of port 7 */
565 #define PDAT7 (*(REG32_PTR_T)(0x3CF00074)) /* The data register for port 7 */
566 #define PCON10 (*(REG32_PTR_T)(0x3CF000A0)) /* Configures the pins of port 10 */
567 #define PDAT10 (*(REG32_PTR_T)(0x3CF000A4)) /* The data register for port 10 */
568 #define PCON11 (*(REG32_PTR_T)(0x3CF000B0)) /* Configures the pins of port 11 */
569 #define PDAT11 (*(REG32_PTR_T)(0x3CF000B4)) /* The data register for port 11 */
570 #define PCON13 (*(REG32_PTR_T)(0x3CF000D0)) /* Configures the pins of port 13 */
571 #define PDAT13 (*(REG32_PTR_T)(0x3CF000D4)) /* The data register for port 13 */
572 #define PCON14 (*(REG32_PTR_T)(0x3CF000E0)) /* Configures the pins of port 14 */
573 #define PDAT14 (*(REG32_PTR_T)(0x3CF000E4)) /* The data register for port 14 */
574 #define PCON15 (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port 15 */
575 #define PUNK15 (*(REG32_PTR_T)(0x3CF000FC)) /* Unknown thing for port 15 */
576 #define PCON_ASRAM (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port nor flash */
577 #define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */
582 #define ULCON0 (*(REG32_PTR_T)(0x3CC00000)) /* Line Control Register */
583 #define UCON0 (*(REG32_PTR_T)(0x3CC00004)) /* Control Register */
584 #define UFCON0 (*(REG32_PTR_T)(0x3CC00008)) /* FIFO Control Register */
585 #define UMCON0 (*(REG32_PTR_T)(0x3CC0000C)) /* Modem Control Register */
586 #define UTRSTAT0 (*(REG32_PTR_T)(0x3CC00010)) /* Tx/Rx Status Register */
587 #define UERSTAT0 (*(REG32_PTR_T)(0x3CC00014)) /* Rx Error Status Register */
588 #define UFSTAT0 (*(REG32_PTR_T)(0x3CC00018)) /* FIFO Status Register */
589 #define UMSTAT0 (*(REG32_PTR_T)(0x3CC0001C)) /* Modem Status Register */
590 #define UTXH0 (*(REG32_PTR_T)(0x3CC00020)) /* Transmit Buffer Register */
591 #define URXH0 (*(REG32_PTR_T)(0x3CC00024)) /* Receive Buffer Register */
592 #define UBRDIV0 (*(REG32_PTR_T)(0x3CC00028)) /* Baud Rate Divisor Register */
595 #define ULCON1 (*(REG32_PTR_T)(0x3CC08000)) /* Line Control Register */
596 #define UCON1 (*(REG32_PTR_T)(0x3CC08004)) /* Control Register */
597 #define UFCON1 (*(REG32_PTR_T)(0x3CC08008)) /* FIFO Control Register */
598 #define UMCON1 (*(REG32_PTR_T)(0x3CC0800C)) /* Modem Control Register */
599 #define UTRSTAT1 (*(REG32_PTR_T)(0x3CC08010)) /* Tx/Rx Status Register */
600 #define UERSTAT1 (*(REG32_PTR_T)(0x3CC08014)) /* Rx Error Status Register */
601 #define UFSTAT1 (*(REG32_PTR_T)(0x3CC08018)) /* FIFO Status Register */
602 #define UMSTAT1 (*(REG32_PTR_T)(0x3CC0801C)) /* Modem Status Register */
603 #define UTXH1 (*(REG32_PTR_T)(0x3CC08020)) /* Transmit Buffer Register */
604 #define URXH1 (*(REG32_PTR_T)(0x3CC08024)) /* Receive Buffer Register */
605 #define UBRDIV1 (*(REG32_PTR_T)(0x3CC08028)) /* Baud Rate Divisor Register */
607 /* 26. LCD INTERFACE CONTROLLER */
608 #if CONFIG_CPU==S5L8700
609 #define LCD_BASE 0x3C100000
610 #else /* CPU_S5L8701 */
611 #define LCD_BASE 0x38600000
614 #define LCD_CON (*(REG32_PTR_T)(LCD_BASE+0x00)) /* Control register. */
615 #define LCD_WCMD (*(REG32_PTR_T)(LCD_BASE+0x04)) /* Write command register. */
616 #define LCD_RCMD (*(REG32_PTR_T)(LCD_BASE+0x0C)) /* Read command register. */
617 #define LCD_RDATA (*(REG32_PTR_T)(LCD_BASE+0x10)) /* Read data register. */
618 #define LCD_DBUFF (*(REG32_PTR_T)(LCD_BASE+0x14)) /* Read Data buffer */
619 #define LCD_INTCON (*(REG32_PTR_T)(LCD_BASE+0x18)) /* Interrupt control register */
620 #define LCD_STATUS (*(REG32_PTR_T)(LCD_BASE+0x1C)) /* LCD Interface status 0106 */
621 #define LCD_PHTIME (*(REG32_PTR_T)(LCD_BASE+0x20)) /* Phase time register 0060 */
622 #define LCD_RST_TIME (*(REG32_PTR_T)(LCD_BASE+0x24)) /* Reset active period 07FF */
623 #define LCD_DRV_RST (*(REG32_PTR_T)(LCD_BASE+0x28)) /* Reset drive signal */
624 #define LCD_WDATA (*(REG32_PTR_T)(LCD_BASE+0x40)) /* Write data register (0x40...0x5C) FIXME */
626 /* 27. CLCD CONTROLLER */
627 #define LCDCON1 (*(REG32_PTR_T)(0x39200000)) /* LCD control 1 register */
628 #define LCDCON2 (*(REG32_PTR_T)(0x39200004)) /* LCD control 2 register */
629 #define LCDTCON1 (*(REG32_PTR_T)(0x39200008)) /* LCD time control 1 register */
630 #define LCDTCON2 (*(REG32_PTR_T)(0x3920000C)) /* LCD time control 2 register */
631 #define LCDTCON3 (*(REG32_PTR_T)(0x39200010)) /* LCD time control 3 register */
632 #define LCDOSD1 (*(REG32_PTR_T)(0x39200014)) /* LCD OSD control 1 register */
633 #define LCDOSD2 (*(REG32_PTR_T)(0x39200018)) /* LCD OSD control 2 register */
634 #define LCDOSD3 (*(REG32_PTR_T)(0x3920001C)) /* LCD OSD control 3 register */
635 #define LCDB1SADDR1 (*(REG32_PTR_T)(0x39200020)) /* Frame buffer start address register for Back-Ground buffer 1 */
636 #define LCDB2SADDR1 (*(REG32_PTR_T)(0x39200024)) /* Frame buffer start address register for Back-Ground buffer 2 */
637 #define LCDF1SADDR1 (*(REG32_PTR_T)(0x39200028)) /* Frame buffer start address register for Fore-Ground (OSD) buffer 1 */
638 #define LCDF2SADDR1 (*(REG32_PTR_T)(0x3920002C)) /* Frame buffer start address register for Fore-Ground (OSD) buffer 2 */
639 #define LCDB1SADDR2 (*(REG32_PTR_T)(0x39200030)) /* Frame buffer end address register for Back-Ground buffer 1 */
640 #define LCDB2SADDR2 (*(REG32_PTR_T)(0x39200034)) /* Frame buffer end address register for Back-Ground buffer 2 */
641 #define LCDF1SADDR2 (*(REG32_PTR_T)(0x39200038)) /* Frame buffer end address register for Fore-Ground (OSD) buffer 1 */
642 #define LCDF2SADDR2 (*(REG32_PTR_T)(0x3920003C)) /* Frame buffer end address register for Fore-Ground (OSD) buffer 2 */
643 #define LCDB1SADDR3 (*(REG32_PTR_T)(0x39200040)) /* Virtual screen address set for Back-Ground buffer 1 */
644 #define LCDB2SADDR3 (*(REG32_PTR_T)(0x39200044)) /* Virtual screen address set for Back-Ground buffer 2 */
645 #define LCDF1SADDR3 (*(REG32_PTR_T)(0x39200048)) /* Virtual screen address set for Fore-Ground(OSD) buffer 1 */
646 #define LCDF2SADDR3 (*(REG32_PTR_T)(0x3920004C)) /* Virtual screen address set for Fore-Ground(OSD) buffer 2 */
647 #define LCDINTCON (*(REG32_PTR_T)(0x39200050)) /* Indicate the LCD interrupt control register */
648 #define LCDKEYCON (*(REG32_PTR_T)(0x39200054)) /* Color key control register */
649 #define LCDCOLVAL (*(REG32_PTR_T)(0x39200058)) /* Color key value ( transparent value) register */
650 #define LCDBGCON (*(REG32_PTR_T)(0x3920005C)) /* Back-Ground color control */
651 #define LCDFGCON (*(REG32_PTR_T)(0x39200060)) /* Fore-Ground color control */
652 #define LCDDITHMODE (*(REG32_PTR_T)(0x39200064)) /* Dithering mode register. */
654 /* 28. ATA CONTROLLER */
655 #define ATA_CONTROL (*(REG32_PTR_T)(0x38E00000)) /* Enable and clock down status */
656 #define ATA_STATUS (*(REG32_PTR_T)(0x38E00004)) /* Status */
657 #define ATA_COMMAND (*(REG32_PTR_T)(0x38E00008)) /* Command */
658 #define ATA_SWRST (*(REG32_PTR_T)(0x38E0000C)) /* Software reset */
659 #define ATA_IRQ (*(REG32_PTR_T)(0x38E00010)) /* Interrupt sources */
660 #define ATA_IRQ_MASK (*(REG32_PTR_T)(0x38E00014)) /* Interrupt mask */
661 #define ATA_CFG (*(REG32_PTR_T)(0x38E00018)) /* Configuration for ATA interface */
662 #define ATA_PIO_TIME (*(REG32_PTR_T)(0x38E0002C)) /* PIO timing */
663 #define ATA_UDMA_TIME (*(REG32_PTR_T)(0x38E00030)) /* UDMA timing */
664 #define ATA_XFR_NUM (*(REG32_PTR_T)(0x38E00034)) /* Transfer number */
665 #define ATA_XFR_CNT (*(REG32_PTR_T)(0x38E00038)) /* Current transfer count */
666 #define ATA_TBUF_START (*(REG32_PTR_T)(0x38E0003C)) /* Start address of track buffer */
667 #define ATA_TBUF_SIZE (*(REG32_PTR_T)(0x38E00040)) /* Size of track buffer */
668 #define ATA_SBUF_START (*(REG32_PTR_T)(0x38E00044)) /* Start address of Source buffer1 */
669 #define ATA_SBUF_SIZE (*(REG32_PTR_T)(0x38E00048)) /* Size of source buffer1 */
670 #define ATA_CADR_TBUF (*(REG32_PTR_T)(0x38E0004C)) /* Current write address of track buffer */
671 #define ATA_CADR_SBUF (*(REG32_PTR_T)(0x38E00050)) /* Current read address of source buffer */
672 #define ATA_PIO_DTR (*(REG32_PTR_T)(0x38E00054)) /* PIO device data register */
673 #define ATA_PIO_FED (*(REG32_PTR_T)(0x38E00058)) /* PIO device Feature/Error register */
674 #define ATA_PIO_SCR (*(REG32_PTR_T)(0x38E0005C)) /* PIO sector count register */
675 #define ATA_PIO_LLR (*(REG32_PTR_T)(0x38E00060)) /* PIO device LBA low register */
676 #define ATA_PIO_LMR (*(REG32_PTR_T)(0x38E00064)) /* PIO device LBA middle register */
677 #define ATA_PIO_LHR (*(REG32_PTR_T)(0x38E00068)) /* PIO device LBA high register */
678 #define ATA_PIO_DVR (*(REG32_PTR_T)(0x38E0006C)) /* PIO device register */
679 #define ATA_PIO_CSD (*(REG32_PTR_T)(0x38E00070)) /* PIO device command/status register */
680 #define ATA_PIO_DAD (*(REG32_PTR_T)(0x38E00074)) /* PIO control/alternate status register */
681 #define ATA_PIO_READY (*(REG32_PTR_T)(0x38E00078)) /* PIO data read/write ready */
682 #define ATA_PIO_RDATA (*(REG32_PTR_T)(0x38E0007C)) /* PIO read data from device register */
683 #define BUS_FIFO_STATUS (*(REG32_PTR_T)(0x38E00080)) /* Reserved */
684 #define ATA_FIFO_STATUS (*(REG32_PTR_T)(0x38E00084)) /* Reserved */
687 #define REG_ONE (*(REG32_PTR_T)(0x3D100000)) /* Receive the first 32 bits from a fuse box */
688 #define REG_TWO (*(REG32_PTR_T)(0x3D100004)) /* Receive the other 8 bits from a fuse box */
691 #if CONFIG_CPU==S5L8701
693 /* Hardware AES crypto unit - S5L8701 only */
694 #define ICONSRCPND (*(REG32_PTR_T)(0x39C00000))
695 #define ICONINTPND (*(REG32_PTR_T)(0x39C00010))
696 #define AESCONTROL (*(REG32_PTR_T)(0x39800000))
697 #define AESGO (*(REG32_PTR_T)(0x39800004))
698 #define AESUNKREG0 (*(REG32_PTR_T)(0x39800008))
699 #define AESSTATUS (*(REG32_PTR_T)(0x3980000C))
700 #define AESUNKREG1 (*(REG32_PTR_T)(0x39800010))
701 #define AESKEYLEN (*(REG32_PTR_T)(0x39800014))
702 #define AESOUTSIZE (*(REG32_PTR_T)(0x39800018))
703 #define AESOUTADDR (*(REG32_PTR_T)(0x39800020))
704 #define AESINSIZE (*(REG32_PTR_T)(0x39800024))
705 #define AESINADDR (*(REG32_PTR_T)(0x39800028))
706 #define AESAUXSIZE (*(REG32_PTR_T)(0x3980002C))
707 #define AESAUXADDR (*(REG32_PTR_T)(0x39800030))
708 #define AESSIZE3 (*(REG32_PTR_T)(0x39800034))
709 #define AESTYPE (*(REG32_PTR_T)(0x3980006C))
710 #define HASHCTRL (*(REG32_PTR_T)(0x3C600000))
711 #define HASHRESULT ((REG32_PTR_T)(0x3C600020))
712 #define HASHDATAIN ((REG32_PTR_T)(0x3C600040))
714 /* Clickwheel controller - S5L8701 only */
715 #define WHEEL00 (*((uint32_t volatile*)(0x3C200000)))
716 #define WHEEL04 (*((uint32_t volatile*)(0x3C200004)))
717 #define WHEEL08 (*((uint32_t volatile*)(0x3C200008)))
718 #define WHEEL0C (*((uint32_t volatile*)(0x3C20000C)))
719 #define WHEEL10 (*((uint32_t volatile*)(0x3C200010)))
720 #define WHEELINT (*((uint32_t volatile*)(0x3C200014)))
721 #define WHEELRX (*((uint32_t volatile*)(0x3C200018)))
722 #define WHEELTX (*((uint32_t volatile*)(0x3C20001C)))
724 /* Synopsys OTG - S5L8701 only */
725 #define OTGBASE 0x38800000
726 #define PHYBASE 0x3C400000
727 #define SYNOPSYSOTG_CLOCK 0
728 #define SYNOPSYSOTG_AHBCFG (GAHBCFG_dma_enable | (GAHBCFG_INT_DMA_BURST_INCR4 << GAHBCFG_hburstlen_bitp) | GAHBCFG_glblintrmsk)
730 #endif /* CONFIG_CPU==S5L8701 */
