firmware/export/s3c2440.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 by Marcoen Hirschberg
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef __S3C2440_H__
  22 #define __S3C2440_H__
  23
  24 #define CACHEALIGN_BITS (5)
  25
  26 #define LCD_BUFFER_SIZE (320*240*2)
  27 #define TTB_SIZE (0x4000)
  28 /* must be 16Kb (0x4000) aligned */
  29 #define TTB_BASE_ADDR   (0x30000000 + (MEMORYSIZE*1024*1024) - TTB_SIZE)
  30 #define LCD_FRAME_ADDR  (TTB_BASE_ADDR - LCD_BUFFER_SIZE)
  31
  32 #define TTB_BASE   ((unsigned long *)TTB_BASE_ADDR) /* End of memory */
  33 #define FRAME           ((unsigned short *)LCD_FRAME_ADDR)  /* Right before TTB */
  34
  35 /* Memory Controllers */
  36
  37 #define BWSCON (*(volatile unsigned long *)0x48000000) /* Bus width & wait status control */
  38 #define BANKCON0 (*(volatile unsigned long *)0x48000004) /* Boot ROM control */
  39 #define BANKCON1 (*(volatile unsigned long *)0x48000008) /* BANK1 control */
  40 #define BANKCON2 (*(volatile unsigned long *)0x4800000C) /* BANK2 control */
  41 #define BANKCON3 (*(volatile unsigned long *)0x48000010) /* BANK3 control */
  42 #define BANKCON4 (*(volatile unsigned long *)0x48000014) /* BANK4 control */
  43 #define BANKCON5 (*(volatile unsigned long *)0x48000018) /* BANK5 control */
  44 #define BANKCON6 (*(volatile unsigned long *)0x4800001C) /* BANK6 control */
  45 #define BANKCON7 (*(volatile unsigned long *)0x48000020) /* BANK7 control */
  46 #define REFRESH (*(volatile unsigned long *)0x48000024) /* DRAM/SDRAM refresh control */
  47 #define BANKSIZE (*(volatile unsigned long *)0x48000028) /* Flexible bank size */
  48 #define MRSRB6 (*(volatile unsigned long *)0x4800002C) /* Mode register set for SDRAM BANK6 */
  49 #define MRSRB7 (*(volatile unsigned long *)0x48000030) /* Mode register set for SDRAM BANK7 */
  50
  51 /* USB Host Controller */
  52
  53 #define OHCI_BASE 0x49000000
  54
  55 /* Interrupt Controller */
  56
  57 #define SRCPND (*(volatile unsigned long *)0x4A000000) /* Interrupt request status */
  58 #define INTMOD (*(volatile unsigned long *)0x4A000004) /* Interrupt mode control */
  59 #define INTMSK (*(volatile unsigned long *)0x4A000008) /* Interrupt mask control */
  60 #define PRIORITY (*(volatile unsigned long *)0x4A00000C) /* IRQ priority control */
  61 #define INTPND (*(volatile unsigned long *)0x4A000010) /* Interrupt request status */
  62 #define INTOFFSET (*(volatile unsigned long *)0x4A000014) /* Interrupt request source offset */
  63 #define SUBSRCPND (*(volatile unsigned long *)0x4A000018) /* Sub source pending */
  64 #define INTSUBMSK (*(volatile unsigned long *)0x4A00001C) /* Interrupt sub mask */
  65
  66 /* Interrupt indexes - INTOFFSET - IRQ mode only */
  67 /* Arbiter 5 => Arbiter 6 Req 5 */
  68 #define ADC_INTOFFSET       31 /* REQ4 */
  69 #define RTC_INTOFFSET       30 /* REQ3 */
  70 #define SPI1_INTOFFSET      29 /* REQ2 */
  71 #define UART0_INTOFFSET     28 /* REQ1 */
  72 /* Arbiter 4 => Arbiter 6 Req 4 */
  73 #define IIC_INTOFFSET       27 /* REQ5 */
  74 #define USBH_INTOFFSET      26 /* REQ4 */
  75 #define USBD_INTOFFSET      25 /* REQ3 */
  76 #define NFCON_INTOFFSET     24 /* REQ2 */
  77 #define UART1_INTOFFSET     23 /* REQ1 */
  78 #define SPI0_INTOFFSET      22 /* REQ0 */
  79 /* Arbiter 3 => Arbiter 6 Req 3  */
  80 #define SDI_INTOFFSET       21 /* REQ5 */
  81 #define DMA3_INTOFFSET      20 /* REQ4 */
  82 #define DMA2_INTOFFSET      19 /* REQ3 */
  83 #define DMA1_INTOFFSET      18 /* REQ2 */
  84 #define DMA0_INTOFFSET      17 /* REQ1 */
  85 #define LCD_INTOFFSET       16 /* REQ0 */
  86 /* Arbiter 2 => Arbiter 6 Req 2 */
  87 #define UART2_INTOFFSET     15 /* REQ5 */
  88 #define TIMER4_INTOFFSET    14 /* REQ4 */
  89 #define TIMER3_INTOFFSET    13 /* REQ3 */
  90 #define TIMER2_INTOFFSET    12 /* REQ2 */
  91 #define TIMER1_INTOFFSET    11 /* REQ1 */
  92 #define TIMER0_INTOFFSET    10 /* REQ0 */
  93 /* Arbiter 1 => Arbiter 6 Req 1  */
  94 #define WDT_AC97_INTOFFSET   9 /* REQ5 */
  95 #define TICK_INTOFFSET       8 /* REQ4 */
  96 #define nBATT_FLT_INTOFFSET  7 /* REQ3 */
  97 #define CAM_INTOFFSET        6 /* REQ2 */
  98 #define EINT8_23_INTOFFSET   5 /* REQ1 */
  99 #define EINT4_7_INTOFFSET    4 /* REQ0 */
 100 /* Arbiter 0  => Arbiter 6 Req 0 */
 101 #define EINT3_INTOFFSET      3 /* REQ4 */
 102 #define EINT2_INTOFFSET      2 /* REQ3 */
 103 #define EINT1_INTOFFSET      1 /* REQ2 */
 104 #define EINT0_INTOFFSET      0 /* REQ1 */
 105
 106 /* Interrupt bitmasks - SRCPND, INTMOD, INTMSK, INTPND */
 107 /* Arbiter 5 => Arbiter 6 Req 5 */
 108 #define ADC_MASK       (1 << 31) /* REQ4 */
 109 #define RTC_MASK       (1 << 30) /* REQ3 */
 110 #define SPI1_MASK      (1 << 29) /* REQ2 */
 111 #define UART0_MASK     (1 << 28) /* REQ1 */
 112 /* Arbiter 4 => Arbiter 6 Req 4 */
 113 #define IIC_MASK       (1 << 27) /* REQ5 */
 114 #define USBH_MASK      (1 << 26) /* REQ4 */
 115 #define USBD_MASK      (1 << 25) /* REQ3 */
 116 #define NFCON_MASK     (1 << 24) /* REQ2 */
 117 #define UART1_MASK     (1 << 23) /* REQ1 */
 118 #define SPI0_MASK      (1 << 22) /* REQ0 */
 119 /* Arbiter 3 => Arbiter 6 Req 3  */
 120 #define SDI_MASK       (1 << 21) /* REQ5 */
 121 #define DMA3_MASK      (1 << 20) /* REQ4 */
 122 #define DMA2_MASK      (1 << 19) /* REQ3 */
 123 #define DMA1_MASK      (1 << 18) /* REQ2 */
 124 #define DMA0_MASK      (1 << 17) /* REQ1 */
 125 #define LCD_MASK       (1 << 16) /* REQ0 */
 126 /* Arbiter 2 => Arbiter 6 Req 2 */
 127 #define UART2_MASK     (1 << 15) /* REQ5 */
 128 #define TIMER4_MASK    (1 << 14) /* REQ4 */
 129 #define TIMER3_MASK    (1 << 13) /* REQ3 */
 130 #define TIMER2_MASK    (1 << 12) /* REQ2 */
 131 #define TIMER1_MASK    (1 << 11) /* REQ1 */
 132 #define TIMER0_MASK    (1 << 10) /* REQ0 */
 133 /* Arbiter 1 => Arbiter 6 Req 1  */
 134 #define WDT_AC97_MASK  (1 <<  9) /* REQ5 */
 135 #define TICK_MASK      (1 <<  8) /* REQ4 */
 136 #define nBATT_FLT_MASK (1 <<  7) /* REQ3 */
 137 #define CAM_MASK       (1 <<  6) /* REQ2 */
 138 #define EINT8_23_MASK  (1 <<  5) /* REQ1 */
 139 #define EINT4_7_MASK   (1 <<  4) /* REQ0 */
 140 /* Arbiter 0  => Arbiter 6 Req 0 */
 141 #define EINT3_MASK     (1 <<  3) /* REQ4 */
 142 #define EINT2_MASK     (1 <<  2) /* REQ3 */
 143 #define EINT1_MASK     (1 <<  1) /* REQ2 */
 144 #define EINT0_MASK     (1 <<  0) /* REQ1 */
 145
 146 /* DMA */
 147
 148 #define DISRC0 (*(volatile unsigned long *)0x4B000000) /* DMA 0 initial source */
 149 #define DISRCC0 (*(volatile unsigned long *)0x4B000004) /* DMA 0 initial source control */
 150 #define DIDST0 (*(volatile unsigned long *)0x4B000008) /* DMA 0 initial destination */
 151 #define DIDSTC0 (*(volatile unsigned long *)0x4B00000C) /* DMA 0 initial destination control */
 152 #define DCON0 (*(volatile unsigned long *)0x4B000010) /* DMA 0 control */
 153 #define DSTAT0 (*(volatile unsigned long *)0x4B000014) /* DMA 0 count */
 154 #define DCSRC0 (*(volatile unsigned long *)0x4B000018) /* DMA 0 current source */
 155 #define DCDST0 (*(volatile unsigned long *)0x4B00001C) /* DMA 0 current destination */
 156 #define DMASKTRIG0 (*(volatile unsigned long *)0x4B000020) /* DMA 0 mask trigger */
 157 #define DISRC1 (*(volatile unsigned long *)0x4B000040) /* DMA 1 initial source */
 158 #define DISRCC1 (*(volatile unsigned long *)0x4B000044) /* DMA 1 initial source control */
 159 #define DIDST1 (*(volatile unsigned long *)0x4B000048) /* DMA 1 initial destination */
 160 #define DIDSTC1 (*(volatile unsigned long *)0x4B00004C) /* DMA 1 initial destination control */
 161 #define DCON1 (*(volatile unsigned long *)0x4B000050) /* DMA 1 control */
 162 #define DSTAT1 (*(volatile unsigned long *)0x4B000054) /* DMA 1 count */
 163 #define DCSRC1 (*(volatile unsigned long *)0x4B000058) /* DMA 1 current source */
 164 #define DCDST1 (*(volatile unsigned long *)0x4B00005C) /* DMA 1 current destination */
 165 #define DMASKTRIG1 (*(volatile unsigned long *)0x4B000060) /* DMA 1 mask trigger */
 166 #define DISRC2 (*(volatile unsigned long *)0x4B000080) /* DMA 2 initial source */
 167 #define DISRCC2 (*(volatile unsigned long *)0x4B000084) /* DMA 2 initial source control */
 168 #define DIDST2 (*(volatile unsigned long *)0x4B000088) /* DMA 2 initial destination */
 169 #define DIDSTC2 (*(volatile unsigned long *)0x4B00008C) /* DMA 2 initial destination control */
 170 #define DCON2 (*(volatile unsigned long *)0x4B000090) /* DMA 2 control */
 171 #define DSTAT2 (*(volatile unsigned long *)0x4B000094) /* DMA 2 count */
 172 #define DCSRC2 (*(volatile unsigned long *)0x4B000098) /* DMA 2 current source */
 173 #define DCDST2 (*(volatile unsigned long *)0x4B00009C) /* DMA 2 current destination */
 174 #define DMASKTRIG2 (*(volatile unsigned long *)0x4B0000A0) /* DMA 2 mask trigger */
 175 #define DISRC3 (*(volatile unsigned long *)0x4B0000C0) /* DMA 3 initial source */
 176 #define DISRCC3 (*(volatile unsigned long *)0x4B0000C4) /* DMA 3 initial source control */
 177 #define DIDST3 (*(volatile unsigned long *)0x4B0000C8) /* DMA 3 initial destination */
 178 #define DIDSTC3 (*(volatile unsigned long *)0x4B0000CC) /* DMA 3 initial destination control */
 179 #define DCON3 (*(volatile unsigned long *)0x4B0000D0) /* DMA 3 control */
 180 #define DSTAT3 (*(volatile unsigned long *)0x4B0000D4) /* DMA 3 count */
 181 #define DCSRC3 (*(volatile unsigned long *)0x4B0000D8) /* DMA 3 current source */
 182 #define DCDST3 (*(volatile unsigned long *)0x4B0000DC) /* DMA 3 current destination */
 183 #define DMASKTRIG3 (*(volatile unsigned long *)0x4B0000E0) /* DMA 3 mask trigger */
 184
 185 #define DISRCC_LOC_AHB              (0 << 1)
 186 #define DISRCC_LOC_APB              (1 << 1)
 187 #define DISRCC_INC_AUTO             (0 << 0)
 188 #define DISRCC_INC_FIXED            (1 << 0)
 189
 190 #define DIDSTC_CHK_INT_TC_ZERO      (0 << 2)
 191 #define DIDSTC_CHK_INT_AFTER_RELOAD (1 << 2)
 192 #define DIDSTC_LOC_AHB              (0 << 1)
 193 #define DIDSTC_LOC_APB              (1 << 1)
 194 #define DIDSTC_INC_AUTO             (0 << 0)
 195 #define DIDSTC_INC_FIXED            (1 << 0)
 196
 197 #define DCON_DMD_HS                 (1 << 31)
 198 #define DCON_SYNC_APB               (0 << 30)
 199 #define DCON_SYNC_AHB               (1 << 30)
 200 #define DCON_INT                    (1 << 29)
 201 #define DCON_TSZ                    (1 << 28)
 202 #define DCON_SERVMODE_WHOLE         (1 << 27)
 203 #define DCON_HWSRCSEL               (1 << 24)
 204 #define DCON_HW_SEL                 (1 << 23)
 205 #define DCON_NO_RELOAD              (1 << 22)
 206 #define DCON_DSZ_MASK               (3 << 20)
 207 #define DCON_DSZ_BYTE               (0 << 20)
 208 #define DCON_DSZ_HALF_WORD          (1 << 20)
 209 #define DCON_DSZ_WORD               (2 << 20)
 210 #define DCON_TC                     (1 << 0)
 211
 212 #define DSTAT_STAT_BUSY             (1 << 20)
 213 #define DSTAT_CURR_TC               (1 << 0)
 214
 215 #define DMASKTRIG_STOP               (1 << 2)
 216 #define DMASKTRIG_ON                 (1 << 1)
 217 #define DMASKTRIG_SW_TRIG            (1 << 0)
 218
 219 /* Get DMA request source (HWSRCSEL) from the map for the specified channel */
 220 #define DMA_GET_SRC(map,channel)  ( ((map) << (channel*8)) & 0xff)
 221
 222 #define DMA_CH0(x) (x<<0)
 223 #define DMA_CH1(x) (x<<8)
 224 #define DMA_CH2(x) (x<<16)
 225 #define DMA_CH3(x) (x<<24)
 226
 227 #define DMA_INVALID 0xff
 228 #define DMA_INV0    DMA_CH0(DMA_INVALID)
 229 #define DMA_INV1    DMA_CH1(DMA_INVALID)
 230 #define DMA_INV2    DMA_CH2(DMA_INVALID)
 231 #define DMA_INV3    DMA_CH3(DMA_INVALID)
 232
 233 /* This map encodes the DMA request source field (HWSRCSEL) since it's value
 234  * depends on channel number and peripheral type.
 235  */
 236 #define DMA_SRC_MAP_XDREQ0    (DMA_CH0(0) | DMA_INV1   | DMA_INV2   | DMA_INV3)
 237 #define DMA_SRC_MAP_XDREQ1    (DMA_INV0   | DMA_CH1(0) | DMA_INV2   | DMA_INV3)
 238 #define DMA_SRC_MAP_USB_EP1   (DMA_CH0(4) | DMA_INV1   | DMA_INV2   | DMA_INV3)
 239 #define DMA_SRC_MAP_USB_EP2   (DMA_INV0   | DMA_CH1(4) | DMA_INV2   | DMA_INV3)
 240 #define DMA_SRC_MAP_USB_EP3   (DMA_INV0   | DMA_INV1   | DMA_CH2(4) | DMA_INV3)
 241 #define DMA_SRC_MAP_USB_EP4   (DMA_INV0   | DMA_INV1   | DMA_INV2   | DMA_CH3(4))
 242 #define DMA_SRC_MAP_SDI       (DMA_CH0(2) | DMA_CH1(6) | DMA_CH2(2) | DMA_CH3(1))
 243 #define DMA_SRC_MAP_UART0     (DMA_CH0(1) | DMA_INV1   | DMA_INV2   | DMA_INV3)
 244 #define DMA_SRC_MAP_UART1     (DMA_INV0   | DMA_CH1(1) | DMA_INV2   | DMA_INV3)
 245 #define DMA_SRC_MAP_UART2     (DMA_INV0   | DMA_INV1   | DMA_INV2   | DMA_CH3(0))
 246 #define DMA_SRC_MAP_I2SSDO    (DMA_CH0(5) | DMA_INV1   | DMA_CH2(0) | DMA_INV3)
 247 #define DMA_SRC_MAP_I2SSDI    (DMA_INV0   | DMA_CH1(2) | DMA_CH2(1) | DMA_INV3)
 248 #define DMA_SRC_MAP_PCMOUT    (DMA_INV0   | DMA_CH1(5) | DMA_INV2   | DMA_CH3(6))
 249 #define DMA_SRC_MAP_PCMIN     (DMA_CH0(6) | DMA_INV1   | DMA_CH2(5) | DMA_INV3)
 250 #define DMA_SRC_MAP_MICIN     (DMA_INV0   | DMA_INV1   | DMA_CH2(6) | DMA_CH3(5))
 251 #define DMA_SRC_MAP_SPI0      (DMA_INV0   | DMA_CH1(3) | DMA_INV2   | DMA_INV3)
 252 #define DMA_SRC_MAP_SPI1      (DMA_INV0   | DMA_INV1   | DMA_INV2   | DMA_CH3(2))
 253 #define DMA_SRC_MAP_TIMER     (DMA_CH0(3) | DMA_INV1   | DMA_CH2(3) | DMA_CH3(3))
 254
 255 /* Clock & Power Management */
 256
 257 #define LOCKTIME (*(volatile unsigned long *)0x4C000000) /* PLL lock time counter */
 258 #define MPLLCON (*(volatile unsigned long *)0x4C000004) /* MPLL control */
 259 #define UPLLCON (*(volatile unsigned long *)0x4C000008) /* UPLL control */
 260 #define CLKCON (*(volatile unsigned long *)0x4C00000C) /* Clock generator control */
 261 #define CLKSLOW (*(volatile unsigned long *)0x4C000010) /* Slow clock control */
 262 #define CLKDIVN (*(volatile unsigned long *)0x4C000014) /* Clock divider control */
 263 #define CAMDIVN (*(volatile unsigned long *)0x4C000018) /* Camera clock divider control */
 264
 265 /* LCD Controller */
 266
 267 #define LCDCON1 (*(volatile unsigned long *)0x4D000000) /* LCD control 1 */
 268 #define LCDCON2 (*(volatile unsigned long *)0x4D000004) /* LCD control 2 */
 269 #define LCDCON3 (*(volatile unsigned long *)0x4D000008) /* LCD control 3 */
 270 #define LCDCON4 (*(volatile unsigned long *)0x4D00000C) /* LCD control 4 */
 271 #define LCDCON5 (*(volatile unsigned long *)0x4D000010) /* LCD control 5 */
 272 #define LCDSADDR1 (*(volatile unsigned long *)0x4D000014) /* STN/TFT: frame buffer start address 1 */
 273 #define LCDSADDR2 (*(volatile unsigned long *)0x4D000018) /* STN/TFT: frame buffer start address 2 */
 274 #define LCDSADDR3 (*(volatile unsigned long *)0x4D00001C) /* STN/TFT: virtual screen address set */
 275 #define REDLUT (*(volatile unsigned long *)0x4D000020) /* STN: red lookup table */
 276 #define GREENLUT (*(volatile unsigned long *)0x4D000024) /* STN: green lookup table */
 277 #define BLUELUT (*(volatile unsigned long *)0x4D000028) /* STN: blue lookup table */
 278 #define DITHMODE (*(volatile unsigned long *)0x4D00004C) /* STN: dithering mode */
 279 #define TPAL (*(volatile unsigned long *)0x4D000050) /* TFT: temporary palette */
 280 #define LCDINTPND (*(volatile unsigned long *)0x4D000054) /* LCD interrupt pending */
 281 #define LCDSRCPND (*(volatile unsigned long *)0x4D000058) /* LCD interrupt source */
 282 #define LCDINTMSK (*(volatile unsigned long *)0x4D00005C) /* LCD interrupt mask */
 283 #define TCONSEL (*(volatile unsigned long *)0x4D000060) /* TCON(LPC3600/LCC3600) control */
 284
 285 /* NAND Flash */
 286
 287 #define NFCONF (*(volatile unsigned long *)0x4E000000) /* NAND flash configuration */
 288 #define NFCONT (*(volatile unsigned long *)0x4E000004) /* NAND flash control */
 289 #define NFCMD (*(volatile unsigned long *)0x4E000008) /* NAND flash command */
 290 #define NFADDR (*(volatile unsigned long *)0x4E00000C) /* NAND flash address */
 291 #define NFDATA (*(volatile unsigned long *)0x4E000010) /* NAND flash data */
 292 #define NFMECC0 (*(volatile unsigned long *)0x4E000014) /* NAND flash main area ECC0/1 */
 293 #define NFMECC1 (*(volatile unsigned long *)0x4E000018) /* NAND flash main area ECC2/3 */
 294 #define NFSECC (*(volatile unsigned long *)0x4E00001C) /* NAND flash spare area ECC */
 295 #define NFSTAT (*(volatile unsigned long *)0x4E000020) /* NAND flash operation status */
 296 #define NFESTAT0 (*(volatile unsigned long *)0x4E000024) /* NAND flash ECC status for I/O[7:0] */
 297 #define NFESTAT1 (*(volatile unsigned long *)0x4E000028) /* NAND flash ECC status for I/O[15:8] */
 298 #define NFMECCSTAT0 (*(volatile unsigned long *)0x4E00002C) /* NAND flash main area ECC0 status */
 299 #define NFMECCSTAT1 (*(volatile unsigned long *)0x4E000030) /* NAND flash main area ECC1 status */
 300 #define NFSECCSTAT (*(volatile unsigned long *)0x4E000034) /* NAND flash spare area ECC status */
 301 #define NFSBLK (*(volatile unsigned long *)0x4E000038) /* NAND flash start block address */
 302 #define NFEBLK (*(volatile unsigned long *)0x4E00003C) /* NAND flash end block address */
 303
 304 /* Camera Interface */
 305
 306 #define CISRCFMT (*(volatile unsigned long *)0x4F000000) /* Input source format */
 307 #define CIWDOFST (*(volatile unsigned long *)0x4F000004) /* Window offset register */
 308 #define CIGCTRL (*(volatile unsigned long *)0x4F000008) /* Global control register */
 309 #define CICOYSA1 (*(volatile unsigned long *)0x4F000018) /* Y 1st frame start address for codec DMA */
 310 #define CICOYSA2 (*(volatile unsigned long *)0x4F00001C) /* Y 2nd frame start address for codec DMA */
 311 #define CICOYSA3 (*(volatile unsigned long *)0x4F000020) /* Y 3nd frame start address for codec DMA */
 312 #define CICOYSA4 (*(volatile unsigned long *)0x4F000024) /* Y 4th frame start address for codec DMA */
 313 #define CICOCBSA1 (*(volatile unsigned long *)0x4F000028) /* Cb 1st frame start address for codec DMA */
 314 #define CICOCBSA2 (*(volatile unsigned long *)0x4F00002C) /* Cb 2nd frame start address for codec DMA */
 315 #define CICOCBSA3 (*(volatile unsigned long *)0x4F000030) /* Cb 3nd frame start address for codec DMA */
 316 #define CICOCBSA4 (*(volatile unsigned long *)0x4F000034) /* Cb 4th frame start address for codec DMA */
 317 #define CICOCRSA1 (*(volatile unsigned long *)0x4F000038) /* Cr 1st frame start address for codec DMA */
 318 #define CICOCRSA2 (*(volatile unsigned long *)0x4F00003C) /* Cr 2nd frame start address for codec DMA */
 319 #define CICOCRSA3 (*(volatile unsigned long *)0x4F000040) /* Cr 3nd frame start address for codec DMA */
 320 #define CICOCRSA4 (*(volatile unsigned long *)0x4F000044) /* Cr 4th frame start address for codec DMA */
 321 #define CICOTRGFMT (*(volatile unsigned long *)0x4F000048) /* Target image format of codec DMA */
 322 #define CICOCTRL (*(volatile unsigned long *)0x4F00004C)
 323
 324 /* Codec DMA control related */
 325
 326 #define CICOSCPRERATIO (*(volatile unsigned long *)0x4F000050) /* Codec pre-scaler ratio control */
 327 #define CICOSCPREDST (*(volatile unsigned long *)0x4F000054) /* Codec pre-scaler destination format */
 328 #define CICOSCCTRL (*(volatile unsigned long *)0x4F000058) /* Codec main-scaler control */
 329 #define CICOTAREA (*(volatile unsigned long *)0x4F00005C) /* Codec scaler target area */
 330 #define CICOSTATUS (*(volatile unsigned long *)0x4F000064) /* Codec path status */
 331 #define CIPRCLRSA1 (*(volatile unsigned long *)0x4F00006C) /* RGB 1st frame start address for preview DMA */
 332 #define CIPRCLRSA2 (*(volatile unsigned long *)0x4F000070) /* RGB 2nd frame start address for preview DMA */
 333 #define CIPRCLRSA3 (*(volatile unsigned long *)0x4F000074) /* RGB 3nd frame start address for preview DMA */
 334 #define CIPRCLRSA4 (*(volatile unsigned long *)0x4F000078) /* RGB 4th frame start address for preview DMA */
 335 #define CIPRTRGFMT (*(volatile unsigned long *)0x4F00007C) /* Target image format of preview DMA */
 336 #define CIPRCTRL (*(volatile unsigned long *)0x4F000080) /* Preview DMA control related */
 337 #define CIPRSCPRERATIO (*(volatile unsigned long *)0x4F000084) /* Preview pre-scaler ratio control */
 338 #define CIPRSCPREDST (*(volatile unsigned long *)0x4F000088) /* Preview pre-scaler destination format */
 339 #define CIPRSCCTRL (*(volatile unsigned long *)0x4F00008C) /* Preview main-scaler control */
 340 #define CIPRTAREA (*(volatile unsigned long *)0x4F000090) /* Preview scaler target area */
 341 #define CIPRSTATUS (*(volatile unsigned long *)0x4F000098) /* Preview path status */
 342 #define CIIMGCPT (*(volatile unsigned long *)0x4F0000A0) /* Image capture enable command */
 343
 344 /* UART */
 345
 346 #define ULCON0 (*(volatile unsigned long *)0x50000000) /* UART 0 line control */
 347 #define UCON0 (*(volatile unsigned long *)0x50000004) /* UART 0 control */
 348 #define UFCON0 (*(volatile unsigned long *)0x50000008) /* UART 0 FIFO control */
 349 #define UMCON0 (*(volatile unsigned long *)0x5000000C) /* UART 0 modem control */
 350 #define UTRSTAT0 (*(volatile unsigned long *)0x50000010) /* UART 0 Tx/Rx status */
 351 #define UERSTAT0 (*(volatile unsigned long *)0x50000014) /* UART 0 Rx error status */
 352 #define UFSTAT0 (*(volatile unsigned long *)0x50000018) /* UART 0 FIFO status */
 353 #define UMSTAT0 (*(volatile unsigned long *)0x5000001C) /* UART 0 modem status */
 354 #define UTXH0 (*(volatile unsigned char *)0x50000020) /* UART 0 transmission hold */
 355 #define URXH0 (*(volatile unsigned char *)0x50000024) /* UART 0 receive buffer */
 356 #define UBRDIV0 (*(volatile unsigned long *)0x50000028) /* UART 0 baud rate divisor */
 357 #define ULCON1 (*(volatile unsigned long *)0x50004000) /* UART 1 line control */
 358 #define UCON1 (*(volatile unsigned long *)0x50004004) /* UART 1 control */
 359 #define UFCON1 (*(volatile unsigned long *)0x50004008) /* UART 1 FIFO control */
 360 #define UMCON1 (*(volatile unsigned long *)0x5000400C) /* UART 1 modem control */
 361 #define UTRSTAT1 (*(volatile unsigned long *)0x50004010) /* UART 1 Tx/Rx status */
 362 #define UERSTAT1 (*(volatile unsigned long *)0x50004014) /* UART 1 Rx error status */
 363 #define UFSTAT1 (*(volatile unsigned long *)0x50004018) /* UART 1 FIFO status */
 364 #define UMSTAT1 (*(volatile unsigned long *)0x5000401C) /* UART 1 modem status */
 365 #define UTXH1 (*(volatile unsigned char*)0x50004020) /* UART 1 transmission hold */
 366 #define URXH1 (*(volatile unsigned char*)0x50004024) /* UART 1 receive buffer */
 367 #define UBRDIV1 (*(volatile unsigned long *)0x50004028) /* UART 1 baud rate divisor */
 368 #define ULCON2 (*(volatile unsigned long *)0x50008000) /* UART 2 line control */
 369 #define UCON2 (*(volatile unsigned long *)0x50008004) /* UART 2 control */
 370 #define UFCON2 (*(volatile unsigned long *)0x50008008) /* UART 2 FIFO control */
 371 #define UTRSTAT2 (*(volatile unsigned long *)0x50008010) /* UART 2 Tx/Rx status */
 372 #define UERSTAT2 (*(volatile unsigned long *)0x50008014) /* UART 2 Rx error status */
 373 #define UFSTAT2 (*(volatile unsigned long *)0x50008018) /* UART 2 FIFO status */
 374 #define UTXH2 (*(volatile unsigned char*)0x50008020) /* UART 2 transmission hold */
 375 #define URXH2 (*(volatile unsigned char*)0x50008024) /* UART 2 receive buffer */
 376 #define UBRDIV2 (*(volatile unsigned long *)0x50008028) /* UART 2 baud rate divisor */
 377
 378 /* PWM Timer */
 379
 380 #define TCFG0 (*(volatile unsigned long *)0x51000000) /* Timer configuration */
 381 #define TCFG1 (*(volatile unsigned long *)0x51000004) /* Timer configuration */
 382 #define TCON (*(volatile unsigned long *)0x51000008) /* Timer control */
 383 #define TCNTB0 (*(volatile unsigned long *)0x5100000C) /* Timer count buffer 0 */
 384 #define TCMPB0 (*(volatile unsigned long *)0x51000010) /* Timer compare buffer 0 */
 385 #define TCNTO0 (*(volatile unsigned long *)0x51000014) /* Timer count observation 0 */
 386 #define TCNTB1 (*(volatile unsigned long *)0x51000018) /* Timer count buffer 1 */
 387 #define TCMPB1 (*(volatile unsigned long *)0x5100001C) /* Timer compare buffer 1 */
 388 #define TCNTO1 (*(volatile unsigned long *)0x51000020) /* Timer count observation 1 */
 389 #define TCNTB2 (*(volatile unsigned long *)0x51000024) /* Timer count buffer 2 */
 390 #define TCMPB2 (*(volatile unsigned long *)0x51000028) /* Timer compare buffer 2 */
 391 #define TCNTO2 (*(volatile unsigned long *)0x5100002C) /* Timer count observation 2 */
 392 #define TCNTB3 (*(volatile unsigned long *)0x51000030) /* Timer count buffer 3 */
 393 #define TCMPB3 (*(volatile unsigned long *)0x51000034) /* Timer compare buffer 3 */
 394 #define TCNTO3 (*(volatile unsigned long *)0x51000038) /* Timer count observation 3 */
 395 #define TCNTB4 (*(volatile unsigned long *)0x5100003C) /* Timer count buffer 4 */
 396 #define TCNTO4 (*(volatile unsigned long *)0x51000040) /* Timer count observation 4 */
 397
 398 /* USB Device */
 399
 400 #define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) /* Function address */
 401 #define PWR_REG (*(volatile unsigned char *)0x52000144) /* Power management */
 402 #define EP_INT_REG (*(volatile unsigned char *)0x52000148) /* EP interrupt pending and clear */
 403 #define USB_INT_REG (*(volatile unsigned char *)0x52000158) /* USB interrupt pending and clear */
 404 #define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015C) /* Interrupt enable */
 405 #define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016C) /* Interrupt enable */
 406 #define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) /* Frame number lower byte */
 407 #define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) /* Frame number higher byte */
 408 #define INDEX_REG (*(volatile unsigned char *)0x52000178) /* Register index */
 409 #define EP0_CSR (*(volatile unsigned char *)0x52000184) /* Endpoint 0 status */
 410 #define IN_CSR1_REG (*(volatile unsigned char *)0x52000184) /* In endpoint control status */
 411 #define IN_CSR2_REG (*(volatile unsigned char *)0x52000188) /* In endpoint control status */
 412 #define MAXP_REG (*(volatile unsigned char *)0x52000180) /* Endpoint max packet */
 413 #define OUT_CSR1_REG (*(volatile unsigned char *)0x52000190) /* Out endpoint control status */
 414 #define OUT_CSR2_REG (*(volatile unsigned char *)0x52000194) /* Out endpoint control status */
 415 #define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) /* Endpoint out write count */
 416 #define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019C) /* Endpoint out write count */
 417 #define EP0_FIFO (*(volatile unsigned char *)0x520001C0) /* Endpoint 0 FIFO */
 418 #define EP1_FIFO (*(volatile unsigned char *)0x520001C4) /* Endpoint 1 FIFO */
 419 #define EP2_FIFO (*(volatile unsigned char *)0x520001C8) /* Endpoint 2 FIFO */
 420 #define EP3_FIFO (*(volatile unsigned char *)0x520001CC) /* Endpoint 3 FIFO */
 421 #define EP4_FIFO (*(volatile unsigned char *)0x520001D0) /* Endpoint 4 FIFO */
 422 #define EP1_DMA_CON (*(volatile unsigned char *)0x52000200) /* EP1 DMA Interface control */
 423 #define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) /* EP1 DMA Tx unit counter */
 424 #define EP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) /* EP1 DMA Tx FIFO counter */
 425 #define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020C) /* EP1 DMA Total Tx counter */
 426 #define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210) /* EP1 DMA Total Tx counter */
 427 #define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214) /* EP1 DMA Total Tx counter */
 428 #define EP2_DMA_CON (*(volatile unsigned char *)0x52000218) /* EP2 DMA interface control */
 429 #define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021C) /* EP2 DMA Tx Unit counter */
 430 #define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) /* EP2 DMA Tx FIFO counter */
 431 #define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) /* EP2 DMA total Tx counter */
 432 #define EP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228) /* EP2 DMA total Tx counter */
 433 #define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022C) /* EP2 DMA Total Tx counter */
 434 #define EP3_DMA_CON (*(volatile unsigned char *)0x52000240) /* EP3 DMA Interface control */
 435 #define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) /* EP3 DMA Tx Unit counter */
 436 #define EP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) /* EP3 DMA Tx FIFO counter */
 437 #define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024C) /* EP3 DMA Total Tx counter */
 438 #define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250) /* EP3 DMA Total Tx counter */
 439 #define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254) /* EP3 DMA Total Tx counter */
 440 #define EP4_DMA_CON (*(volatile unsigned char *)0x52000258) /* EP4 DMA Interface control */
 441 #define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025C) /* EP4 DMA Tx Unit counter */
 442 #define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) /* EP4 DMA Tx FIFO counter */
 443 #define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) /* EP4 DMA Total Tx counter */
 444 #define EP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268) /* EP4 DMA Total Tx counter */
 445 #define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026C) /* EP4 DMA Total Tx counter */
 446
 447 /* Watchdog Timer */
 448
 449 #define WTCON (*(volatile unsigned long *)0x53000000) /* Watchdog timer mode */
 450 #define WTDAT (*(volatile unsigned long *)0x53000004) /* Watchdog timer data */
 451 #define WTCNT (*(volatile unsigned long *)0x53000008) /* Watchdog timer count */
 452
 453 /* IIC */
 454
 455 #define IICCON (*(volatile unsigned long *)0x54000000) /* IIC control  */
 456 #define IICSTAT (*(volatile unsigned long *)0x54000004) /* IIC status */
 457 #define IICADD (*(volatile unsigned long *)0x54000008) /* IIC address */
 458 #define IICDS (*(volatile unsigned long *)0x5400000C) /* IIC data shift */
 459 #define IICLC (*(volatile unsigned long *)0x54000010) /* IIC multi-master line control */
 460
 461 /* IIS */
 462
 463 #define IISCON (*(volatile unsigned long *)0x55000000) /* IIS control */
 464 #define IISMOD (*(volatile unsigned long *)0x55000004) /* IIS mode */
 465 #define IISPSR (*(volatile unsigned long *)0x55000008) /* IIS prescaler */
 466 #define IISFCON (*(volatile unsigned long *)0x5500000C) /* IIS FIFO control */
 467 #define IISFIFO (*(volatile unsigned short *)0x55000010) /* IIS FIFO entry */
 468
 469 #define IISCON_RIGHT_CHANNEL            (1 << 8)
 470 #define IISCON_TX_FIFO_NOT_EMPTY        (1 << 7)
 471 #define IISCON_RX_FIFO_NOT_FULL         (1 << 6)
 472 #define IISCON_TX_DMA_REQUEST           (1 << 5)
 473 #define IISCON_RX_DMA_REQUEST           (1 << 4)
 474 #define IISCON_TX_IDLE                  (1 << 3)
 475 #define IISCON_RX_IDLE                  (1 << 2)
 476 #define IISCON_IIS_PRESCALER_ENABLE     (1 << 1)
 477 #define IISCON_IIS_INTERFACE_ENABLE     (1 << 0)
 478
 479 #define IISMOD_MASTER_CLOCK_PCLK        (0 << 9)
 480 #define IISMOD_MASTER_CLOCK_MPLLIN      (1 << 9)
 481 #define IISMOD_MASTER_MODE              (0 << 8)
 482 #define IISMOD_SLAVE_MODE               (1 << 8)
 483 #define IISMOD_NO_TRANSFER              (0 << 6)
 484 #define IISMOD_RECEIVE_MODE             (1 << 6)
 485 #define IISMOD_TRANSMIT_MODE            (2 << 6)
 486 #define IISMOD_TRANSMIT_RECEIVE_MODE    (3 << 6)
 487 #define IISMOD_LOW_LEFT                 (0 << 5)
 488 #define IISMOD_HIGH_LEFT                (1 << 5)
 489 #define IISMOD_IIS                      (0 << 4)
 490 #define IISMOD_MSB                      (1 << 4)
 491 #define IISMOD_8_BIT                    (0 << 3)
 492 #define IISMOD_16_BIT                   (1 << 3)
 493 #define IISMOD_MASTER_CLOCK_256FS       (0 << 2)
 494 #define IISMOD_MASTER_CLOCK_384FS       (1 << 2)
 495 #define IISMOD_BIT_CLOCK_16FS           (0 << 0)
 496 #define IISMOD_BIT_CLOCK_32FS           (1 << 0)
 497 #define IISMOD_BIT_CLOCK_48FS           (2 << 0)
 498
 499 #define IISPSR_PRESCALER_A              (1 << 5)
 500 #define IISPSR_PRESCALER_B              (1 << 0)
 501
 502 /* I/O port */
 503
 504 #define GPACON (*(volatile unsigned long *)0x56000000) /* Port A control */
 505 #define GPADAT (*(volatile unsigned long *)0x56000004) /* Port A data */
 506 #define GPBCON (*(volatile unsigned long *)0x56000010) /* Port B control */
 507 #define GPBDAT (*(volatile unsigned long *)0x56000014) /* Port B data */
 508 #define GPBUP (*(volatile unsigned long *)0x56000018) /* Pull-up control B */
 509 #define GPCCON (*(volatile unsigned long *)0x56000020) /* Port C control */
 510 #define GPCDAT (*(volatile unsigned long *)0x56000024) /* Port C data */
 511 #define GPCUP (*(volatile unsigned long *)0x56000028) /* Pull-up control C */
 512 #define GPDCON (*(volatile unsigned long *)0x56000030) /* Port D control */
 513 #define GPDDAT (*(volatile unsigned long *)0x56000034) /* Port D data */
 514 #define GPDUP (*(volatile unsigned long *)0x56000038) /* Pull-up control D */
 515 #define GPECON (*(volatile unsigned long *)0x56000040) /* Port E control */
 516 #define GPEDAT (*(volatile unsigned long *)0x56000044) /* Port E data */
 517 #define GPEUP (*(volatile unsigned long *)0x56000048) /* Pull-up control E */
 518 #define GPFCON (*(volatile unsigned long *)0x56000050) /* Port F control */
 519 #define GPFDAT (*(volatile unsigned long *)0x56000054) /* Port F data */
 520 #define GPFUP (*(volatile unsigned long *)0x56000058) /* Pull-up control F */
 521 #define GPGCON (*(volatile unsigned long *)0x56000060) /* Port G control */
 522 #define GPGDAT (*(volatile unsigned long *)0x56000064) /* Port G data */
 523 #define GPGUP (*(volatile unsigned long *)0x56000068) /* Pull-up control G */
 524 #define GPHCON (*(volatile unsigned long *)0x56000070) /* Port H control */
 525 #define GPHDAT (*(volatile unsigned long *)0x56000074) /* Port H data */
 526 #define GPHUP (*(volatile unsigned long *)0x56000078) /* Pull-up control H */
 527 #define MISCCR (*(volatile unsigned long *)0x56000080) /* Miscellaneous control */
 528 #define DCLKCON (*(volatile unsigned long *)0x56000084) /* DCLK0/1 control */
 529 #define EXTINT0 (*(volatile unsigned long *)0x56000088) /* External interrupt control register 0 */
 530 #define EXTINT1 (*(volatile unsigned long *)0x5600008C) /* External interrupt control register 1 */
 531 #define EXTINT2 (*(volatile unsigned long *)0x56000090) /* External interrupt control register 2 */
 532 #define EINTFLT0 (*(volatile unsigned long *)0x56000094) /* Reserved */
 533 #define EINTFLT1 (*(volatile unsigned long *)0x56000098) /* Reserved */
 534 #define EINTFLT2 (*(volatile unsigned long *)0x5600009C) /* External interrupt filter control register 2 */
 535 #define EINTFLT3 (*(volatile unsigned long *)0x560000A0) /* External interrupt filter control register 3 */
 536 #define EINTMASK (*(volatile unsigned long *)0x560000A4) /* External interrupt mask */
 537 #define EINTPEND (*(volatile unsigned long *)0x560000A8) /* External interrupt pending */
 538 #define GSTATUS0 (*(volatile unsigned long *)0x560000AC) /* External pin status */
 539 #define GSTATUS1 (*(volatile unsigned long *)0x560000B0) /* Chip ID */
 540 #define GSTATUS2 (*(volatile unsigned long *)0x560000B4) /* Reset status */
 541 #define GSTATUS3 (*(volatile unsigned long *)0x560000B8) /* Inform register */
 542 #define GSTATUS4 (*(volatile unsigned long *)0x560000BC) /* Inform register */
 543 #define MSLCON (*(volatile unsigned long *)0x560000CC) /* Memory sleep control register */
 544 #define GPJCON (*(volatile unsigned long *)0x560000D0) /* Port J control */
 545 #define GPJDAT (*(volatile unsigned long *)0x560000D4) /* Port J data */
 546 #define GPJUP (*(volatile unsigned long *)0x560000D8) /* Pull-up control J */
 547
 548 /* RTC */
 549
 550 #define RTCCON (*(volatile unsigned char *)0x57000040) /* RTC control */
 551 #define TICNT (*(volatile unsigned char *)0x57000044) /* Tick time count */
 552 #define RTCALM (*(volatile unsigned char *)0x57000050) /* RTC alarm control */
 553 #define ALMSEC (*(volatile unsigned char *)0x57000054) /* Alarm second */
 554 #define ALMMIN (*(volatile unsigned char *)0x57000058) /* Alarm minute */
 555 #define ALMHOUR (*(volatile unsigned char *)0x5700005C) /* Alarm hour */
 556 #define ALMDATE (*(volatile unsigned char *)0x57000060) /* alarm day */
 557 #define ALMMON (*(volatile unsigned char *)0x57000064) /* Alarm month */
 558 #define ALMYEAR (*(volatile unsigned char *)0x57000068) /* Alarm year */
 559 #define BCDSEC (*(volatile unsigned char *)0x57000070) /* BCD second */
 560 #define BCDMIN (*(volatile unsigned char *)0x57000074) /* BCD minute */
 561 #define BCDHOUR (*(volatile unsigned char *)0x57000078) /* BCD hour */
 562 #define BCDDATE (*(volatile unsigned char *)0x5700007C) /* BCD day */
 563 #define BCDDAY (*(volatile unsigned char *)0x57000080) /* BCD date */
 564 #define BCDMON (*(volatile unsigned char *)0x57000084) /* BCD month */
 565 #define BCDYEAR (*(volatile unsigned char *)0x57000088) /* BCD year */
 566
 567 /* A/D Converter */
 568
 569 #define ADCCON (*(volatile unsigned long *)0x58000000) /* ADC control */
 570 #define ADCTSC (*(volatile unsigned long *)0x58000004) /* ADC touch screen control */
 571 #define ADCDLY (*(volatile unsigned long *)0x58000008) /* ADC start or interval delay */
 572 #define ADCDAT0 (*(volatile unsigned long *)0x5800000C) /* ADC conversion data */
 573 #define ADCDAT1 (*(volatile unsigned long *)0x58000010) /* ADC conversion data */
 574 #define ADCUPDN (*(volatile unsigned long *)0x58000014) /* Stylus up or down interrupt status */
 575
 576 /* SPI */
 577
 578 #define SPCON0 (*(volatile unsigned long *)0x59000000) /* SPI control */
 579 #define SPSTA0 (*(volatile unsigned long *)0x59000004) /* SPI status */
 580 #define SPPIN0 (*(volatile unsigned long *)0x59000008) /* SPI pin control */
 581 #define SPPRE0 (*(volatile unsigned long *)0x5900000C) /* SPI baud rate prescaler */
 582 #define SPTDAT0 (*(volatile unsigned long *)0x59000010) /* SPI Tx data */
 583 #define SPRDAT0 (*(volatile unsigned long *)0x59000014) /* SPI Rx data */
 584 #define SPCON1 (*(volatile unsigned long *)0x59000020) /* SPI control */
 585 #define SPSTA1 (*(volatile unsigned long *)0x59000024) /* SPI status */
 586 #define SPPIN1 (*(volatile unsigned long *)0x59000028) /* SPI pin control */
 587 #define SPPRE1 (*(volatile unsigned long *)0x5900002C) /* SPI baud rate prescaler */
 588 #define SPTDAT1 (*(volatile unsigned long *)0x59000030) /* SPI Tx data */
 589 #define SPRDAT1 (*(volatile unsigned long *)0x59000034) /* SPI Rx data */
 590
 591 /* SD Interface */
 592
 593 #define SDICON (*(volatile unsigned long *)0x5A000000) /* SDI control */
 594 #define SDIPRE (*(volatile unsigned long *)0x5A000004) /* SDI baud rate prescaler */
 595 #define SDICARG (*(volatile unsigned long *)0x5A000008) /* SDI command argument */
 596 #define SDICCON (*(volatile unsigned long *)0x5A00000C) /* SDI command control */
 597 #define SDICSTA (*(volatile unsigned long *)0x5A000010) /* SDI command status */
 598 #define SDIRSP0 (*(volatile unsigned long *)0x5A000014) /* SDI response */
 599 #define SDIRSP1 (*(volatile unsigned long *)0x5A000018) /* SDI response */
 600 #define SDIRSP2 (*(volatile unsigned long *)0x5A00001C) /* SDI response */
 601 #define SDIRSP3 (*(volatile unsigned long *)0x5A000020) /* SDI response */
 602 #define SDIDTIMER (*(volatile unsigned long *)0x5A000024) /* SDI data / busy timer */
 603 #define SDIBSIZE (*(volatile unsigned long *)0x5A000028) /* SDI block size */
 604 #define SDIDCON (*(volatile unsigned long *)0x5A00002C) /* SDI data control */
 605 #define SDIDCNT (*(volatile unsigned long *)0x5A000030) /* SDI data remain counter */
 606 #define SDIDSTA (*(volatile unsigned long *)0x5A000034) /* SDI data status */
 607 #define SDIFSTA (*(volatile unsigned long *)0x5A000038) /* SDI FIFO status */
 608 #define SDIIMSK (*(volatile unsigned long *)0x5A00003C) /* SDI interrupt mask */
 609
 610 /* SDI data - LE = Little Endian, BE = Big Endian */
 611 #define SDIDAT_LLE (*(volatile unsigned long *)0x5A000040)  /* 32 bit */
 612 #define SDIDAT_HLE (*(volatile unsigned short *)0x5A000044) /* 16 */
 613 #define SDIDAT_BLE (*(volatile unsigned char *)0x5A000048)  /* 8 */
 614 #define SDIDAT_LBE (*(volatile unsigned long *)0x5A00004C)  /* 32 */
 615 #define SDIDAT_HBE (*(volatile unsigned short *)0x5A000041) /* 16 */
 616 #define SDIDAT_BBE (*(volatile unsigned char *)0x5A000043)  /* 8 */
 617
 618 /* SDI register bit definitions. S3C2440 is a superset of S3C2410 */
 619
 620 #define S3C2440_SDICON_SDRESET        (1<<8)
 621 #define S3C2440_SDICON_MMCCLOCK       (1<<5)
 622 #define S3C2410_SDICON_BYTEORDER      (1<<4)
 623 #define S3C2410_SDICON_SDIOIRQ        (1<<3)
 624 #define S3C2410_SDICON_RWAITEN        (1<<2)
 625 #define S3C2410_SDICON_FIFORESET      (1<<1)
 626 #define S3C2410_SDICON_CLOCKTYPE      (1<<0)
 627
 628 #define S3C2410_SDICMDCON_ABORT       (1<<12)
 629 #define S3C2410_SDICMDCON_WITHDATA    (1<<11)
 630 #define S3C2410_SDICMDCON_LONGRSP     (1<<10)
 631 #define S3C2410_SDICMDCON_WAITRSP     (1<<9)
 632 #define S3C2410_SDICMDCON_CMDSTART    (1<<8)
 633 #define S3C2410_SDICMDCON_SENDERHOST  (1<<6)
 634 #define S3C2410_SDICMDCON_INDEX       (0x3f)
 635
 636 #define S3C2410_SDICMDSTAT_CRCFAIL    (1<<12)
 637 #define S3C2410_SDICMDSTAT_CMDSENT    (1<<11)
 638 #define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10)
 639 #define S3C2410_SDICMDSTAT_RSPFIN     (1<<9)
 640 #define S3C2410_SDICMDSTAT_XFERING    (1<<8)
 641 #define S3C2410_SDICMDSTAT_INDEX      (0xff)
 642
 643 #define S3C2440_SDIDCON_DS_BYTE       (0<<22)
 644 #define S3C2440_SDIDCON_DS_HALFWORD   (1<<22)
 645 #define S3C2440_SDIDCON_DS_WORD       (2<<22)
 646 #define S3C2410_SDIDCON_IRQPERIOD     (1<<21)
 647 #define S3C2410_SDIDCON_TXAFTERRESP   (1<<20)
 648 #define S3C2410_SDIDCON_RXAFTERCMD    (1<<19)
 649 #define S3C2410_SDIDCON_BUSYAFTERCMD  (1<<18)
 650 #define S3C2410_SDIDCON_BLOCKMODE     (1<<17)
 651 #define S3C2410_SDIDCON_WIDEBUS       (1<<16)
 652 #define S3C2410_SDIDCON_DMAEN         (1<<15)
 653 #define S3C2410_SDIDCON_STOP          (0<<14)
 654 #define S3C2440_SDIDCON_DATSTART      (1<<14)
 655 #define S3C2410_SDIDCON_DATMODE       (3<<12)
 656 #define S3C2410_SDIDCON_BLKNUM        (0xfff)
 657
 658 /* constants for S3C2410_SDIDCON_DATMODE */
 659 #define S3C2410_SDIDCON_XFER_READY    (0<<12)
 660 #define S3C2410_SDIDCON_XFER_CHKSTART (1<<12)
 661 #define S3C2410_SDIDCON_XFER_RXSTART  (2<<12)
 662 #define S3C2410_SDIDCON_XFER_TXSTART  (3<<12)
 663
 664 #define S3C2410_SDIDCNT_BLKNUM_MASK   (0xFFF)
 665 #define S3C2410_SDIDCNT_BLKNUM_SHIFT  (12)
 666
 667 #define S3C2410_SDIDSTA_RDYWAITREQ    (1<<10)
 668 #define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9)
 669 #define S3C2410_SDIDSTA_FIFOFAIL      (1<<8)    /* reserved on 2440 */
 670 #define S3C2410_SDIDSTA_CRCFAIL       (1<<7)
 671 #define S3C2410_SDIDSTA_RXCRCFAIL     (1<<6)
 672 #define S3C2410_SDIDSTA_DATATIMEOUT   (1<<5)
 673 #define S3C2410_SDIDSTA_XFERFINISH    (1<<4)
 674 #define S3C2410_SDIDSTA_BUSYFINISH    (1<<3)
 675 #define S3C2410_SDIDSTA_SBITERR       (1<<2)    /* reserved on 2410a/2440 */
 676 #define S3C2410_SDIDSTA_TXDATAON      (1<<1)
 677 #define S3C2410_SDIDSTA_RXDATAON      (1<<0)
 678
 679 #define S3C2410_SDIDSTA_CLEAR_BITS    ( S3C2410_SDIDSTA_BUSYFINISH  | \
 680         S3C2410_SDIDSTA_XFERFINISH    | S3C2410_SDIDSTA_DATATIMEOUT | \
 681         S3C2410_SDIDSTA_RXCRCFAIL     | S3C2410_SDIDSTA_CRCFAIL     | \
 682         S3C2410_SDIDSTA_SDIOIRQDETECT | S3C2410_SDIDSTA_RDYWAITREQ )
 683
 684 #define S3C2440_SDIFSTA_FIFORESET      (1<<16)
 685 #define S3C2440_SDIFSTA_FIFOFAIL       (3<<14)  /* 3 is correct (2 bits) */
 686 #define S3C2410_SDIFSTA_TFDET          (1<<13)
 687 #define S3C2410_SDIFSTA_RFDET          (1<<12)
 688 #define S3C2410_SDIFSTA_TFHALF         (1<<11)
 689 #define S3C2410_SDIFSTA_TFEMPTY        (1<<10)
 690 #define S3C2410_SDIFSTA_RFLAST         (1<<9)
 691 #define S3C2410_SDIFSTA_RFFULL         (1<<8)
 692 #define S3C2410_SDIFSTA_RFHALF         (1<<7)
 693 #define S3C2410_SDIFSTA_COUNTMASK      (0x7f)
 694
 695 #define S3C2410_SDIIMSK_RESPONSECRC    (1<<17)
 696 #define S3C2410_SDIIMSK_CMDSENT        (1<<16)
 697 #define S3C2410_SDIIMSK_CMDTIMEOUT     (1<<15)
 698 #define S3C2410_SDIIMSK_RESPONSEND     (1<<14)
 699 #define S3C2410_SDIIMSK_READWAIT       (1<<13)
 700 #define S3C2410_SDIIMSK_SDIOIRQ        (1<<12)
 701 #define S3C2410_SDIIMSK_FIFOFAIL       (1<<11)
 702 #define S3C2410_SDIIMSK_CRCSTATUS      (1<<10)
 703 #define S3C2410_SDIIMSK_DATACRC        (1<<9)
 704 #define S3C2410_SDIIMSK_DATATIMEOUT    (1<<8)
 705 #define S3C2410_SDIIMSK_DATAFINISH     (1<<7)
 706 #define S3C2410_SDIIMSK_BUSYFINISH     (1<<6)
 707 #define S3C2410_SDIIMSK_SBITERR        (1<<5)   /* reserved 2440/2410a */
 708 #define S3C2410_SDIIMSK_TXFIFOHALF     (1<<4)
 709 #define S3C2410_SDIIMSK_TXFIFOEMPTY    (1<<3)
 710 #define S3C2410_SDIIMSK_RXFIFOLAST     (1<<2)
 711 #define S3C2410_SDIIMSK_RXFIFOFULL     (1<<1)
 712 #define S3C2410_SDIIMSK_RXFIFOHALF     (1<<0)
 713
 714 /* AC97 Audio-CODEC Interface */
 715
 716 #define AC_GLBCTRL (*(volatile unsigned long *)0x5B000000) /* AC97 global control register */
 717 #define AC_GLBSTAT (*(volatile unsigned long *)0x5B000004) /* AC97 global status register */
 718 #define AC_CODEC_CMD (*(volatile unsigned long *)0x5B000008) /* AC97 codec command register */
 719 #define AC_CODEC_STAT (*(volatile unsigned long *)0x5B00000C) /* AC97 codec status register */
 720 #define AC_PCMADDR (*(volatile unsigned long *)0x5B000010) /* AC97 PCM out/in channel FIFO address register */
 721 #define AC_MICADDR (*(volatile unsigned long *)0x5B000014) /* AC97 mic in channel FIFO address register */
 722 #define AC_PCMDATA (*(volatile unsigned long *)0x5B000018) /* AC97 PCM out/in channel FIFO data register */
 723 #define AC_MICDATA (*(volatile unsigned long *)0x5B00001C) /* AC97 MIC in channel FIFO data register */
 724
 725 /* Memory banks */
 726
 727 #define BANK0 0x00000000
 728 #define BANK1 0x08000000
 729 #define BANK2 0x10000000
 730 #define BANK3 0x18000000
 731 #define BANK4 0x20000000
 732 #define BANK5 0x28000000
 733 #define DRAM0 0x30000000
 734 #define DRAM1 0x31000000
 735 #define BOOTRAM 0x40000000
 736
 737 /* Timer frequency */
 738
 739 /* timer is based on PCLK and minimum division is 2 */
 740 #define TIMER_FREQ (49156800/2)
 741 #define TIMER234_PRESCALE 21
 742
 743 /* I/O Port macros */
 744
 745 #define GPIO_INPUT          0
 746 #define GPIO_OUTPUT         1
 747 #define GPIO_FUNCTION       2
 748 #define GPIO_ALT_FUNCTION   3
 749
 750 #define GPIO_PULLUP_DISABLE 1
 751 #define GPIO_PULLUP_ENABLE  0
 752
 753 #define S3C2440_GPIO_CONFIG(port,pin,function)  port = ( (port & ~(3<<(pin*2)) ) | (function<<(pin*2)) )
 754 #define S3C2440_GPIO_PULLUP(port,pin,state)     port = ( (port & ~(1<<pin    ) ) | (state<<pin       ) )
 755
 756
 757 #endif /* __S3C2440_H__ */