firmware/export/as3525.h

   1 /*
   2 * (C) Copyright 2006
   3 * Copyright (C) 2006 Austriamicrosystems, by thomas.luo
   4 *
   5 * This program is free software; you can redistribute it and/or
   6 * modify it under the terms of the GNU General Public License as
   7 * published by the Free Software Foundation; either version 2 of
   8 * the License, or (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18 * MA 02111-1307 USA
  19 */
  20 #ifndef __AS3525_H__
  21 #define __AS3525_H__
  22
  23 #define CACHEALIGN_BITS (5)
  24
  25 #define UART_CHANNELS 1
  26
  27
  28 #if MEMORYSIZE <= 2
  29 /* we put the codec buffer in IRAM */
  30 #define AMS_LOWMEM
  31 #endif
  32
  33 /* Virtual addresses */
  34 #define DRAM_ORIG 0x30000000
  35 #define IRAM_ORIG (DRAM_ORIG + DRAM_SIZE) /* IRAM is mapped just next to DRAM */
  36
  37 #define DRAM_SIZE (MEMORYSIZE * 0x100000)
  38 #define IRAM_SIZE 0x50000
  39
  40
  41 /* AS352X only supports 512 Byte HW ECC */
  42 #define ECCSIZE 512
  43 #define ECCBYTES 3
  44
  45 /* AS352X MMU Page Table Entries */
  46 #define TTB_SIZE                  0x4000
  47 #define TTB_BASE_ADDR             (DRAM_ORIG + DRAM_SIZE - TTB_SIZE)
  48
  49
  50 /* AS352X device base addresses */
  51
  52
  53 /*
  54 ------------------------------------------------------------------------
  55 *  AS352X Registers
  56 *
  57 ------------------------------------------------------------------------
  58 *
  59 */
  60
  61
  62 /* AHB */
  63 #define USB_BASE             0xC6000000
  64 #define VIC_BASE             0xC6010000
  65 #define DMAC_BASE            0xC6020000
  66 #define MPMC_BASE            0xC6030000
  67 #define MEMSTICK_BASE        0xC6040000
  68 #define CF_IDE_BASE          0xC6050000
  69
  70 /* APB */
  71 #define NAND_FLASH_BASE      0xC8000000
  72 #define BIST_MANAGER_BASE    0xC8010000
  73 #define SD_MCI_BASE          0xC8020000
  74 #define TIMER_BASE           0xC8040000
  75 #define WDT_BASE             0xC8050000
  76 #define I2C_MS_BASE          0xC8060000
  77 #define I2C_AUDIO_BASE       0xC8070000
  78 #define SSP_BASE             0xC8080000
  79 #define I2SIN_BASE           0xC8090000
  80 #define I2SOUT_BASE          0xC80A0000
  81 #define GPIOA_BASE           0xC80B0000
  82 #define GPIOB_BASE           0xC80C0000
  83 #define GPIOC_BASE           0xC80D0000
  84 #define GPIOD_BASE           0xC80E0000
  85 #define CGU_BASE             0xC80F0000
  86 #define CCU_BASE             0xC8100000
  87 #define UART0_BASE           0xC8110000
  88 #define DBOP_BASE            0xC8120000
  89
  90
  91
  92
  93
  94
  95
  96
  97 /*
  98 ------------------------------------------------------------------------
  99 *  AS352X control registers
 100 *
 101 ------------------------------------------------------------------------
 102 */
 103
 104 #define CCU_SRC           (*(volatile unsigned long *)(CCU_BASE + 0x00))
 105 #define CCU_SRL           (*(volatile unsigned long *)(CCU_BASE + 0x04))
 106 #define CCU_MEMMAP        (*(volatile unsigned long *)(CCU_BASE + 0x08))
 107 #define CCU_IO            (*(volatile unsigned long *)(CCU_BASE + 0x0C))
 108 #define CCU_SCON          (*(volatile unsigned long *)(CCU_BASE + 0x10))
 109 #define CCU_VERS          (*(volatile unsigned long *)(CCU_BASE + 0x14))
 110 #define CCU_SPARE1        (*(volatile unsigned long *)(CCU_BASE + 0x18))
 111 #define CCU_SPARE2        (*(volatile unsigned long *)(CCU_BASE + 0x1C))
 112
 113 /* DBOP */
 114 #define DBOP_TIMPOL_01    (*(volatile unsigned long *)(DBOP_BASE + 0x00))
 115 #define DBOP_TIMPOL_23    (*(volatile unsigned long *)(DBOP_BASE + 0x04))
 116 #define DBOP_CTRL         (*(volatile unsigned long *)(DBOP_BASE + 0x08))
 117 #define DBOP_STAT         (*(volatile unsigned long *)(DBOP_BASE + 0x0C))
 118 /* default is 16bit, but we switch to 32bit for some targets for better speed */
 119 #define DBOP_DOUT8        (*(volatile unsigned  char*)(DBOP_BASE + 0x10))
 120 #define DBOP_DOUT         (*(volatile unsigned short*)(DBOP_BASE + 0x10))
 121 #define DBOP_DOUT16       (*(volatile unsigned short*)(DBOP_BASE + 0x10))
 122 #define DBOP_DOUT32       (*(volatile unsigned long *)(DBOP_BASE + 0x10))
 123 #define DBOP_DIN          (*(volatile unsigned short*)(DBOP_BASE + 0x14))
 124
 125
 126 /**
 127 * Reset Control Lines in CCU_SRC register
 128 **/
 129 #define CCU_SRC_DBOP_EN        ( 1 << 24 )
 130 #define CCU_SRC_SPDIF_EN       ( 1 << 22 )
 131 #define CCU_SRC_TIMER_EN       ( 1 << 21 )
 132 #define CCU_SRC_SSP_EN         ( 1 << 20 )
 133 #define CCU_SRC_WDO_EN         ( 1 << 19 )
 134 #define CCU_SRC_IDE_EN         ( 1 << 18 )
 135 #define CCU_SRC_IDE_AHB_EN     ( 1 << 17 )
 136 #define CCU_SRC_UART0          ( 1 << 16 )
 137 #define CCU_SRC_NAF_EN         ( 1 << 15 )
 138 #define CCU_SRC_SDMCI_EN       ( 1 << 14 )
 139 #define CCU_SRC_GPIO_EN        ( 1 << 13 )
 140 #define CCU_SRC_I2C_AUDIO_EN   ( 1 << 12 )
 141 #define CCU_SRC_I2C_EN         ( 1 << 11 )
 142 #define CCU_SRC_MST_EN         ( 1 << 10 )
 143 #define CCU_SRC_I2SIN          ( 1 <<  9 )
 144 #define CCU_SRC_I2SOUT         ( 1 <<  8 )
 145 #define CCU_SRC_USB_AHB_EN     ( 1 <<  7 )
 146 #define CCU_SRC_USB_PHY_EN     ( 1 <<  6 )
 147 #define CCU_SRC_DMAC_EN        ( 1 <<  5 )
 148 #define CCU_SRC_VIC_EN         ( 1 <<  4 )
 149
 150 /**
 151 * Magic number for CCU_SRL for reset.
 152 **/
 153 #define CCU_SRL_MAGIC_NUMBER      0x1A720212
 154
 155 /**
 156 * Chip select lines for NAF. Use these constants to select/deselct the
 157 CE lines
 158 * for NAND flashes in Register CCU_IO.
 159 **/
 160 #define CCU_IO_NAF_CE_LINE_0      ( 0 << 7 )
 161 #define CCU_IO_NAF_CE_LINE_1      ( 1 << 7 )
 162 #define CCU_IO_NAF_CE_LINE_2      ( 2 << 7 )
 163 #define CCU_IO_NAF_CE_LINE_3      ( 3 << 7 )
 164
 165 /* CCU IO Select/Deselect IDE */
 166 #define CCU_IO_IDE                ( 1 << 5 )
 167
 168 /* CCU IO Select/desect I2C */
 169 #define CCU_IO_I2C_MASTER_SLAVE   ( 1 << 1 )
 170
 171 /* CCU IO Select/desect UART */
 172 #define CCU_IO_UART0               ( 1 << 0 )
 173
 174
 175 #define CCU_RESET_ALL_BUT_MEMORY \
 176  ( CCU_SRC_DBOP_EN        \
 177  | CCU_SRC_SPDIF_EN       \
 178  | CCU_SRC_TIMER_EN       \
 179  | CCU_SRC_SSP_EN         \
 180  | CCU_SRC_WDO_EN         \
 181  | CCU_SRC_IDE_EN         \
 182  | CCU_SRC_IDE_AHB_EN     \
 183  | CCU_SRC_UART0          \
 184  | CCU_SRC_NAF_EN         \
 185  | CCU_SRC_SDMCI_EN       \
 186  | CCU_SRC_GPIO_EN        \
 187  | CCU_SRC_I2C_AUDIO_EN   \
 188  | CCU_SRC_I2C_EN         \
 189  | CCU_SRC_MST_EN         \
 190  | CCU_SRC_I2SIN          \
 191  | CCU_SRC_I2SOUT         \
 192  | CCU_SRC_USB_AHB_EN     \
 193  | CCU_SRC_USB_PHY_EN     \
 194  | CCU_SRC_DMAC_EN        \
 195  | CCU_SRC_VIC_EN         \
 196  )
 197
 198 #define CCU_IO_UART               ( 1 << 0 )
 199 /*
 200 ------------------------------------------------------------------------
 201 *  AS352X clock control registers
 202 *
 203 ------------------------------------------------------------------------
 204 */
 205
 206 #define CGU_PLLA         (*(volatile unsigned long *)(CGU_BASE + 0x00))
 207 #define CGU_PLLB         (*(volatile unsigned long *)(CGU_BASE + 0x04))
 208 #define CGU_PLLASUP      (*(volatile unsigned long *)(CGU_BASE + 0x08))
 209 #define CGU_PLLBSUP      (*(volatile unsigned long *)(CGU_BASE + 0x0C))
 210 #define CGU_PROC         (*(volatile unsigned long *)(CGU_BASE + 0x10))
 211 #define CGU_PERI         (*(volatile unsigned long *)(CGU_BASE + 0x14))
 212 #define CGU_AUDIO        (*(volatile unsigned long *)(CGU_BASE + 0x18))
 213 #define CGU_USB          (*(volatile unsigned long *)(CGU_BASE + 0x1C))
 214 #define CGU_INTCTRL      (*(volatile unsigned long *)(CGU_BASE + 0x20))
 215 #define CGU_IRQ          (*(volatile unsigned long *)(CGU_BASE + 0x24))
 216 #define CGU_COUNTA       (*(volatile unsigned long *)(CGU_BASE + 0x28))
 217 #define CGU_COUNTB       (*(volatile unsigned long *)(CGU_BASE + 0x2C))
 218 #define CGU_IDE          (*(volatile unsigned long *)(CGU_BASE + 0x30))
 219 #define CGU_MEMSTICK     (*(volatile unsigned long *)(CGU_BASE + 0x34))
 220 #define CGU_DBOP         (*(volatile unsigned long *)(CGU_BASE + 0x38))
 221
 222 #define CGU_VIC_CLOCK_ENABLE                 ( 1 << 23 ) /* vic */
 223 /* --- are disabled after reset --- */
 224 #define CGU_EXTMEM_CLOCK_ENABLE              ( 1 << 27 ) /* external memory */
 225 #define CGU_EXTMEMIF_CLOCK_ENABLE            ( 1 << 26 ) /* ext mem AHB IF */
 226 #define CGU_DMA_CLOCK_ENABLE                 ( 1 << 22 ) /* dma */
 227 #define CGU_USB_CLOCK_ENABLE                 ( 1 << 21 ) /* usb */
 228 #define CGU_I2SOUT_APB_CLOCK_ENABLE          ( 1 << 20 ) /* i2sout */
 229 #define CGU_I2SIN_APB_CLOCK_ENABLE           ( 1 << 19 ) /* i2sin */
 230 #define CGU_I2C_MASTER_SLAVE_CLOCK_ENABLE    ( 1 << 18 ) /* i2c master/slave */
 231 #define CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE    ( 1 << 17 ) /* i2c audio master */
 232 #define CGU_GPIO_CLOCK_ENABLE                ( 1 << 16 ) /* gpio */
 233 #define CGU_MCI_CLOCK_ENABLE                 ( 1 << 15 ) /* mmc + sd */
 234 #define CGU_NAF_CLOCK_ENABLE                 ( 1 << 14 ) /* naf */
 235 #define CGU_UART_APB_CLOCK_ENABLE            ( 1 << 13 ) /* uart */
 236 #define CGU_WDOCNT_CLOCK_ENABLE              ( 1 << 12 ) /* watchdog counter */
 237 #define CGU_WDOIF_CLOCK_ENABLE               ( 1 << 11 ) /* watchdog timer module */
 238 #define CGU_SSP_CLOCK_ENABLE                 ( 1 << 10 ) /* ssp */
 239 #define CGU_TIMER1_CLOCK_ENABLE              ( 1 <<  9 ) /* timer 1 */
 240 #define CGU_TIMER2_CLOCK_ENABLE              ( 1 <<  8 ) /* timer 2 */
 241 #define CGU_TIMERIF_CLOCK_ENABLE             ( 1 <<  7 ) /* timer interface */
 242
 243 /* CGU_PLL[AB]SUP bits */
 244 #define CGU_PLL_POWERDOWN                    ( 1 <<  3 )
 245
 246 /* CGU_INTCTRL bits */
 247 #define CGU_PLLA_LOCK                        ( 1 <<  0 )
 248 #define CGU_PLLB_LOCK                        ( 1 <<  1 )
 249
 250 /**  ------------------------------------------------------------------
 251 * Number of cycles to wait before cgu is safely locked.
 252 **/
 253 #define CGU_LOCK_CNT 0xFF
 254
 255 /* FIFO depth is 16 for tx and rx fifo */
 256 #define UART_FIFO_DEPTH           16
 257
 258 /* ------------------- UART Line Control Register bit fields -------------------- */
 259
 260 #define UART_LNCTL_DLSEN          (1 << 7) /* Device latch select bit */
 261
 262
 263 /* --------------   UART Interrupt Control Register bit fields --------------- */
 264
 265 #define UART_INTR_RXDRDY           0x1 /* Data ready interrupt */
 266 #define UART_INTR_TXEMT            0x2 /* Transmit data empty interrupt */
 267 #define UART_INTR_RXLINESTATUS     0x4 /* Receive line status interrupt */
 268
 269 /* ------------------- UART Line Status Register bit fields --------------------  */
 270
 271 #define UART_ERRORBITS             0x1E
 272 #define UART_RX_DATA_READY        (1 << 0)
 273 #define UART_TX_HOLD_EMPTY    (1 << 5)
 274
 275 /* -------------------        FIFO CNTL Register contants -------------------*/
 276
 277 #define UART_FIFO_EN              (1 << 0)  /* Enable the UART FIFO */
 278 #define UART_TX_FIFO_RST          (1 << 1)  /* Enable the UART FIFO */
 279 #define UART_RX_FIFO_RST          (1 << 2)
 280 #define UART_RXFIFO_TRIGLVL_1     (0 << 4) /* RX FIFO TRIGGER_LEVEL 1 */
 281 #define UART_RXFIFO_TRIGLVL_4      0x08    /* RX FIFO TRIGGER_LEVEL 4 */
 282 #define UART_RXFIFO_TRIGLVL_8      0x10    /* RX FIFO TRIGGER_LEVEL 8 */
 283 #define UART_RXFIFO_TRIGLVL_14     0x18    /* RX FIFO TRIGGER_LEVEL 14 */
 284
 285
 286 /* -------------------        FIFO status Register contants ------------------*/
 287 #define UART_TX_FIFO_FULL         (1 << 0)
 288 #define UART_RX_FIFO_FULL         (1 << 1)
 289 #define UART_TX_FIFO_EMPTY        (1 << 2)
 290 #define UART_RX_FIFO_EMPTY        (1 << 3)
 291
 292
 293 /* ----------------------- defines ---------------------------------------- */
 294
 295
 296
 297 #define UART_DATA_REG       (*(volatile unsigned long*)(UART0_BASE + 0x00)) /* Data register */
 298 #define UART_DLO_REG        (*(volatile unsigned long*)(UART0_BASE + 0x00)) /* Clock divider(lower byte) register */
 299 #define UART_DHI_REG        (*(volatile unsigned long*)(UART0_BASE + 0x04)) /* Clock divider(higher byte) register */
 300 #define UART_INTEN_REG      (*(volatile unsigned long*)(UART0_BASE + 0x04)) /* Interrupt enable register */
 301 #define UART_INTSTATUS_REG  (*(volatile unsigned long*)(UART0_BASE + 0x08)) /* Interrupt status register */
 302 #define UART_FCTL_REG       (*(volatile unsigned long*)(UART0_BASE + 0x0C)) /* Fifo control  register */
 303 #define UART_FSTATUS_REG    (*(volatile unsigned long*)(UART0_BASE + 0x0C)) /* Fifo status register */
 304 #define UART_LNCTL_REG      (*(volatile unsigned long*)(UART0_BASE + 0x10)) /* Line control register */
 305 #define UART_LNSTATUS_REG   (*(volatile unsigned long*)(UART0_BASE + 0x14)) /* Line status register */
 306
 307
 308 #define SD_MCI_POWER        (*(volatile unsigned long*)(SD_MCI_BASE + 0x0))
 309
 310
 311 #define TIMER1_LOAD      (*(volatile unsigned long*)(TIMER_BASE + 0x00)) /* 32-bit width */
 312 #define TIMER1_VALUE     (*(volatile unsigned long*)(TIMER_BASE + 0x04)) /* 32 bit width */
 313 #define TIMER1_CONTROL   (*(volatile unsigned long*)(TIMER_BASE + 0x08)) /*  8 bit width */
 314 #define TIMER1_INTCLR    (*(volatile unsigned long*)(TIMER_BASE + 0x0C)) /* clears ir by write access */
 315 #define TIMER1_RIS       (*(volatile unsigned long*)(TIMER_BASE + 0x10)) /*  1 bit width */
 316 #define TIMER1_MIS       (*(volatile unsigned long*)(TIMER_BASE + 0x14)) /*  1 bit width */
 317 #define TIMER1_BGLOAD    (*(volatile unsigned long*)(TIMER_BASE + 0x18)) /* 32-bit width */
 318
 319 #define TIMER2_LOAD      (*(volatile unsigned long*)(TIMER_BASE + 0x20)) /* 32-bit width */
 320 #define TIMER2_VALUE     (*(volatile unsigned long*)(TIMER_BASE + 0x24)) /* 32 bit width */
 321 #define TIMER2_CONTROL   (*(volatile unsigned long*)(TIMER_BASE + 0x28)) /*  8 bit width */
 322 #define TIMER2_INTCLR    (*(volatile unsigned long*)(TIMER_BASE + 0x2C)) /* clears ir by write access */
 323 #define TIMER2_RIS       (*(volatile unsigned long*)(TIMER_BASE + 0x30)) /*  1 bit width */
 324 #define TIMER2_MIS       (*(volatile unsigned long*)(TIMER_BASE + 0x34)) /*  1 bit width */
 325 #define TIMER2_BGLOAD    (*(volatile unsigned long*)(TIMER_BASE + 0x38)) /* 32-bit width */
 326
 327 /**
 328 * Counter/Timer control register bits
 329 **/
 330 #define TIMER_ENABLE       0x80
 331 #define TIMER_PERIODIC     0x40
 332 #define TIMER_INT_ENABLE   0x20
 333 #define TIMER_32_BIT   0x02
 334 #define TIMER_ONE_SHOT   0x01
 335 #define TIMER_PRESCALE_1   0x00
 336 #define TIMER_PRESCALE_16   0x04
 337 #define TIMER_PRESCALE_256 0x08
 338
 339
 340 /* Watchdog registers */
 341 #define WDT_LOAD        (*(volatile unsigned long*)(WDT_BASE))
 342 #define WDT_CONTROL     (*(volatile unsigned long*)(WDT_BASE+8))
 343
 344
 345 /* GPIO registers */
 346 #define GPIOA_DIR       (*(volatile unsigned char*)(GPIOA_BASE+0x400))
 347 #define GPIOA_IS        (*(volatile unsigned char*)(GPIOA_BASE+0x404))
 348 #define GPIOA_IBE       (*(volatile unsigned char*)(GPIOA_BASE+0x408))
 349 #define GPIOA_IEV       (*(volatile unsigned char*)(GPIOA_BASE+0x40C))
 350 #define GPIOA_IE        (*(volatile unsigned char*)(GPIOA_BASE+0x410))
 351 #define GPIOA_RIS       (*(volatile unsigned char*)(GPIOA_BASE+0x414))
 352 #define GPIOA_MIS       (*(volatile unsigned char*)(GPIOA_BASE+0x418))
 353 #define GPIOA_IC        (*(volatile unsigned char*)(GPIOA_BASE+0x41C))
 354 #define GPIOA_AFSEL     (*(volatile unsigned char*)(GPIOA_BASE+0x420))
 355 #define GPIOA_PIN(a)    (*(volatile unsigned char*)(GPIOA_BASE+(1<<((a)+2))))
 356 #define GPIOA_PIN_MASK(m) (*(volatile unsigned char *)(GPIOA_BASE+(((m)&0xff)<<2)))
 357 #define GPIOA_DATA      (*(volatile unsigned char*)(GPIOA_BASE+(0xff<<2)))
 358
 359
 360 #define GPIOB_DIR       (*(volatile unsigned char*)(GPIOB_BASE+0x400))
 361 #define GPIOB_IS        (*(volatile unsigned char*)(GPIOB_BASE+0x404))
 362 #define GPIOB_IBE       (*(volatile unsigned char*)(GPIOB_BASE+0x408))
 363 #define GPIOB_IEV       (*(volatile unsigned char*)(GPIOB_BASE+0x40C))
 364 #define GPIOB_IE        (*(volatile unsigned char*)(GPIOB_BASE+0x410))
 365 #define GPIOB_RIS       (*(volatile unsigned char*)(GPIOB_BASE+0x414))
 366 #define GPIOB_MIS       (*(volatile unsigned char*)(GPIOB_BASE+0x418))
 367 #define GPIOB_IC        (*(volatile unsigned char*)(GPIOB_BASE+0x41C))
 368 #define GPIOB_AFSEL     (*(volatile unsigned char*)(GPIOB_BASE+0x420))
 369 #define GPIOB_PIN(a)    (*(volatile unsigned char*)(GPIOB_BASE+(1<<((a)+2))))
 370 #define GPIOB_PIN_MASK(m) (*(volatile unsigned char *)(GPIOB_BASE+(((m)&0xff)<<2)))
 371 #define GPIOB_DATA      (*(volatile unsigned char*)(GPIOB_BASE+(0xff<<2)))
 372
 373 #define GPIOC_DIR       (*(volatile unsigned char*)(GPIOC_BASE+0x400))
 374 #define GPIOC_IS        (*(volatile unsigned char*)(GPIOC_BASE+0x404))
 375 #define GPIOC_IBE       (*(volatile unsigned char*)(GPIOC_BASE+0x408))
 376 #define GPIOC_IEV       (*(volatile unsigned char*)(GPIOC_BASE+0x40C))
 377 #define GPIOC_IE        (*(volatile unsigned char*)(GPIOC_BASE+0x410))
 378 #define GPIOC_RIS       (*(volatile unsigned char*)(GPIOC_BASE+0x414))
 379 #define GPIOC_MIS       (*(volatile unsigned char*)(GPIOC_BASE+0x418))
 380 #define GPIOC_IC        (*(volatile unsigned char*)(GPIOC_BASE+0x41C))
 381 #define GPIOC_AFSEL     (*(volatile unsigned char*)(GPIOC_BASE+0x420))
 382 #define GPIOC_PIN(a)    (*(volatile unsigned char*)(GPIOC_BASE+(1<<((a)+2))))
 383 #define GPIOC_PIN_MASK(m) (*(volatile unsigned char *)(GPIOC_BASE+(((m)&0xff)<<2)))
 384 #define GPIOC_DATA      (*(volatile unsigned char*)(GPIOC_BASE+(0xff<<2)))
 385
 386 #define GPIOD_DIR       (*(volatile unsigned char*)(GPIOD_BASE+0x400))
 387 #define GPIOD_IS        (*(volatile unsigned char*)(GPIOD_BASE+0x404))
 388 #define GPIOD_IBE       (*(volatile unsigned char*)(GPIOD_BASE+0x408))
 389 #define GPIOD_IEV       (*(volatile unsigned char*)(GPIOD_BASE+0x40C))
 390 #define GPIOD_IE        (*(volatile unsigned char*)(GPIOD_BASE+0x410))
 391 #define GPIOD_RIS       (*(volatile unsigned char*)(GPIOD_BASE+0x414))
 392 #define GPIOD_MIS       (*(volatile unsigned char*)(GPIOD_BASE+0x418))
 393 #define GPIOD_IC        (*(volatile unsigned char*)(GPIOD_BASE+0x41C))
 394 #define GPIOD_AFSEL     (*(volatile unsigned char*)(GPIOD_BASE+0x420))
 395 #define GPIOD_PIN(a)    (*(volatile unsigned char*)(GPIOD_BASE+(1<<((a)+2))))
 396 #define GPIOD_PIN_MASK(m) (*(volatile unsigned char *)(GPIOD_BASE+(((m)&0xff)<<2)))
 397 #define GPIOD_DATA      (*(volatile unsigned char*)(GPIOD_BASE+(0xff<<2)))
 398
 399 /* ARM PL172 Memory Controller registers */
 400
 401 #define MPMC_CONTROL              (*(volatile unsigned long*)(MPMC_BASE+0x000))
 402 #define MPMC_STATUS               (*(volatile unsigned long*)(MPMC_BASE+0x004))
 403 #define MPMC_CONFIG               (*(volatile unsigned long*)(MPMC_BASE+0x008))
 404
 405 #define MPMC_DYNAMIC_CONTROL      (*(volatile unsigned long*)(MPMC_BASE+0x020))
 406 #define MPMC_DYNAMIC_REFRESH      (*(volatile unsigned long*)(MPMC_BASE+0x024))
 407 #define MPMC_DYNAMIC_READ_CONFIG  (*(volatile unsigned long*)(MPMC_BASE+0x028))
 408 #define MPMC_DYNAMIC_tRP          (*(volatile unsigned long*)(MPMC_BASE+0x030))
 409 #define MPMC_DYNAMIC_tRAS         (*(volatile unsigned long*)(MPMC_BASE+0x034))
 410 #define MPMC_DYNAMIC_tSREX        (*(volatile unsigned long*)(MPMC_BASE+0x038))
 411 #define MPMC_DYNAMIC_tAPR         (*(volatile unsigned long*)(MPMC_BASE+0x03C))
 412 #define MPMC_DYNAMIC_tDAL         (*(volatile unsigned long*)(MPMC_BASE+0x040))
 413 #define MPMC_DYNAMIC_tWR          (*(volatile unsigned long*)(MPMC_BASE+0x044))
 414 #define MPMC_DYNAMIC_tRC          (*(volatile unsigned long*)(MPMC_BASE+0x048))
 415 #define MPMC_DYNAMIC_tRFC         (*(volatile unsigned long*)(MPMC_BASE+0x04C))
 416 #define MPMC_DYNAMIC_tXSR         (*(volatile unsigned long*)(MPMC_BASE+0x050))
 417 #define MPMC_DYNAMIC_tRRD         (*(volatile unsigned long*)(MPMC_BASE+0x054))
 418 #define MPMC_DYNAMIC_tMRD         (*(volatile unsigned long*)(MPMC_BASE+0x058))
 419
 420 #define MPMC_STATIC_EXTENDED_WAIT (*(volatile unsigned long*)(MPMC_BASE+0x080))
 421
 422 #define MPMC_DYNAMIC_CONFIG_0     (*(volatile unsigned long*)(MPMC_BASE+0x100))
 423 #define MPMC_DYNAMIC_CONFIG_1     (*(volatile unsigned long*)(MPMC_BASE+0x120))
 424 #define MPMC_DYNAMIC_CONFIG_2     (*(volatile unsigned long*)(MPMC_BASE+0x140))
 425 #define MPMC_DYNAMIC_CONFIG_3     (*(volatile unsigned long*)(MPMC_BASE+0x160))
 426
 427 #define MPMC_DYNAMIC_RASCAS_0     (*(volatile unsigned long*)(MPMC_BASE+0x104))
 428 #define MPMC_DYNAMIC_RASCAS_1     (*(volatile unsigned long*)(MPMC_BASE+0x124))
 429 #define MPMC_DYNAMIC_RASCAS_2     (*(volatile unsigned long*)(MPMC_BASE+0x144))
 430 #define MPMC_DYNAMIC_RASCAS_3     (*(volatile unsigned long*)(MPMC_BASE+0x164))
 431
 432 #define MPMC_PERIPH_ID2           (*(volatile unsigned long*)(MPMC_BASE+0xFE8))
 433
 434 /* VIC controller (PL190) registers */
 435
 436 #define VIC_IRQ_STATUS      (*(volatile unsigned long*)(VIC_BASE+0x00))
 437 #define VIC_FIQ_STATUS      (*(volatile unsigned long*)(VIC_BASE+0x04))
 438 #define VIC_RAW_INTR        (*(volatile unsigned long*)(VIC_BASE+0x08))
 439 #define VIC_INT_SELECT      (*(volatile unsigned long*)(VIC_BASE+0x0C))
 440 #define VIC_INT_ENABLE      (*(volatile unsigned long*)(VIC_BASE+0x10))
 441 #define VIC_INT_EN_CLEAR    (*(volatile unsigned long*)(VIC_BASE+0x14))
 442 #define VIC_SOFT_INT        (*(volatile unsigned long*)(VIC_BASE+0x18))
 443 #define VIC_SOFT_INT_CLEAR  (*(volatile unsigned long*)(VIC_BASE+0x1C))
 444 #define VIC_PROTECTION      (*(volatile unsigned long*)(VIC_BASE+0x20))
 445 #define VIC_VECT_ADDR       ((void (* volatile *) (void)) (VIC_BASE+0x30))
 446 #define VIC_DEF_VECT_ADDR   ((void (* volatile *) (void)) (VIC_BASE+0x34))
 447 #define VIC_VECT_ADDRS      ((void (* volatile *) (void)) (VIC_BASE+0x100))
 448 #define VIC_VECT_CNTLS      ((volatile unsigned long*)(VIC_BASE+0x200))
 449
 450 /* Interrupt sources (for vectors setup) */
 451 #define INT_SRC_WATCHDOG      0
 452 #define INT_SRC_TIMER1        1
 453 #define INT_SRC_TIMER2        2
 454 #define INT_SRC_USB           3
 455 #define INT_SRC_DMAC          4
 456 #define INT_SRC_NAND          5
 457 #define INT_SRC_IDE           6
 458 #define INT_SRC_MCI0          7
 459 #define INT_SRC_MCI1          8
 460 #define INT_SRC_AUDIO         9
 461 #define INT_SRC_SSP           10
 462 #define INT_SRC_I2C_MS        11
 463 #define INT_SRC_I2C_AUDIO     12
 464 #define INT_SRC_I2SIN         13
 465 #define INT_SRC_I2SOUT        14
 466 #define INT_SRC_UART          15
 467 #define INT_SRC_GPIOD         16
 468 /* 17 reserved */
 469 #define INT_SRC_CGU           18
 470 #define INT_SRC_MEMORY_STICK  19
 471 #define INT_SRC_DBOP          20
 472 /* 21-28 reserved */
 473 #define INT_SRC_GPIOA         29
 474 #define INT_SRC_GPIOB         30
 475 #define INT_SRC_GPIOC         31
 476
 477 /* Interrupt sources bitmask */
 478 #define INTERRUPT_WATCHDOG      (1<<0)
 479 #define INTERRUPT_TIMER1        (1<<1)
 480 #define INTERRUPT_TIMER2        (1<<2)
 481 #define INTERRUPT_USB           (1<<3)
 482 #define INTERRUPT_DMAC          (1<<4)
 483 #define INTERRUPT_NAND          (1<<5)
 484 #define INTERRUPT_IDE           (1<<6)
 485 #define INTERRUPT_MCI0          (1<<7)
 486 #define INTERRUPT_MCI1          (1<<8)
 487 #define INTERRUPT_AUDIO         (1<<9)
 488 #define INTERRUPT_SSP           (1<<10)
 489 #define INTERRUPT_I2C_MS        (1<<11)
 490 #define INTERRUPT_I2C_AUDIO     (1<<12)
 491 #define INTERRUPT_I2SIN         (1<<13)
 492 #define INTERRUPT_I2SOUT        (1<<14)
 493 #define INTERRUPT_UART          (1<<15)
 494 #define INTERRUPT_GPIOD         (1<<16)
 495 /* 17 reserved */
 496 #define INTERRUPT_CGU           (1<<18)
 497 #define INTERRUPT_MEMORY_STICK  (1<<19)
 498 #define INTERRUPT_DBOP          (1<<20)
 499 /* 21-28 reserved */
 500 #define INTERRUPT_GPIOA         (1<<29)
 501 #define INTERRUPT_GPIOB         (1<<30)
 502 #define INTERRUPT_GPIOC         (1<<31)
 503
 504 /* I2SOUT registers */
 505
 506 #define I2SOUT_CONTROL      (*(volatile unsigned char*)(I2SOUT_BASE+0x00))
 507 #define I2SOUT_MASK         (*(volatile unsigned char*)(I2SOUT_BASE+0x04))
 508 #define I2SOUT_RAW_STATUS   (*(volatile unsigned char*)(I2SOUT_BASE+0x08))
 509 #define I2SOUT_STATUS       (*(volatile unsigned char*)(I2SOUT_BASE+0x0C))
 510 #define I2SOUT_CLEAR        (*(volatile unsigned char*)(I2SOUT_BASE+0x10))
 511 #define I2SOUT_DATA         (volatile unsigned long*)(I2SOUT_BASE+0x14)
 512
 513
 514 /* SSP registers (PrimeCell PL022) */
 515
 516 #define SSP_CR0             (*(volatile unsigned short*)(SSP_BASE+0x00))
 517 #define SSP_CR1             (*(volatile unsigned char*)(SSP_BASE+0x04))
 518 #define SSP_DATA            (*(volatile unsigned short*)(SSP_BASE+0x08))
 519 #define SSP_SR              (*(volatile unsigned char*)(SSP_BASE+0x0C))
 520 #define SSP_CPSR            (*(volatile unsigned char*)(SSP_BASE+0x10))
 521 #define SSP_IMSC            (*(volatile unsigned char*)(SSP_BASE+0x14))
 522 #define SSP_IRS             (*(volatile unsigned char*)(SSP_BASE+0x18))
 523 #define SSP_MIS             (*(volatile unsigned char*)(SSP_BASE+0x1C))
 524 #define SSP_ICR             (*(volatile unsigned char*)(SSP_BASE+0x20))
 525 #define SSP_DMACR           (*(volatile unsigned char*)(SSP_BASE+0x24))
 526
 527 /* PCM addresses for obtaining buffers will be what DMA is using (physical) */
 528 #define HAVE_PCM_DMA_ADDRESS
 529 #define HAVE_PCM_REC_DMA_ADDRESS
 530
 531 /* Timer frequency */
 532 #define TIMER_FREQ (24000000 / 16)
 533
 534 /* USB */
 535 #define USB_NUM_ENDPOINTS 4
 536 #define USB_DEVBSS_ATTR
 537
 538 /* I2SIN registers */
 539
 540 #define I2SIN_CONTROL      (*(volatile unsigned long*)(I2SIN_BASE+0x00))
 541 #define I2SIN_MASK         (*(volatile unsigned char*)(I2SIN_BASE+0x04))
 542 #define I2SIN_RAW_STATUS   (*(volatile unsigned char*)(I2SIN_BASE+0x08))
 543 #define I2SIN_STATUS       (*(volatile unsigned char*)(I2SIN_BASE+0x0C))
 544 #define I2SIN_CLEAR        (*(volatile unsigned char*)(I2SIN_BASE+0x10))
 545 #define I2SIN_DATA         (volatile unsigned long*)(I2SIN_BASE+0x14)
 546 #define I2SIN_SPDIF_STATUS (*(volatile unsigned long*)(I2SIN_BASE+0x18))
 547
 548 /* I2SIN_MASK */
 549
 550 #define I2SIN_MASK_PUER   ( 1<<6 ) /* push error */
 551 #define I2SIN_MASK_POE    ( 1<<5 ) /* empty */
 552 #define I2SIN_MASK_POAE   ( 1<<4 ) /* almost empty */
 553 #define I2SIN_MASK_POHF   ( 1<<3 ) /* half full */
 554 #define I2SIN_MASK_POAF   ( 1<<2 ) /* almost full */
 555 #define I2SIN_MASK_POF    ( 1<<1 ) /* full */
 556 #define I2SIN_MASK_POER   ( 1<<0 ) /* pop error */
 557
 558 #endif /*__AS3525_H__*/