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Fix playlist catalog directory manual spelling
[maemo-rb.git] / firmware / drivers / audio / uda1380.c
blobfd32b398ca1fa09e1582af3baa889103e500d750
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2005 by Andy Young
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21 #include <string.h>
22
23 #include "config.h"
24 #include "logf.h"
25 #include "system.h"
26 #include "audio.h"
27 #include "debug.h"
28 #include "udacodec.h"
29
30 #include "audiohw.h"
31
32 /* The UDA1380 requires a clock signal at a multiple of the sample rate
33 (256Fs, 384Fs, 512Fs or 768Fs, where Fs = sample rate).
34 Some targets are able to supply this clock directly to the SYSCLK input.
35 The H100 and H300 coldfire targets are limited in the selection of
36 frequencies for this clock signal so they use a PLL inside the UDA1380
37 (called the WSPLL) to regenerate it from the LRCK signal off the IIS bus.
38 */
39 #if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300_SERIES)
40 #define USE_WSPLL
41 #endif
42
43 const struct sound_settings_info audiohw_settings[] = {
44 [SOUND_VOLUME] = {"dB", 0, 1, -84, 0, -25},
45 [SOUND_BASS] = {"dB", 0, 2, 0, 24, 0},
46 [SOUND_TREBLE] = {"dB", 0, 2, 0, 6, 0},
47 [SOUND_BALANCE] = {"%", 0, 1,-100, 100, 0},
48 [SOUND_CHANNELS] = {"", 0, 1, 0, 5, 0},
49 [SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100},
50 #ifdef HAVE_RECORDING
51 [SOUND_LEFT_GAIN] = {"dB", 1, 1,-128, 96, 0},
52 [SOUND_RIGHT_GAIN] = {"dB", 1, 1,-128, 96, 0},
53 [SOUND_MIC_GAIN] = {"dB", 1, 1,-128, 108, 16},
54 #endif
55 };
56
57 /* convert tenth of dB volume (-840..0) to master volume register value */
58 int tenthdb2master(int db)
59 {
60 if (db < -720) /* 1.5 dB steps */
61 return (2940 - db) / 15;
62 else if (db < -660) /* 0.75 dB steps */
63 return (1110 - db) * 2 / 15;
64 else if (db < -520) /* 0.5 dB steps */
65 return (520 - db) / 5;
66 else /* 0.25 dB steps */
67 return -db * 2 / 5;
68 }
69
70 /* convert tenth of dB volume (-780..0) to mixer volume register value */
71 int tenthdb2mixer(int db)
72 {
73 if (db < -660) /* 1.5 dB steps */
74 return (2640 - db) / 15;
75 else if (db < -600) /* 0.75 dB steps */
76 return (990 - db) * 2 / 15;
77 else if (db < -460) /* 0.5 dB steps */
78 return (460 - db) / 5;
79 else /* 0.25 dB steps */
80 return -db * 2 / 5;
81 }
82
83 /* ------------------------------------------------- */
84 /* Local functions and variables */
85 /* ------------------------------------------------- */
86
87 static int uda1380_write_reg(unsigned char reg, unsigned short value);
88 static unsigned short uda1380_regs[0x30];
89 static short recgain_mic;
90 static short recgain_line;
91
92 /* Definition of a playback configuration to start with */
93
94 #define NUM_DEFAULT_REGS 13
95 static const unsigned short uda1380_defaults[2*NUM_DEFAULT_REGS] =
96 {
97 REG_0, EN_DAC | EN_INT | EN_DEC |
98 #ifdef USE_WSPLL
99 ADC_CLK | DAC_CLK | WSPLL_25_50 |
100 #endif
101 SYSCLK_256FS,
102 REG_I2S, I2S_IFMT_IIS,
103 REG_PWR, PON_PLL | PON_BIAS,
104 /* PON_HP & PON_DAC is enabled later */
105 REG_AMIX, AMIX_RIGHT(0x3f) | AMIX_LEFT(0x3f),
106 /* 00=max, 3f=mute */
107 REG_MASTER_VOL, MASTER_VOL_LEFT(0x20) | MASTER_VOL_RIGHT(0x20),
108 /* 00=max, ff=mute */
109 REG_MIX_VOL, MIX_VOL_CH_1(0) | MIX_VOL_CH_2(0xff),
110 /* 00=max, ff=mute */
111 REG_EQ, EQ_MODE_MAX,
112 /* Bass and treble = 0 dB */
113 REG_MUTE, MUTE_MASTER | MUTE_CH2,
114 /* Mute everything to start with */
115 REG_MIX_CTL, MIX_CTL_MIX,
116 /* Enable mixer */
117 REG_DEC_VOL, 0,
118 REG_PGA, MUTE_ADC,
119 REG_ADC, SKIP_DCFIL,
120 REG_AGC, 0
121 };
122
123
124 /* Returns 0 if register was written or -1 if write failed */
125 static int uda1380_write_reg(unsigned char reg, unsigned short value)
126 {
127 if (udacodec_write(reg, value) < 0)
128 {
129 DEBUGF("uda1380 error reg=0x%x", reg);
130 return -1;
131 }
132
133 uda1380_regs[reg] = value;
134
135 return 0;
136 }
137
138 /**
139 * Sets left and right master volume (0(max) to 252(muted))
140 */
141 void audiohw_set_master_vol(int vol_l, int vol_r)
142 {
143 uda1380_write_reg(REG_MASTER_VOL,
144 MASTER_VOL_LEFT(vol_l) | MASTER_VOL_RIGHT(vol_r));
145 }
146
147 /**
148 * Sets mixer volume for both channels (0(max) to 228(muted))
149 */
150 void audiohw_set_mixer_vol(int channel1, int channel2)
151 {
152 uda1380_write_reg(REG_MIX_VOL,
153 MIX_VOL_CH_1(channel1) | MIX_VOL_CH_2(channel2));
154 }
155
156 /**
157 * Sets the bass value (0-12)
158 */
159 void audiohw_set_bass(int value)
160 {
161 uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~BASS_MASK)
162 | BASSL(value) | BASSR(value));
163 }
164
165 /**
166 * Sets the treble value (0-3)
167 */
168 void audiohw_set_treble(int value)
169 {
170 uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~TREBLE_MASK)
171 | TREBLEL(value) | TREBLER(value));
172 }
173
174 static void audiohw_mute(bool mute)
175 {
176 unsigned int value = uda1380_regs[REG_MUTE];
177
178 if (mute)
179 value = value | MUTE_MASTER;
180 else
181 value = value & ~MUTE_MASTER;
182
183 uda1380_write_reg(REG_MUTE, value);
184 }
185
186 /* Returns 0 if successful or -1 if some register failed */
187 static int audiohw_set_regs(void)
188 {
189 int i;
190 memset(uda1380_regs, 0, sizeof(uda1380_regs));
191
192 /* Initialize all registers */
193 for (i=0; i<NUM_DEFAULT_REGS; i++)
194 {
195 unsigned char reg = uda1380_defaults[i*2+0];
196 unsigned short value = uda1380_defaults[i*2+1];
197
198 if (uda1380_write_reg(reg, value) == -1)
199 return -1;
200 }
201
202 return 0;
203 }
204
205 /**
206 * Sets frequency settings for DAC and ADC relative to MCLK
207 *
208 * Selection for frequency ranges:
209 * Fs: range: with:
210 * 11025: 0 = 6.25 to 12.5 MCLK/2 SCLK, LRCK: Audio Clk / 16
211 * 22050: 1 = 12.5 to 25 MCLK/2 SCLK, LRCK: Audio Clk / 8
212 * 44100: 2 = 25 to 50 MCLK SCLK, LRCK: Audio Clk / 4 (default)
213 * 88200: 3 = 50 to 100 MCLK SCLK, LRCK: Audio Clk / 2
214 */
215 void audiohw_set_frequency(int fsel)
216 {
217 static const unsigned short values_reg[HW_NUM_FREQ][2] =
218 {
219 [HW_FREQ_11] = /* Fs: */
220 {
221 0,
222 WSPLL_625_125 | SYSCLK_512FS
223 },
224 [HW_FREQ_22] =
225 {
226 0,
227 WSPLL_125_25 | SYSCLK_256FS
228 },
229 [HW_FREQ_44] =
230 {
231 MIX_CTL_SEL_NS,
232 WSPLL_25_50 | SYSCLK_256FS
233 },
234 [HW_FREQ_88] =
235 {
236 MIX_CTL_SEL_NS,
237 WSPLL_50_100 | SYSCLK_256FS
238 },
239 };
240
241 const unsigned short *ent;
242
243 if ((unsigned)fsel >= HW_NUM_FREQ)
244 fsel = HW_FREQ_DEFAULT;
245
246 ent = values_reg[fsel];
247
248 /* Set WSPLL input frequency range or SYSCLK divider */
249 uda1380_regs[REG_0] &= ~0xf;
250 uda1380_write_reg(REG_0, uda1380_regs[REG_0] | ent[1]);
251
252 /* Choose 3rd order or 5th order noise shaper */
253 uda1380_regs[REG_MIX_CTL] &= ~MIX_CTL_SEL_NS;
254 uda1380_write_reg(REG_MIX_CTL, uda1380_regs[REG_MIX_CTL] | ent[0]);
255 }
256
257 /* Initialize UDA1380 codec with default register values (uda1380_defaults) */
258 void audiohw_init(void)
259 {
260 recgain_mic = 0;
261 recgain_line = 0;
262
263 udacodec_reset();
264
265 if (audiohw_set_regs() == -1)
266 {
267 /* this shoud never (!) happen. */
268 logf("uda1380: audiohw_init failed");
269 }
270 }
271
272 void audiohw_postinit(void)
273 {
274 /* Sleep a while so the power can stabilize (especially a long
275 delay is needed for the line out connector). */
276 sleep(HZ);
277
278 /* Power on FSDAC and HP amp. */
279 uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_DAC | PON_HP);
280
281 /* UDA1380: Unmute the master channel
282 (DAC should be at zero point now). */
283 audiohw_mute(false);
284 }
285
286 void audiohw_set_prescaler(int val)
287 {
288 audiohw_set_mixer_vol(tenthdb2mixer(-val), tenthdb2mixer(-val));
289 }
290
291 /* Nice shutdown of UDA1380 codec */
292 void audiohw_close(void)
293 {
294 /* First enable mute and sleep a while */
295 uda1380_write_reg(REG_MUTE, MUTE_MASTER);
296 sleep(HZ/8);
297
298 /* Then power off the rest of the chip */
299 uda1380_write_reg(REG_PWR, 0);
300 uda1380_write_reg(REG_0, 0); /* Disable codec */
301 }
302
303 /**
304 * Calling this function enables the UDA1380 to send
305 * sound samples over the I2S bus, which is connected
306 * to the processor's IIS1 interface.
307 *
308 * source_mic: true=record from microphone, false=record from line-in (or radio)
309 */
310 void audiohw_enable_recording(bool source_mic)
311 {
312 #ifdef USE_WSPLL
313 uda1380_regs[REG_0] &= ~(ADC_CLK | DAC_CLK);
314 #endif
315 uda1380_write_reg(REG_0, uda1380_regs[REG_0] | EN_ADC);
316
317 if (source_mic)
318 {
319 /* VGA_GAIN: 0=0 dB, F=30dB */
320 /* Output of left ADC is fed into right bitstream */
321 uda1380_regs[REG_PWR] &= ~(PON_PGAR | PON_ADCR);
322 uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_LNA | PON_ADCL);
323 uda1380_regs[REG_ADC] &= ~SKIP_DCFIL;
324 uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC] & VGA_GAIN_MASK)
325 | SEL_LNA | SEL_MIC | EN_DCFIL);
326 uda1380_write_reg(REG_PGA, 0);
327 }
328 else
329 {
330 /* PGA_GAIN: 0=0 dB, F=24dB */
331 uda1380_regs[REG_PWR] &= ~PON_LNA;
332 uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_PGAL | PON_ADCL
333 | PON_PGAR | PON_ADCR);
334 uda1380_write_reg(REG_ADC, EN_DCFIL);
335 uda1380_write_reg(REG_PGA, uda1380_regs[REG_PGA] & PGA_GAIN_MASK);
336 }
337
338 sleep(HZ/8);
339
340 uda1380_write_reg(REG_I2S, uda1380_regs[REG_I2S] | I2S_MODE_MASTER);
341 uda1380_write_reg(REG_MIX_CTL, MIX_MODE(1));
342 }
343
344 /**
345 * Stop sending samples on the I2S bus
346 */
347 void audiohw_disable_recording(void)
348 {
349 uda1380_write_reg(REG_PGA, MUTE_ADC);
350 sleep(HZ/8);
351
352 uda1380_write_reg(REG_I2S, I2S_IFMT_IIS);
353
354 uda1380_regs[REG_PWR] &= ~(PON_LNA | PON_ADCL | PON_ADCR |
355 PON_PGAL | PON_PGAR);
356 uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR]);
357
358 uda1380_regs[REG_0] &= ~EN_ADC;
359 #ifdef USE_WSPLL
360 uda1380_write_reg(REG_0, uda1380_regs[REG_0] | ADC_CLK | DAC_CLK);
361 #endif
362
363 uda1380_write_reg(REG_ADC, SKIP_DCFIL);
364 }
365
366 /**
367 * Set recording gain and volume
368 *
369 * type: params: ranges:
370 * AUDIO_GAIN_MIC: left -128 .. 108 -> -64 .. 54 dB gain
371 * AUDIO_GAIN_LINEIN left & right -128 .. 96 -> -64 .. 48 dB gain
372 *
373 * Note: - For all types the value 0 gives 0 dB gain.
374 * - order of setting both values determines if the small glitch will
375 be a peak or a dip. The small glitch is caused by the time between
376 setting the two gains
377 */
378 void audiohw_set_recvol(int left, int right, int type)
379 {
380 int left_ag, right_ag;
381
382 switch (type)
383 {
384 case AUDIO_GAIN_MIC:
385 left_ag = MIN(MAX(0, left / 4), 15);
386 left -= left_ag * 4;
387
388 if(left < recgain_mic)
389 {
390 uda1380_write_reg(REG_DEC_VOL, DEC_VOLL(left)
391 | DEC_VOLR(left));
392 uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC]
393 & ~VGA_GAIN_MASK)
394 | VGA_GAIN(left_ag));
395 }
396 else
397 {
398 uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC]
399 & ~VGA_GAIN_MASK)
400 | VGA_GAIN(left_ag));
401 uda1380_write_reg(REG_DEC_VOL, DEC_VOLL(left)
402 | DEC_VOLR(left));
403 }
404 recgain_mic = left;
405 logf("Mic: %dA/%dD", left_ag, left);
406 break;
407
408 case AUDIO_GAIN_LINEIN:
409 left_ag = MIN(MAX(0, left / 6), 8);
410 left -= left_ag * 6;
411 right_ag = MIN(MAX(0, right / 6), 8);
412 right -= right_ag * 6;
413
414 if(left < recgain_line)
415 {
416 /* for this order we can combine both registers,
417 making the glitch even smaller */
418 unsigned short value_dec;
419 unsigned short value_pga;
420 value_dec = DEC_VOLL(left) | DEC_VOLR(right);
421 value_pga = (uda1380_regs[REG_PGA] & ~PGA_GAIN_MASK)
422 | PGA_GAINL(left_ag) | PGA_GAINR(right_ag);
423
424 if (udacodec_write2(REG_DEC_VOL, value_dec, value_pga) < 0)
425 {
426 DEBUGF("uda1380 error reg=combi rec gain");
427 }
428 else
429 {
430 uda1380_regs[REG_DEC_VOL] = value_dec;
431 uda1380_regs[REG_PGA] = value_pga;
432 }
433 }
434 else
435 {
436 uda1380_write_reg(REG_PGA, (uda1380_regs[REG_PGA]
437 & ~PGA_GAIN_MASK)
438 | PGA_GAINL(left_ag)
439 | PGA_GAINR(right_ag));
440 uda1380_write_reg(REG_DEC_VOL, DEC_VOLL(left)
441 | DEC_VOLR(right));
442 }
443
444 recgain_line = left;
445 logf("Line L: %dA/%dD", left_ag, left);
446 logf("Line R: %dA/%dD", right_ag, right);
447 break;
448 }
449 }
450
451
452 /**
453 * Enable or disable recording monitor (so one can listen to the recording)
454 *
455 */
456 void audiohw_set_monitor(bool enable)
457 {
458 if (enable) /* enable channel 2 */
459 uda1380_write_reg(REG_MUTE, uda1380_regs[REG_MUTE] & ~MUTE_CH2);
460 else /* mute channel 2 */
461 uda1380_write_reg(REG_MUTE, uda1380_regs[REG_MUTE] | MUTE_CH2);
462 }
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