firmware/export/rk27xx_codec.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Driver for internal Rockchip rk27xx audio codec
  11  * (shCODlp-100.01-HD IP core from Dolphin)
  12  *
  13  * Copyright (c) 2011 Marcin Bukat
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * as published by the Free Software Foundation; either version 2
  18  * of the License, or (at your option) any later version.
  19  *
  20  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  21  * KIND, either express or implied.
  22  *
  23  ****************************************************************************/
  24 #ifndef _RK27XX_CODEC_H_
  25 #define _RK27XX_CODEC_H_
  26
  27 #define VOLUME_MIN -335
  28 #define VOLUME_MAX   45
  29 #define AUDIOHW_CAPS (BASS_CAP | TREBLE_CAP)
  30
  31 extern int tenthdb2master(int db);
  32 extern void audiohw_set_master_vol(int vol_l, int vol_r);
  33
  34 #define CODEC_I2C_ADDR 0x4e
  35
  36 /* registers */
  37 #define AICR  0x00     /* Audio Interface Control    */
  38 #define DAC_SERIAL     (1<<3)
  39 #define ADC_SERIAL     (1<<2)
  40 #define DAC_I2S        (1<<1)
  41 #define ADC_I2S        (1<<0)
  42
  43 #define CR1   0x02     /* Control Register 1         */
  44 #define SB_MICBIAS     (1<<7)
  45 #define CR1_MONO       (1<<6)
  46 #define DAC_MUTE       (1<<5)
  47 #define HP_DIS         (1<<4)
  48 #define DACSEL         (1<<3)
  49 #define BYPASS1        (1<<2)
  50 #define BYPASS2        (1<<1)
  51 #define SIDETONE       (1<<0)
  52
  53 #define CR2   0x04     /* Control Register 2         */
  54 #define DAC_DEEMP      (1<<7)
  55 #define ADC_HPF        (1<<2)
  56 #define INSEL_MIX      (3<<0)
  57 #define INSEL_MIC      (2<<0)
  58 #define INSEL_LINE2    (1<<0)
  59 #define INSEL_LINE1    (0<<0)
  60
  61 #define CCR1  0x06     /* Control Clock Register 1   */
  62 #define CRYSTAL_16M    (1<<0)
  63 #define CRYSTAL_12M    (0<<0)
  64
  65 #define CCR2  0x08     /* Control Clock Register 2   */
  66 #define FREQ8000       0x0a
  67 #define FREQ9600       0x09
  68 #define FREQ11025      0x08
  69 #define FREQ12000      0x07
  70 #define FREQ16000      0x06
  71 #define FREQ22050      0x05
  72 #define FREQ24000      0x04
  73 #define FREQ32000      0x03
  74 #define FREQ44100      0x02
  75 #define FREQ48000      0x01
  76 #define FREQ96000      0x00
  77
  78 #define PMR1  0x0a     /* Power Mode Register 1      */
  79 #define SB_DAC         (1<<7)
  80 #define SB_OUT         (1<<6)
  81 #define SB_MIX         (1<<5)
  82 #define SB_ADC         (1<<4)
  83 #define SB_IN1         (1<<3)
  84 #define SB_IN2         (1<<2)
  85 #define SB_MIC         (1<<1)
  86 #define SB_IND         (1<<0)
  87
  88 #define PMR2  0x0c     /* Power Mode Register 1      */
  89 #define LRGI           (1<<7)
  90 #define RLGI           (1<<6)
  91 #define LRGOD          (1<<5)
  92 #define RLGOD          (1<<4)
  93 #define GIM            (1<<3)
  94 #define SB_MC          (1<<2)
  95 #define SB             (1<<1)
  96 #define SB_SLEEP       (1<<0)
  97
  98 #define CRR   0x0e     /* Control Ramp Register      */
  99 #define RATIO_8        (3<<5)
 100 #define RATIO_4        (2<<5)
 101 #define RATIO_2        (1<<5)
 102 #define RATIO_1        (0<<5)
 103 #define KFAST_32       (5<<2)
 104 #define KFAST_16       (4<<2)
 105 #define KFAST_8        (3<<2)
 106 #define KFAST_4        (2<<2)
 107 #define KFAST_2        (1<<2)
 108 #define KFAST_1        (0<<2)
 109 #define THRESHOLD_128  (3<<0)
 110 #define THRESHOLD_64   (2<<0)
 111 #define THRESHOLD_32   (1<<0)
 112 #define THRESHOLD_0    (0<<0)
 113
 114 #define ICR   0x10     /* Interrupt Control Register */
 115 #define IRQ_LOW_PULSE  (3<<6)
 116 #define IRQ_HIGH_PULSE (2<<6)
 117 #define IRQ_LOW        (1<<6)
 118 #define IRQ_HIGH       (0<<6)
 119 #define JACK_MASK      (1<<5)
 120 #define CCMC_MASK      (1<<4)
 121 #define RUD_MASK       (1<<3)
 122 #define RDD_MASK       (1<<2)
 123 #define GUD_MASK       (1<<1)
 124 #define GDD_MASK       (1<<0)
 125
 126 #define IFR   0x12     /* Interrupt Flag Register    */
 127 #define JACK           (1<<6)
 128 #define JACK_EVENT     (1<<5)
 129 #define CCMC           (1<<4)
 130 #define RAMP_UP_DONE   (1<<3)
 131 #define RAMP_DOWN_DONE (1<<2)
 132 #define GAIN_UP_DONE   (1<<1)
 133 #define GAIN_DOWN_DONE (1<<0)
 134
 135 #define CGR1  0x14     /* Control Gain Register 1 (DAC mixing)      */
 136
 137 #define CGR2  0x16     /* Control Gain Register 2 (LINE1 mixing)    */
 138 #define LRGOB1         (1<<7)
 139 #define RLGOB1         (1<<6)
 140
 141 #define CGR3  0x18     /* Control Gain Register 3 (LINE1 mixing)    */
 142
 143 #define CGR4  0x1a     /* Control Gain Register 4 (LINE2 mixing)    */
 144 #define LRGOB2         (1<<7)
 145 #define RLGOB2         (1<<6)
 146
 147 #define CGR5  0x1c     /* Control Gain Register 5 (LINE2 mixing)    */
 148
 149 #define CGR6  0x1e     /* Control Gain Register 6 (MIC mixing)      */
 150 #define LRGOS          (1<<7)
 151 #define RLGOS          (1<<6)
 152
 153 #define CGR7  0x20     /* Control Gain Register 7 (MIC mixing)      */
 154
 155 #define CGR8  0x22     /* Control Gain Register 8 (OUT STAGE gain)  */
 156 #define LRGO           (1<<7)
 157 #define RLGO           (1<<6)
 158
 159 #define CGR9  0x24     /* Control Gain Register 9 (OUT STAGE gain)  */
 160
 161 #define CGR10 0x26     /* Control Gain Register 10 (ADC input gain) */
 162
 163 #define TR1   0x28     /* undocumented */
 164 #define NOSC           (1<<1)
 165
 166 #define TR2   0x2a     /* undocumented */
 167
 168 #endif /* _RK27XX_CODEC_H_ */