firmware/export/usb-s3c6400x.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2009 Michael Sparmann
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef USB_S3C6400X_H
  22 #define USB_S3C6400X_H
  23
  24
  25 /* All multi-bit fields in the driver use the following convention.
  26  * If the register name is NAME, then there is one define NAME_bitp
  27  * which holds the bit position and one define NAME_bits which holds
  28  * a mask of the bits within the register (after shift).
  29  * These macros allow easy access and construction of such fields */
  30 /* Usage:
  31  * - extract(reg_name,field_name)
  32  *   extract a field of the register
  33  * - bitm(reg_name,field_name)
  34  *   build a bitmask for the field
  35  */
  36 #define extract(reg_name, field_name) \
  37     ((reg_name >> reg_name##_##field_name##_bitp) & reg_name##_##field_name##_bits)
  38
  39 #define bitm(reg_name, field_name) \
  40     (reg_name##_##field_name##_bits << reg_name##_##field_name##_bitp)
  41
  42
  43 /*** OTG PHY CONTROL REGISTERS ***/
  44 #define OPHYPWR     (*((uint32_t volatile*)(PHYBASE + 0x000)))
  45 #define OPHYCLK     (*((uint32_t volatile*)(PHYBASE + 0x004)))
  46 #define ORSTCON     (*((uint32_t volatile*)(PHYBASE + 0x008)))
  47 #define OPHYUNK3    (*((uint32_t volatile*)(PHYBASE + 0x018)))
  48 #define OPHYUNK1    (*((uint32_t volatile*)(PHYBASE + 0x01c)))
  49 #define OPHYUNK2    (*((uint32_t volatile*)(PHYBASE + 0x044)))
  50
  51 /*** OTG LINK CORE REGISTERS ***/
  52 /* Core Global Registers */
  53
  54 /** OTG Control and Status Register */
  55 #define GOTGCTL     (*((uint32_t volatile*)(OTGBASE + 0x000)))
  56
  57 /** OTG Interrupt Register */
  58 #define GOTGINT     (*((uint32_t volatile*)(OTGBASE + 0x004)))
  59
  60 /** Core AHB Configuration Register */
  61 #define GAHBCFG     (*((uint32_t volatile*)(OTGBASE + 0x008)))
  62 #define GAHBCFG_glblintrmsk             (1 << 0) /** Global interrupt mask */
  63 #define GAHBCFG_hburstlen_bitp          1
  64 #define GAHBCFG_hburstlen_bits          0xf
  65 #define GAHBCFG_INT_DMA_BURST_SINGLE    0
  66 #define GAHBCFG_INT_DMA_BURST_INCR      1 /** note: the linux patch has several other value, this is one picked for internal dma */
  67 #define GAHBCFG_INT_DMA_BURST_INCR4     3
  68 #define GAHBCFG_INT_DMA_BURST_INCR8     5
  69 #define GAHBCFG_INT_DMA_BURST_INCR16    7
  70 #define GAHBCFG_dma_enable              (1 << 5) /** Enable DMA */
  71
  72 /** Core USB Configuration Register */
  73 #define GUSBCFG     (*((uint32_t volatile*)(OTGBASE + 0x00C)))
  74 #define GUSBCFG_toutcal_bitp            0
  75 #define GUSBCFG_toutcal_bits            0x7
  76 #define GUSBCFG_phy_if                  (1 << 3) /** select utmi bus width ? */
  77 #define GUSBCFG_ulpi_utmi_sel           (1 << 4) /** select ulpi:1 or utmi:0 */
  78 #define GUSBCFG_fsintf                  (1 << 5)
  79 #define GUSBCFG_physel                  (1 << 6)
  80 #define GUSBCFG_ddrsel                  (1 << 7)
  81 #define GUSBCFG_srpcap                  (1 << 8)
  82 #define GUSBCFG_hnpcapp                 (1 << 9)
  83 #define GUSBCFG_usbtrdtim_bitp          10
  84 #define GUSBCFG_usbtrdtim_bits          0xf
  85 #define GUSBCFG_nptxfrwnden             (1 << 14)
  86 #define GUSBCFG_phylpwrclksel           (1 << 15)
  87 #define GUSBCFG_otgutmifssel            (1 << 16)
  88 #define GUSBCFG_ulpi_fsls               (1 << 17)
  89 #define GUSBCFG_ulpi_auto_res           (1 << 18)
  90 #define GUSBCFG_ulpi_clk_sus_m          (1 << 19)
  91 #define GUSBCFG_ulpi_ext_vbus_drv       (1 << 20)
  92 #define GUSBCFG_ulpi_int_vbus_indicator (1 << 21)
  93 #define GUSBCFG_term_sel_dl_pulse       (1 << 22)
  94 #define GUSBCFG_force_host_mode         (1 << 29)
  95 #define GUSBCFG_force_device_mode       (1 << 30)
  96 #define GUSBCFG_corrupt_tx_packet       (1 << 31)
  97
  98
  99 /** Core Reset Register */
 100 #define GRSTCTL     (*((uint32_t volatile*)(OTGBASE + 0x010)))
 101 #define GRSTCTL_csftrst         (1 << 0) /** Core soft reset */
 102 #define GRSTCTL_hsftrst         (1 << 1) /** Hclk soft reset */
 103 #define GRSTCTL_intknqflsh      (1 << 3) /** In Token Sequence Learning Queue Flush */
 104 #define GRSTCTL_rxfflsh_flush   (1 << 4) /** RxFIFO Flush */
 105 #define GRSTCTL_txfflsh_flush   (1 << 5) /** TxFIFO Flush */
 106 #define GRSTCTL_txfnum_bitp     6 /** TxFIFO Number */
 107 #define GRSTCTL_txfnum_bits     0x1f
 108 #define GRSTCTL_ahbidle         (1 << 31) /** AHB idle state*/
 109
 110 /** Core Interrupt Register */
 111 #define GINTSTS     (*((uint32_t volatile*)(OTGBASE + 0x014)))
 112 /* NOTE: GINTSTS bits are the same as in GINTMSK plus this one */
 113 #define GINTSTS_curmode     (1 << 0) /** Current mode, 0 for device */
 114
 115 /** Core Interrupt Mask Register */
 116 #define GINTMSK     (*((uint32_t volatile*)(OTGBASE + 0x018)))
 117 #define GINTMSK_modemismatch    (1 << 1) /** mode mismatch ? */
 118 #define GINTMSK_otgintr         (1 << 2)
 119 #define GINTMSK_sofintr         (1 << 3)
 120 #define GINTMSK_rxstsqlvl       (1 << 4)
 121 #define GINTMSK_nptxfempty      (1 << 5) /** Non-periodic TX fifo empty ? */
 122 #define GINTMSK_ginnakeff       (1 << 6)
 123 #define GINTMSK_goutnakeff      (1 << 7)
 124 #define GINTMSK_i2cintr         (1 << 9)
 125 #define GINTMSK_erlysuspend     (1 << 10)
 126 #define GINTMSK_usbsuspend      (1 << 11) /** USB suspend */
 127 #define GINTMSK_usbreset        (1 << 12) /** USB reset */
 128 #define GINTMSK_enumdone        (1 << 13) /** Enumeration done */
 129 #define GINTMSK_isooutdrop      (1 << 14)
 130 #define GINTMSK_eopframe        (1 << 15)
 131 #define GINTMSK_epmismatch      (1 << 17) /** endpoint mismatch ? */
 132 #define GINTMSK_inepintr        (1 << 18) /** in pending ? */
 133 #define GINTMSK_outepintr       (1 << 19) /** out pending ? */
 134 #define GINTMSK_incomplisoin    (1 << 20) /** ISP in complete ? */
 135 #define GINTMSK_incomplisoout   (1 << 21) /** ISO out complete ? */
 136 #define GINTMSK_portintr        (1 << 24) /** Port status change ? */
 137 #define GINTMSK_hcintr          (1 << 25)
 138 #define GINTMSK_ptxfempty       (1 << 26) /** Periodic TX fifof empty ? */
 139 #define GINTMSK_conidstschng    (1 << 28)
 140 #define GINTMSK_disconnect      (1 << 29) /** Disconnect */
 141 #define GINTMSK_sessreqintr     (1 << 30) /** Session request */
 142 #define GINTMSK_wkupintr        (1 << 31) /** Wake up */
 143
 144 /** Receive Status Debug Read Register (Read Only) */
 145 #define GRXSTSR     (*((uint32_t volatile*)(OTGBASE + 0x01C)))
 146
 147 /** Receive Status Read /Pop Register (Read Only) */
 148 #define GRXSTSP     (*((uint32_t volatile*)(OTGBASE + 0x020)))
 149
 150 /** Receive FIFO Size Register */
 151 #define GRXFSIZ     (*((uint32_t volatile*)(OTGBASE + 0x024)))
 152
 153 /** Periodic Transmit FIFO Size Register */
 154 #define GNPTXFSIZ   (*((uint32_t volatile*)(OTGBASE + 0x028)))
 155 #define MAKE_FIFOSIZE_DATA(depth) ((depth) | ((depth) << 16))
 156
 157 /** Non-Periodic Transmit FIFO/Queue Status Register */
 158 #define GNPTXSTS    (*((uint32_t volatile*)(OTGBASE + 0x02C)))
 159
 160 /** Device IN Endpoint Transmit FIFO (ep) Size Register */
 161 /* 1<=ep<=15, don't use ep=0 !!! */
 162 #define HPTXFSIZ    (*((uint32_t volatile*)(OTGBASE + 0x100)))
 163 #define DPTXFSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x100 + 4 * (x))))
 164
 165 /*** HOST MODE REGISTERS ***/
 166 /* Host Global Registers */
 167 #define HCFG        (*((uint32_t volatile*)(OTGBASE + 0x400)))
 168 #define HFIR        (*((uint32_t volatile*)(OTGBASE + 0x404)))
 169 #define HFNUM       (*((uint32_t volatile*)(OTGBASE + 0x408)))
 170 #define HPTXSTS     (*((uint32_t volatile*)(OTGBASE + 0x410)))
 171 #define HAINT       (*((uint32_t volatile*)(OTGBASE + 0x414)))
 172 #define HAINTMSK    (*((uint32_t volatile*)(OTGBASE + 0x418)))
 173
 174 /* Host Port Control and Status Registers */
 175 #define HPRT        (*((uint32_t volatile*)(OTGBASE + 0x440)))
 176
 177 /* Host Channel-Specific Registers */
 178 #define HCCHAR(x)   (*((uint32_t volatile*)(OTGBASE + 0x500 + 0x20 * (x))))
 179 #define HCSPLT(x)   (*((uint32_t volatile*)(OTGBASE + 0x504 + 0x20 * (x))))
 180 #define HCINT(x)    (*((uint32_t volatile*)(OTGBASE + 0x508 + 0x20 * (x))))
 181 #define HCINTMSK(x) (*((uint32_t volatile*)(OTGBASE + 0x50C + 0x20 * (x))))
 182 #define HCTSIZ(x)   (*((uint32_t volatile*)(OTGBASE + 0x510 + 0x20 * (x))))
 183 #define HCDMA(x)    (*((uint32_t volatile*)(OTGBASE + 0x514 + 0x20 * (x))))
 184 #define HCCHAR0     (*((uint32_t volatile*)(OTGBASE + 0x500)))
 185 #define HCSPLT0     (*((uint32_t volatile*)(OTGBASE + 0x504)))
 186 #define HCINT0      (*((uint32_t volatile*)(OTGBASE + 0x508)))
 187 #define HCINTMSK0   (*((uint32_t volatile*)(OTGBASE + 0x50C)))
 188 #define HCTSIZ0     (*((uint32_t volatile*)(OTGBASE + 0x510)))
 189 #define HCDMA0      (*((uint32_t volatile*)(OTGBASE + 0x514)))
 190 #define HCCHAR1     (*((uint32_t volatile*)(OTGBASE + 0x520)))
 191 #define HCSPLT1     (*((uint32_t volatile*)(OTGBASE + 0x524)))
 192 #define HCINT1      (*((uint32_t volatile*)(OTGBASE + 0x528)))
 193 #define HCINTMSK1   (*((uint32_t volatile*)(OTGBASE + 0x52C)))
 194 #define HCTSIZ1     (*((uint32_t volatile*)(OTGBASE + 0x530)))
 195 #define HCDMA1      (*((uint32_t volatile*)(OTGBASE + 0x534)))
 196 #define HCCHAR2     (*((uint32_t volatile*)(OTGBASE + 0x540)))
 197 #define HCSPLT2     (*((uint32_t volatile*)(OTGBASE + 0x544)))
 198 #define HCINT2      (*((uint32_t volatile*)(OTGBASE + 0x548)))
 199 #define HCINTMSK2   (*((uint32_t volatile*)(OTGBASE + 0x54C)))
 200 #define HCTSIZ2     (*((uint32_t volatile*)(OTGBASE + 0x550)))
 201 #define HCDMA2      (*((uint32_t volatile*)(OTGBASE + 0x554)))
 202 #define HCCHAR3     (*((uint32_t volatile*)(OTGBASE + 0x560)))
 203 #define HCSPLT3     (*((uint32_t volatile*)(OTGBASE + 0x564)))
 204 #define HCINT3      (*((uint32_t volatile*)(OTGBASE + 0x568)))
 205 #define HCINTMSK3   (*((uint32_t volatile*)(OTGBASE + 0x56C)))
 206 #define HCTSIZ3     (*((uint32_t volatile*)(OTGBASE + 0x570)))
 207 #define HCDMA3      (*((uint32_t volatile*)(OTGBASE + 0x574)))
 208 #define HCCHAR4     (*((uint32_t volatile*)(OTGBASE + 0x580)))
 209 #define HCSPLT4     (*((uint32_t volatile*)(OTGBASE + 0x584)))
 210 #define HCINT4      (*((uint32_t volatile*)(OTGBASE + 0x588)))
 211 #define HCINTMSK4   (*((uint32_t volatile*)(OTGBASE + 0x58C)))
 212 #define HCTSIZ4     (*((uint32_t volatile*)(OTGBASE + 0x590)))
 213 #define HCDMA4      (*((uint32_t volatile*)(OTGBASE + 0x594)))
 214 #define HCCHAR5     (*((uint32_t volatile*)(OTGBASE + 0x5A0)))
 215 #define HCSPLT5     (*((uint32_t volatile*)(OTGBASE + 0x5A4)))
 216 #define HCINT5      (*((uint32_t volatile*)(OTGBASE + 0x5A8)))
 217 #define HCINTMSK5   (*((uint32_t volatile*)(OTGBASE + 0x5AC)))
 218 #define HCTSIZ5     (*((uint32_t volatile*)(OTGBASE + 0x5B0)))
 219 #define HCDMA5      (*((uint32_t volatile*)(OTGBASE + 0x5B4)))
 220 #define HCCHAR6     (*((uint32_t volatile*)(OTGBASE + 0x5C0)))
 221 #define HCSPLT6     (*((uint32_t volatile*)(OTGBASE + 0x5C4)))
 222 #define HCINT6      (*((uint32_t volatile*)(OTGBASE + 0x5C8)))
 223 #define HCINTMSK6   (*((uint32_t volatile*)(OTGBASE + 0x5CC)))
 224 #define HCTSIZ6     (*((uint32_t volatile*)(OTGBASE + 0x5D0)))
 225 #define HCDMA6      (*((uint32_t volatile*)(OTGBASE + 0x5D4)))
 226 #define HCCHAR7     (*((uint32_t volatile*)(OTGBASE + 0x5E0)))
 227 #define HCSPLT7     (*((uint32_t volatile*)(OTGBASE + 0x5E4)))
 228 #define HCINT7      (*((uint32_t volatile*)(OTGBASE + 0x5E8)))
 229 #define HCINTMSK7   (*((uint32_t volatile*)(OTGBASE + 0x5EC)))
 230 #define HCTSIZ7     (*((uint32_t volatile*)(OTGBASE + 0x5F0)))
 231 #define HCDMA7      (*((uint32_t volatile*)(OTGBASE + 0x5F4)))
 232 #define HCCHAR8     (*((uint32_t volatile*)(OTGBASE + 0x600)))
 233 #define HCSPLT8     (*((uint32_t volatile*)(OTGBASE + 0x604)))
 234 #define HCINT8      (*((uint32_t volatile*)(OTGBASE + 0x608)))
 235 #define HCINTMSK8   (*((uint32_t volatile*)(OTGBASE + 0x60C)))
 236 #define HCTSIZ8     (*((uint32_t volatile*)(OTGBASE + 0x610)))
 237 #define HCDMA8      (*((uint32_t volatile*)(OTGBASE + 0x614)))
 238 #define HCCHAR9     (*((uint32_t volatile*)(OTGBASE + 0x620)))
 239 #define HCSPLT9     (*((uint32_t volatile*)(OTGBASE + 0x624)))
 240 #define HCINT9      (*((uint32_t volatile*)(OTGBASE + 0x628)))
 241 #define HCINTMSK9   (*((uint32_t volatile*)(OTGBASE + 0x62C)))
 242 #define HCTSIZ9     (*((uint32_t volatile*)(OTGBASE + 0x630)))
 243 #define HCDMA9      (*((uint32_t volatile*)(OTGBASE + 0x634)))
 244 #define HCCHAR10    (*((uint32_t volatile*)(OTGBASE + 0x640)))
 245 #define HCSPLT10    (*((uint32_t volatile*)(OTGBASE + 0x644)))
 246 #define HCINT10     (*((uint32_t volatile*)(OTGBASE + 0x648)))
 247 #define HCINTMSK10  (*((uint32_t volatile*)(OTGBASE + 0x64C)))
 248 #define HCTSIZ10    (*((uint32_t volatile*)(OTGBASE + 0x650)))
 249 #define HCDMA10     (*((uint32_t volatile*)(OTGBASE + 0x654)))
 250 #define HCCHAR11    (*((uint32_t volatile*)(OTGBASE + 0x660)))
 251 #define HCSPLT11    (*((uint32_t volatile*)(OTGBASE + 0x664)))
 252 #define HCINT11     (*((uint32_t volatile*)(OTGBASE + 0x668)))
 253 #define HCINTMSK11  (*((uint32_t volatile*)(OTGBASE + 0x66C)))
 254 #define HCTSIZ11    (*((uint32_t volatile*)(OTGBASE + 0x670)))
 255 #define HCDMA11     (*((uint32_t volatile*)(OTGBASE + 0x674)))
 256 #define HCCHAR12    (*((uint32_t volatile*)(OTGBASE + 0x680)))
 257 #define HCSPLT12    (*((uint32_t volatile*)(OTGBASE + 0x684)))
 258 #define HCINT12     (*((uint32_t volatile*)(OTGBASE + 0x688)))
 259 #define HCINTMSK12  (*((uint32_t volatile*)(OTGBASE + 0x68C)))
 260 #define HCTSIZ12    (*((uint32_t volatile*)(OTGBASE + 0x690)))
 261 #define HCDMA12     (*((uint32_t volatile*)(OTGBASE + 0x694)))
 262 #define HCCHAR13    (*((uint32_t volatile*)(OTGBASE + 0x6A0)))
 263 #define HCSPLT13    (*((uint32_t volatile*)(OTGBASE + 0x6A4)))
 264 #define HCINT13     (*((uint32_t volatile*)(OTGBASE + 0x6A8)))
 265 #define HCINTMSK13  (*((uint32_t volatile*)(OTGBASE + 0x6AC)))
 266 #define HCTSIZ13    (*((uint32_t volatile*)(OTGBASE + 0x6B0)))
 267 #define HCDMA13     (*((uint32_t volatile*)(OTGBASE + 0x6B4)))
 268 #define HCCHAR14    (*((uint32_t volatile*)(OTGBASE + 0x6C0)))
 269 #define HCSPLT14    (*((uint32_t volatile*)(OTGBASE + 0x6C4)))
 270 #define HCINT14     (*((uint32_t volatile*)(OTGBASE + 0x6C8)))
 271 #define HCINTMSK14  (*((uint32_t volatile*)(OTGBASE + 0x6CC)))
 272 #define HCTSIZ14    (*((uint32_t volatile*)(OTGBASE + 0x6D0)))
 273 #define HCDMA14     (*((uint32_t volatile*)(OTGBASE + 0x6D4)))
 274 #define HCCHAR15    (*((uint32_t volatile*)(OTGBASE + 0x6E0)))
 275 #define HCSPLT15    (*((uint32_t volatile*)(OTGBASE + 0x6E4)))
 276 #define HCINT15     (*((uint32_t volatile*)(OTGBASE + 0x6E8)))
 277 #define HCINTMSK15  (*((uint32_t volatile*)(OTGBASE + 0x6EC)))
 278 #define HCTSIZ15    (*((uint32_t volatile*)(OTGBASE + 0x6F0)))
 279 #define HCDMA15     (*((uint32_t volatile*)(OTGBASE + 0x6F4)))
 280
 281 /*** DEVICE MODE REGISTERS ***/
 282 /* Device Global Registers */
 283
 284 /** Device Configuration Register */
 285 #define DCFG        (*((uint32_t volatile*)(OTGBASE + 0x800)))
 286 #define DCFG_devspd_bitp        0 /** Device Speed */
 287 #define DCFG_devspd_bits        0x3
 288 #define DCFG_devspd_hs_phy_hs   0 /** High speed PHY running at high speed */
 289 #define DCFG_devspd_hs_phy_fs   1 /** High speed PHY running at full speed */
 290 #define DCFG_nzstsouthshk       (1 << 2) /** Non Zero Length Status OUT Handshake */
 291 #define DCFG_devadr_bitp        4 /** Device Address */
 292 #define DCFG_devadr_bits        0x7f
 293 #define DCFG_perfrint_bitp      11 /** Periodic Frame Interval */
 294 #define DCFG_perfrint_bits      0x3
 295 #define DCFG_FRAME_INTERVAL_80  0
 296 #define DCFG_FRAME_INTERVAL_85  1
 297 #define DCFG_FRAME_INTERVAL_90  2
 298 #define DCFG_FRAME_INTERVAL_95  3
 299
 300 /** Device Control Register */
 301 #define DCTL        (*((uint32_t volatile*)(OTGBASE + 0x804)))
 302 #define DCTL_rmtwkupsig     (1 << 0) /** Remote Wakeup */
 303 #define DCTL_sftdiscon      (1 << 1) /** Soft Disconnect */
 304 #define DCTL_gnpinnaksts    (1 << 2) /** Global Non-Periodic IN NAK Status */
 305 #define DCTL_goutnaksts     (1 << 3) /** Global OUT NAK Status */
 306 #define DCTL_tstctl_bitp    4 /** Test Control */
 307 #define DCTL_tstctl_bits    0x7
 308 #define DCTL_sgnpinnak      (1 << 7) /** Set Global Non-Periodic IN NAK */
 309 #define DCTL_cgnpinnak      (1 << 8) /** Clear Global Non-Periodic IN NAK */
 310 #define DCTL_sgoutnak       (1 << 9) /** Set Global OUT NAK */
 311 #define DCTL_cgoutnak       (1 << 10) /** Clear Global OUT NAK */
 312 #define DCTL_pwronprgdone   (1 << 11) /** Power on Program Done ? */
 313
 314 /** Device Status Register */
 315 #define DSTS        (*((uint32_t volatile*)(OTGBASE + 0x808)))
 316 #define DSTS_suspsts        (1 << 0) /** Suspend status */
 317 #define DSTS_enumspd_bitp   1 /** Enumerated speed */
 318 #define DSTS_enumspd_bits   0x3
 319 #define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
 320 #define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
 321 #define DSTS_ENUMSPD_LS_PHY_6MHZ           2
 322 #define DSTS_ENUMSPD_FS_PHY_48MHZ          3
 323 #define DSTS_errticerr      (1 << 3) /** Erratic errors ? */
 324 #define DSTS_soffn_bitp     8 /** Frame or Microframe Number of the received SOF */
 325 #define DSTS_soffn_bits     0x3fff
 326
 327 /** Device IN Endpoint Common Interrupt Mask Register */
 328 #define DIEPMSK     (*((uint32_t volatile*)(OTGBASE + 0x810)))
 329 /* the following apply to DEPMSK and DEPINT */
 330 #define DEPINT_xfercompl       (1 << 0) /** Transfer complete */
 331 #define DEPINT_epdisabled      (1 << 1) /** Endpoint disabled */
 332 #define DEPINT_ahberr          (1 << 2) /** AHB error */
 333 #define DIEPINT_timeout         (1 << 3) /** Timeout handshake (non-iso TX) */
 334 #define DOEPINT_setup           (1 << 3) /** Setup Phase Done (control EPs)*/
 335 #define DIEPINT_intktxfemp      (1 << 4) /** IN token received with tx fifo empty */
 336 #define DIEPINT_intknepmis      (1 << 5) /** IN token received with ep mismatch */
 337 #define DIEPINT_inepnakeff      (1 << 6) /** IN endpoint NAK effective */
 338 #define DIEPINT_emptyintr       (1 << 7) /** linux doc broken on this, empty fifo ? */
 339 #define DIEPINT_txfifoundrn     (1 << 8) /** linux doc void on this, tx fifo underrun ? */
 340
 341 /** Device OUT Endpoint Common Interrupt Mask Register */
 342 #define DOEPMSK     (*((uint32_t volatile*)(OTGBASE + 0x814)))
 343
 344 /** Device All Endpoints Interrupt Register */
 345 #define DAINT       (*((uint32_t volatile*)(OTGBASE + 0x818)))
 346 /* valid for DAINT and DAINTMSK, for 0<=ep<=15 */
 347 #define DAINT_IN_EP(i)      (1 << (i))
 348 #define DAINT_OUT_EP(i)     (1 << ((i) + 16))
 349
 350 /** Device Endpoints Interrupt Mask Register */
 351 #define DAINTMSK    (*((uint32_t volatile*)(OTGBASE + 0x81C)))
 352
 353 /** Device IN Token Sequence Learning Queue Read Register 1 */
 354 #define DTKNQR1     (*((uint32_t volatile*)(OTGBASE + 0x820)))
 355
 356 /** Device IN Token Sequence Learning Queue Register 2 */
 357 #define DTKNQR2     (*((uint32_t volatile*)(OTGBASE + 0x824)))
 358
 359 /* fixme: those registers are not present in registers.h but are in dwc_otgh_regs.h.
 360  *        the previous registers exists but has a different name :( */
 361 /** Device VBUS discharge register*/
 362 #define DVBUSDIS    (*((uint32_t volatile*)(OTGBASE + 0x828)))
 363
 364 /** Device VBUS pulse register */
 365 #define DVBUSPULSE  (*((uint32_t volatile*)(OTGBASE + 0x82C)))
 366
 367 // FIXME : 2 names for the same reg?
 368 /** Device IN Token Queue Read Register 3 (RO) */
 369 /** Device Thresholding control register */
 370 #define DTKNQR3     (*((uint32_t volatile*)(OTGBASE + 0x830)))
 371 #define DTHRCTL     (*((uint32_t volatile*)(OTGBASE + 0x830)))
 372 #define DTHRCTL_non_iso_thr_en      (1 << 0)
 373 #define DTHRCTL_iso_thr_en          (1 << 1)
 374 #define DTHRCTL_tx_thr_len_bitp     2
 375 #define DTHRCTL_tx_thr_len_bits     0x1FF
 376 #define DTHRCTL_rx_thr_en           (1 << 16)
 377 #define DTHRCTL_rx_thr_len_bitp     17
 378 #define DTHRCTL_rx_thr_len_bits     0x1FF
 379
 380 /** Device IN Token Queue Read Register 4 (RO) */
 381 #define DTKNQR4     (*((uint32_t volatile*)(OTGBASE + 0x834)))
 382
 383 /* Device Logical Endpoint-Specific Registers */
 384 #define DEPCTL(x, out)  (*((uint32_t volatile*)(OTGBASE + 0x900 + ((!!out) * 0x200) + 0x20 * (x))))
 385 /** Maximum Packet Size
 386  * IN/OUT EPn
 387  * IN/OUT EP0 - 2 bits
 388  *  2'b00: 64 Bytes
 389  *  2'b01: 32
 390  *  2'b10: 16
 391  *  2'b11: 8 */
 392 #define DEPCTL_mps_bitp         0
 393 #define DEPCTL_mps_bits         0x7ff
 394 #define DEPCTL_MPS_64           0
 395 #define DEPCTL_MPS_32           1
 396 #define DEPCTL_MPS_16           2
 397 #define DEPCTL_MPS_8            3
 398 /** Next Endpoint
 399  * IN EPn/IN EP0
 400  * OUT EPn/OUT EP0 - reserved */
 401 #define DEPCTL_nextep_bitp      11
 402 #define DEPCTL_nextep_bits      0xf
 403 #define DEPCTL_usbactep         (1 << 15) /** USB Active Endpoint */
 404 /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
 405  * This field contains the PID of the packet going to
 406  * be received or transmitted on this endpoint. The
 407  * application should program the PID of the first
 408  * packet going to be received or transmitted on this
 409  * endpoint , after the endpoint is
 410  * activated. Application use the SetD1PID and
 411  * SetD0PID fields of this register to program either
 412  * D0 or D1 PID.
 413  *
 414  * The encoding for this field is
 415  * - 0: D0
 416  * - 1: D1
 417  */
 418 #define DEPCTL_dpid             (1 << 16)
 419 #define DEPCTL_naksts           (1 << 17) /** NAK Status */
 420 /** Endpoint Type
 421  *  2'b00: Control
 422  *  2'b01: Isochronous
 423  *  2'b10: Bulk
 424  *  2'b11: Interrupt */
 425 #define DEPCTL_eptype_bitp      18
 426 #define DEPCTL_eptype_bits      0x3
 427 /** Snoop Mode
 428  * OUT EPn/OUT EP0
 429  * IN EPn/IN EP0 - reserved */
 430 #define DEPCTL_snp              (1 << 20)
 431 #define DEPCTL_stall            (1 << 21) /** Stall Handshake */
 432 /** Tx Fifo Number
 433  * IN EPn/IN EP0
 434  * OUT EPn/OUT EP0 - reserved */
 435 #define DEPCTL_txfnum_bitp      22
 436 #define DEPCTL_txfnum_bits      0xf
 437 #define DEPCTL_cnak             (1 << 26) /** Clear NAK */
 438 #define DEPCTL_snak             (1 << 27) /** Set NAK */
 439 /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
 440  * Writing to this field sets the Endpoint DPID (DPID)
 441  * field in this register to DATA0. Set Even
 442  * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
 443  * Writing to this field sets the Even/Odd
 444  * (micro)frame (EO_FrNum) field to even (micro)
 445  * frame.
 446  */
 447 #define DEPCTL_setd0pid         (1 << 28)
 448 /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
 449  * Writing to this field sets the Endpoint DPID (DPID)
 450  * field in this register to DATA1 Set Odd
 451  * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
 452  * Writing to this field sets the Even/Odd
 453  * (micro)frame (EO_FrNum) field to odd (micro) frame.
 454  */
 455 #define DEPCTL_setd1pid         (1 << 29)
 456 #define DEPCTL_epdis            (1 << 30) /** Endpoint disable */
 457 #define DEPCTL_epena            (1 << 31) /** Endpoint enable */
 458
 459 /** Device Endpoint (ep) Transfer Size Register */
 460 #define DEPTSIZ(x, out) (*((uint32_t volatile*)(OTGBASE + 0x910 + (0x200 * (!!out)) + 0x20 * (x))))
 461 /* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */
 462 #define DEPTSIZ_xfersize_bitp   0 /** Transfer Size */
 463 #define DEPTSIZ_xfersize_bits   0x7ffff
 464 #define DEPTSIZ_pkcnt_bitp      19 /** Packet Count */
 465 #define DEPTSIZ_pkcnt_bits      0x3ff
 466 #define DEPTSIZ_mc_bitp         29 /** Multi Count - Periodic IN endpoints */
 467 #define DEPTSIZ_mc_bits         0x3
 468 /* idem but for i=0 */
 469 #define DEPTSIZ0_xfersize_bitp  0 /** Transfer Size */
 470 #define DEPTSIZ0_xfersize_bits  0x7f
 471 #define DEPTSIZ0_pkcnt_bitp     19 /** Packet Count */
 472 #define DEPTSIZ0_pkcnt_bits     0x3
 473 #define DEPTSIZ0_supcnt_bitp    29 /** Setup Packet Count (DOEPTSIZ0 Only) */
 474 #define DEPTSIZ0_supcnt_bits    0x3
 475
 476
 477 /** Device Endpoint (ep) Control Register */
 478 #define DEPINT(x,out)  (*((uint32_t volatile*)(OTGBASE + 0x908 + (0x200 * (!!out)) + 0x20 * (x))))
 479
 480 /** Device Endpoint (ep) DMA Address Register */
 481 #define DEPDMA(x,out)  (*((const void* volatile*)(OTGBASE + 0x914 + (0x200 * (!!out)) + 0x20 * (x))))
 482
 483 #if 0 /* Those are present in as3525v2, not s5l870x */
 484 /** Device IN Endpoint (ep) Transmit FIFO Status Register */
 485 #define DTXFSTS(ep) (*((const void* volatile*)(OTGBASE + 0x918 + 0x20 * (x))))
 486
 487 /** Device OUT Endpoint (ep) Frame number Register */
 488 #define DOEPFN(ep)  (*((const void* volatile*)(OTGBASE + 0xB04 + 0x20 * (x))))
 489 #endif
 490
 491 /* Power and Clock Gating Register */
 492 #define PCGCCTL     (*((uint32_t volatile*)(OTGBASE + 0xE00)))
 493
 494 /** User HW Config1 Register */
 495 #define GHWCFG1                 (*((uint32_t volatile*)(OTGBASE + 0x044)))
 496 #define GHWCFG1_epdir_bitp(ep)  (2 * (ep))
 497 #define GHWCFG1_epdir_bits      0x3
 498 #define GHWCFG1_EPDIR_BIDIR     0
 499 #define GHWCFG1_EPDIR_IN        1
 500 #define GHWCFG1_EPDIR_OUT       2
 501
 502 /** User HW Config2 Register */
 503 #define GHWCFG2                     (*((uint32_t volatile*)(OTGBASE + 0x048)))
 504 #define GHWCFG2_arch_bitp           3 /** Architecture */
 505 #define GHWCFG2_arch_bits           0x3
 506 #define GHWCFG2_hs_phy_type_bitp    6 /** High speed PHY type */
 507 #define GHWCFG2_hs_phy_type_bits    0x3
 508 #define GHWCFG2_fs_phy_type_bitp    8 /** Full speed PHY type */
 509 #define GHWCFG2_fs_phy_type_bits    0x3
 510 #define GHWCFG2_num_ep_bitp         10 /** Number of endpoints */
 511 #define GHWCFG2_num_ep_bits         0xf
 512 #define GHWCFG2_dyn_fifo            (1 << 19) /** Dynamic FIFO */
 513 /* For GHWCFG2_HS_PHY_TYPE and GHWCFG2_FS_PHY_TYPE */
 514 #define GHWCFG2_PHY_TYPE_UNSUPPORTED        0
 515 #define GHWCFG2_PHY_TYPE_UTMI               1
 516 #define GHWCFG2_ARCH_INTERNAL_DMA           2
 517
 518 /** User HW Config3 Register */
 519 #define GHWCFG3                 (*((uint32_t volatile*)(OTGBASE + 0x04C)))
 520 #define GHWCFG3_dfifo_len_bitp  16 /** Total fifo size */
 521 #define GHWCFG3_dfifo_len_bits  0xffff
 522
 523 /** User HW Config4 Register */
 524 #define GHWCFG4                             (*((uint32_t volatile*)(OTGBASE + 0x050)))
 525 #define GHWCFG4_utmi_phy_data_width_bitp    14 /** UTMI+ data bus width */
 526 #define GHWCFG4_utmi_phy_data_width_bits    0x3
 527 #define GHWCFG4_ded_fifo_en                 (1 << 25) /** Dedicated Tx FIFOs */
 528 #define GHWCFG4_num_in_ep_bitp              26 /** Number of IN endpoints */
 529 #define GHWCFG4_num_in_ep_bits              0xf
 530
 531 #endif /* USB_S3C6400X_H */