firmware/target/arm/imx233/icoll-imx233.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2012 by amaury Pouly
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "icoll-imx233.h"
  23 #include "rtc-imx233.h"
  24 #include "kernel-imx233.h"
  25 #include "string.h"
  26
  27 #define default_interrupt(name) \
  28     extern __attribute__((weak, alias("UIRQ"))) void name(void)
  29
  30 static void UIRQ (void) __attribute__((interrupt ("IRQ")));
  31 void irq_handler(void) __attribute__((interrupt("IRQ")));
  32 void fiq_handler(void) __attribute__((interrupt("FIQ")));
  33
  34 default_interrupt(INT_USB_CTRL);
  35 default_interrupt(INT_TIMER0);
  36 default_interrupt(INT_TIMER1);
  37 default_interrupt(INT_TIMER2);
  38 default_interrupt(INT_TIMER3);
  39 default_interrupt(INT_LCDIF_DMA);
  40 default_interrupt(INT_LCDIF_ERROR);
  41 default_interrupt(INT_SSP1_DMA);
  42 default_interrupt(INT_SSP1_ERROR);
  43 default_interrupt(INT_SSP2_DMA);
  44 default_interrupt(INT_SSP2_ERROR);
  45 default_interrupt(INT_I2C_DMA);
  46 default_interrupt(INT_I2C_ERROR);
  47 default_interrupt(INT_GPIO0);
  48 default_interrupt(INT_GPIO1);
  49 default_interrupt(INT_GPIO2);
  50 default_interrupt(INT_VDD5V);
  51 default_interrupt(INT_LRADC_CH0);
  52 default_interrupt(INT_LRADC_CH1);
  53 default_interrupt(INT_LRADC_CH2);
  54 default_interrupt(INT_LRADC_CH3);
  55 default_interrupt(INT_LRADC_CH4);
  56 default_interrupt(INT_LRADC_CH5);
  57 default_interrupt(INT_LRADC_CH6);
  58 default_interrupt(INT_LRADC_CH7);
  59 default_interrupt(INT_DAC_DMA);
  60 default_interrupt(INT_DAC_ERROR);
  61 default_interrupt(INT_ADC_DMA);
  62 default_interrupt(INT_ADC_ERROR);
  63 default_interrupt(INT_DCP);
  64 default_interrupt(INT_TOUCH_DETECT);
  65 default_interrupt(INT_RTC_1MSEC);
  66
  67 void INT_RTC_1MSEC(void);
  68
  69 typedef void (*isr_t)(void);
  70
  71 static isr_t isr_table[INT_SRC_NR_SOURCES] =
  72 {
  73     [INT_SRC_USB_CTRL] = INT_USB_CTRL,
  74     [INT_SRC_TIMER(0)] = INT_TIMER0,
  75     [INT_SRC_TIMER(1)] = INT_TIMER1,
  76     [INT_SRC_TIMER(2)] = INT_TIMER2,
  77     [INT_SRC_TIMER(3)] = INT_TIMER3,
  78     [INT_SRC_LCDIF_DMA] = INT_LCDIF_DMA,
  79     [INT_SRC_LCDIF_ERROR] = INT_LCDIF_ERROR,
  80     [INT_SRC_SSP1_DMA] = INT_SSP1_DMA,
  81     [INT_SRC_SSP1_ERROR] = INT_SSP1_ERROR,
  82     [INT_SRC_SSP2_DMA] = INT_SSP2_DMA,
  83     [INT_SRC_SSP2_ERROR] = INT_SSP2_ERROR,
  84     [INT_SRC_I2C_DMA] = INT_I2C_DMA,
  85     [INT_SRC_I2C_ERROR] = INT_I2C_ERROR,
  86     [INT_SRC_GPIO0] = INT_GPIO0,
  87     [INT_SRC_GPIO1] = INT_GPIO1,
  88     [INT_SRC_GPIO2] = INT_GPIO2,
  89     [INT_SRC_VDD5V] = INT_VDD5V,
  90     [INT_SRC_LRADC_CHx(0)] = INT_LRADC_CH0,
  91     [INT_SRC_LRADC_CHx(1)] = INT_LRADC_CH1,
  92     [INT_SRC_LRADC_CHx(2)] = INT_LRADC_CH2,
  93     [INT_SRC_LRADC_CHx(3)] = INT_LRADC_CH3,
  94     [INT_SRC_LRADC_CHx(4)] = INT_LRADC_CH4,
  95     [INT_SRC_LRADC_CHx(5)] = INT_LRADC_CH5,
  96     [INT_SRC_LRADC_CHx(6)] = INT_LRADC_CH6,
  97     [INT_SRC_LRADC_CHx(7)] = INT_LRADC_CH7,
  98     [INT_SRC_DAC_DMA] = INT_DAC_DMA,
  99     [INT_SRC_DAC_ERROR] = INT_DAC_ERROR,
 100     [INT_SRC_ADC_DMA] = INT_ADC_DMA,
 101     [INT_SRC_ADC_ERROR] = INT_ADC_ERROR,
 102     [INT_SRC_DCP] = INT_DCP,
 103     [INT_SRC_TOUCH_DETECT] = INT_TOUCH_DETECT,
 104     [INT_SRC_RTC_1MSEC] = INT_RTC_1MSEC,
 105 };
 106
 107 #define IRQ_STORM_DELAY         100 /* ms */
 108 #define IRQ_STORM_THRESHOLD     10000 /* allows irq / delay */
 109
 110 static uint32_t irq_count_old[INT_SRC_NR_SOURCES];
 111 static uint32_t irq_count[INT_SRC_NR_SOURCES];
 112
 113 struct imx233_icoll_irq_info_t imx233_icoll_get_irq_info(int src)
 114 {
 115     struct imx233_icoll_irq_info_t info;
 116     info.enabled = !!(HW_ICOLL_INTERRUPT(src) & HW_ICOLL_INTERRUPT__ENABLE);
 117     info.freq = irq_count_old[src];
 118     return info;
 119 }
 120
 121 static void do_irq_stat(void)
 122 {
 123     static unsigned counter = 0;
 124     if(counter++ >= HZ)
 125     {
 126         counter = 0;
 127         memcpy(irq_count_old, irq_count, sizeof(irq_count));
 128         memset(irq_count, 0, sizeof(irq_count));
 129     }
 130 }
 131
 132 static void UIRQ(void)
 133 {
 134     panicf("Unhandled IRQ %02X",
 135         (unsigned int)(HW_ICOLL_VECTOR - (uint32_t)isr_table) / 4);
 136 }
 137
 138 void irq_handler(void)
 139 {
 140     HW_ICOLL_VECTOR = HW_ICOLL_VECTOR; /* notify icoll that we entered ISR */
 141     int irq_nr = (HW_ICOLL_VECTOR - HW_ICOLL_VBASE) / 4;
 142     if(irq_count[irq_nr]++ > IRQ_STORM_THRESHOLD)
 143         panicf("IRQ %d: storm detected", irq_nr);
 144     if(irq_nr == INT_SRC_TIMER(TICK_TIMER_NR))
 145         do_irq_stat();
 146     (*(isr_t *)HW_ICOLL_VECTOR)();
 147     /* acknowledge completion of IRQ (all use the same priority 0) */
 148     HW_ICOLL_LEVELACK = HW_ICOLL_LEVELACK__LEVEL0;
 149 }
 150
 151 void fiq_handler(void)
 152 {
 153 }
 154
 155 void imx233_icoll_enable_interrupt(int src, bool enable)
 156 {
 157     if(enable)
 158         __REG_SET(HW_ICOLL_INTERRUPT(src)) = HW_ICOLL_INTERRUPT__ENABLE;
 159     else
 160         __REG_CLR(HW_ICOLL_INTERRUPT(src)) = HW_ICOLL_INTERRUPT__ENABLE;
 161 }
 162
 163 void imx233_icoll_init(void)
 164 {
 165     imx233_reset_block(&HW_ICOLL_CTRL);
 166     /* disable all interrupts */
 167     for(int i = 0; i < INT_SRC_NR_SOURCES; i++)
 168     {
 169         /* priority = 0, disable, disable fiq */
 170         HW_ICOLL_INTERRUPT(i) = 0;
 171     }
 172     /* setup vbase as isr_table */
 173     HW_ICOLL_VBASE = (uint32_t)&isr_table;
 174     /* enable final irq bit */
 175     __REG_SET(HW_ICOLL_CTRL) = HW_ICOLL_CTRL__IRQ_FINAL_ENABLE;
 176 }
 177