firmware/target/arm/tms320dm320/uart-dm320.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007 Catalin Patulea <cat@vv.carleton.ca>
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "config.h"
  22 #include "cpu.h"
  23 #include "system.h"
  24 #include "string.h"
  25 #include "panic.h"
  26 #include "uart-target.h"
  27
  28 #define MAX_UART_BUFFER     31
  29 #define SEND_RING_SIZE      256
  30 #define RECEIVE_RING_SIZE   20
  31
  32 static char
  33     uart1_send_buffer_ring[SEND_RING_SIZE],
  34     uart1_receive_buffer_ring[RECEIVE_RING_SIZE];
  35
  36 static volatile int uart1_send_count, uart1_send_read, uart1_send_write;
  37 static volatile int uart1_receive_count, uart1_receive_read, uart1_receive_write;
  38
  39 void uart_init(void)
  40 {
  41     /* Enable UART clock */
  42     bitset16(&IO_CLK_MOD2, CLK_MOD2_UART1);
  43
  44     // 8-N-1
  45     IO_UART1_MSR = 0xC400;
  46     IO_UART1_BRSR = 0x0057;
  47     IO_UART1_RFCR = 0x8020; /* Trigger later */
  48     IO_UART1_TFCR = 0x0000; /* Trigger level */
  49
  50     /* init the receive buffer */
  51     uart1_receive_count=0;
  52     uart1_receive_read=0;
  53     uart1_receive_write=0;
  54
  55     /* init the send buffer */
  56     uart1_send_count=0;
  57     uart1_send_read=0;
  58     uart1_send_write=0;
  59
  60     /* Enable the interrupt */
  61     bitset16(&IO_INTC_EINT0, INTR_EINT0_UART1);
  62 }
  63
  64 /* This function is not interrupt driven */
  65 void uart1_putc(char ch)
  66 {
  67     /* Wait for the interupt driven puts to finish */
  68     while(uart1_send_count>0);
  69
  70     /* Wait for room in FIFO */
  71     while ((IO_UART1_TFCR & 0x3f) >= 0x20);
  72
  73     /* Write character */
  74     IO_UART1_DTRR=ch;
  75 }
  76
  77 void uart1_puts(const char *str, int size)
  78 {
  79     if(size>SEND_RING_SIZE)
  80         panicf("Too much data passed to uart1_puts");
  81
  82     /* Wait for the previous transfer to finish */
  83     while(uart1_send_count>0);
  84
  85     memcpy(uart1_send_buffer_ring, str, size);
  86
  87     /* Disable interrupt while modifying the pointers */
  88     bitclr16(&IO_INTC_EINT0, INTR_EINT0_UART1);
  89
  90     uart1_send_count=size;
  91     uart1_send_read=0;
  92
  93     /* prime the hardware buffer */
  94     while(((IO_UART1_TFCR & 0x3f) < 0x20) && (uart1_send_count > 0))
  95     {
  96         IO_UART1_DTRR=uart1_send_buffer_ring[uart1_send_read++];
  97         uart1_send_count--;
  98     }
  99
 100     /* Enable interrupt */
 101     bitset16(&IO_INTC_EINT0, INTR_EINT0_UART1);
 102 }
 103
 104 void uart1_clear_queue(void)
 105 {
 106     /* Disable interrupt while modifying the pointers */
 107     bitclr16(&IO_INTC_EINT0, INTR_EINT0_UART1);
 108
 109     uart1_receive_write=0;
 110     uart1_receive_count=0;
 111     uart1_receive_read=0;
 112
 113     /* Enable interrupt */
 114     bitset16(&IO_INTC_EINT0, INTR_EINT0_UART1);
 115 }
 116
 117 /* This function returns the number of bytes left in the queue after a read is done (negative if fail)*/
 118 int uart1_gets_queue(char *str, int size)
 119 {
 120     /* Disable the interrupt while modifying the pointers */
 121     bitclr16(&IO_INTC_EINT0, INTR_EINT0_UART1);
 122     int retval;
 123
 124     if(uart1_receive_count<size)
 125     {
 126         retval= -1;
 127     }
 128     else
 129     {
 130         if(uart1_receive_read+size<=RECEIVE_RING_SIZE)
 131         {
 132             memcpy(str,uart1_receive_buffer_ring+uart1_receive_read,size);
 133
 134             uart1_receive_read+=size;
 135         }
 136         else
 137         {
 138             int tempcount=(RECEIVE_RING_SIZE-uart1_receive_read);
 139             memcpy(str,uart1_receive_buffer_ring+uart1_receive_read,tempcount);
 140             memcpy(str+tempcount,uart1_receive_buffer_ring,size-tempcount);
 141
 142             uart1_receive_read=size-tempcount;
 143         }
 144
 145         uart1_receive_count-=size;
 146
 147         retval=uart1_receive_count;
 148     }
 149
 150     /* Enable the interrupt */
 151     bitset16(&IO_INTC_EINT0, INTR_EINT0_UART1);
 152
 153     return retval;
 154 }
 155
 156 /* UART1 receive/transmit interupt handler */
 157 void UART1(void)
 158 {
 159     IO_INTC_IRQ0 = INTR_IRQ0_UART1; /* Clear the interrupt first */
 160     while (IO_UART1_RFCR & 0x3f)
 161     {
 162         if (uart1_receive_count > RECEIVE_RING_SIZE)
 163             panicf("UART1 receive buffer overflow");
 164         else
 165         {
 166             if(uart1_receive_write>=RECEIVE_RING_SIZE)
 167                 uart1_receive_write=0;
 168
 169             uart1_receive_buffer_ring[uart1_receive_write]=IO_UART1_DTRR & 0xff;
 170             uart1_receive_write++;
 171             uart1_receive_count++;
 172         }
 173     }
 174
 175     while ( ((IO_UART1_TFCR & 0x3f) < 0x20) && (uart1_send_count > 0) )
 176     {
 177         IO_UART1_DTRR=uart1_send_buffer_ring[uart1_send_read++];
 178         uart1_send_count--;
 179     }
 180 }
 181