firmware/target/arm/s3c2440/sd-s3c2440.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2009 by Bob Cousins
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 //#define SD_DEBUG
  23
  24 #include "sd.h"
  25 #include "system.h"
  26 #include <string.h>
  27 #include "gcc_extensions.h"
  28 #include "thread.h"
  29 #include "panic.h"
  30
  31 #ifdef SD_DEBUG
  32 #include "uart-s3c2440.h"
  33 #endif
  34 #ifdef HAVE_HOTSWAP
  35 #include "sdmmc.h"
  36 #include "disk.h"
  37 #include "fat.h"
  38 #endif
  39 #include "dma-target.h"
  40 #include "system-target.h"
  41 #include "led-mini2440.h"
  42
  43 /* The configuration method is not very flexible. */
  44 #define CARD_NUM_SLOT   0
  45 #define NUM_CARDS       2
  46
  47 #define EC_OK                    0
  48 #define EC_FAILED                1
  49 #define EC_NOCARD                2
  50 #define EC_WAIT_STATE_FAILED     3
  51 #define EC_POWER_UP              4
  52 #define EC_FIFO_WR_EMPTY         5
  53 #define EC_FIFO_WR_DONE          6
  54 #define EC_TRAN_READ_ENTRY       7
  55 #define EC_TRAN_READ_EXIT        8
  56 #define EC_TRAN_WRITE_ENTRY      9
  57 #define EC_TRAN_WRITE_EXIT       10
  58 #define EC_COMMAND               11
  59 #define EC_WRITE_PROTECT         12
  60
  61 #define MIN_YIELD_PERIOD        1000
  62 #define UNALIGNED_NUM_SECTORS   10
  63 #define MAX_TRANSFER_ERRORS     10
  64
  65 /* command flags for send_cmd */
  66 #define MCI_NO_FLAGS    (0<<0)
  67 #define MCI_RESP        (1<<0)
  68 #define MCI_LONG_RESP   (1<<1)
  69 #define MCI_ARG         (1<<2)
  70
  71 #define INITIAL_CLK    400000   /* Initial clock */
  72 #define SD_CLK       24000000   /* Clock for SD cards */
  73 #define MMC_CLK      15000000   /* Clock for MMC cards */
  74
  75 #define SD_ACTIVE_LED   LED4
  76
  77 #ifdef SD_DEBUG
  78 #define dbgprintf uart_printf
  79 #else
  80 #define dbgprintf(...)
  81 #endif
  82
  83 struct sd_card_status
  84 {
  85     int retry;
  86     int retry_max;
  87 };
  88
  89 /** static, private data **/
  90
  91 /* for compatibility */
  92 static long last_disk_activity = -1;
  93
  94 static bool initialized = false;
  95 static bool sd_enabled = false;
  96 static long next_yield = 0;
  97
  98 static tCardInfo card_info [NUM_CARDS];
  99
 100 #ifdef HAVE_MULTIDRIVE
 101 static int curr_card = 0; /* current active card */
 102 #if 0
 103 static struct sd_card_status sd_status[NUM_CARDS] =
 104 {
 105 #if NUM_CARDS > 1
 106     {0, 10},
 107 #endif
 108     {0, 10}
 109 };
 110 #endif
 111 #endif
 112
 113 /* Shoot for around 75% usage */
 114 static long             sd_stack [(DEFAULT_STACK_SIZE*2 + 0x1c0)/sizeof(long)];
 115 static const char               sd_thread_name[] = "sd";
 116 static struct mutex             sd_mtx SHAREDBSS_ATTR;
 117 static struct event_queue       sd_queue;
 118 static struct semaphore         transfer_completion_signal;
 119 static volatile unsigned int    transfer_error[NUM_DRIVES];
 120 /* align on cache line size */
 121 static unsigned char    aligned_buffer[UNALIGNED_NUM_SECTORS * SD_BLOCK_SIZE]
 122                         __attribute__((aligned(32)));
 123 static unsigned char *  uncached_buffer;
 124
 125 static inline void mci_delay(void)
 126 {
 127     int i = 0xffff;
 128     while (i--)
 129         asm volatile ("nop\n");
 130 }
 131
 132 /* TODO: should be in target include file */
 133 /*****************************************************************************
 134     Definitions specific to Mini2440
 135  *****************************************************************************/
 136
 137 #define SD_CD (1<<8)    /* Port G */
 138 #define SD_WP (1<<8)    /* Port H */
 139
 140 /*****************************************************************************
 141     Functions specific to S3C2440 SoC
 142  *****************************************************************************/
 143
 144 #ifdef SD_DEBUG
 145 static unsigned reg_copy[16], reg_copy2[16];
 146 static void get_regs (unsigned *regs)
 147 {
 148     unsigned j;
 149     volatile unsigned long *sdi_reg = &SDICON;
 150
 151     for (j=0; j < 16;j++)
 152     {
 153         *regs++ = *sdi_reg++;
 154     }
 155 }
 156
 157 static void dump_regs (unsigned *regs1, unsigned *regs2)
 158 {
 159     unsigned j;
 160     volatile unsigned long*sdi_reg = &SDICON;
 161     unsigned long diff;
 162
 163     for (j=0; j < 16;j++)
 164     {
 165         diff = *regs1 ^ *regs2;
 166         if (diff)
 167             dbgprintf ("%8x %8x %8x %8x\n", sdi_reg, *regs1, *regs2, diff );
 168         regs1++;
 169         regs2++;
 170         sdi_reg++;
 171     }
 172 }
 173 #endif
 174
 175 static void debug_r1(int cmd)
 176 {
 177 #if defined(SD_DEBUG)
 178     dbgprintf("CMD%2.2d:SDICSTA=%04x [%c%c%c%c%c-%c%c%c%c%c%c%c]  SDIRSP0=%08x [%d %s] \n",
 179         cmd,
 180         SDICSTA,
 181         (SDICSTA & S3C2410_SDICMDSTAT_CRCFAIL)    ? 'C' : ' ',
 182         (SDICSTA & S3C2410_SDICMDSTAT_CMDSENT)    ? 'S' : ' ',
 183         (SDICSTA & S3C2410_SDICMDSTAT_CMDTIMEOUT) ? 'T' : ' ',
 184         (SDICSTA & S3C2410_SDICMDSTAT_RSPFIN)     ? 'R' : ' ',
 185         (SDICSTA & S3C2410_SDICMDSTAT_XFERING)    ? 'X' : ' ',
 186
 187         (SDICSTA & 0x40)    ? 'P' : ' ',
 188         (SDICSTA & 0x20)    ? 'A' : ' ',
 189         (SDICSTA & 0x10)    ? 'E' : ' ',
 190         (SDICSTA & 0x08)    ? 'C' : ' ',
 191         (SDICSTA & 0x04)    ? 'I' : ' ',
 192         (SDICSTA & 0x02)    ? 'R' : ' ',
 193         (SDICSTA & 0x01)    ? 'Z' : ' ',
 194
 195         SDIRSP0,
 196         SD_R1_CURRENT_STATE(SDIRSP0),
 197         (SDIRSP0 & SD_R1_READY_FOR_DATA) ? "RDY " : "    "
 198         );
 199 #else
 200     (void)cmd;
 201 #endif
 202 }
 203
 204 void SDI (void)
 205 {
 206     int status = SDIDSTA;
 207 #ifndef HAVE_MULTIDRIVE
 208     const int curr_card = 0;
 209 #endif
 210
 211     transfer_error[curr_card] = status
 212 #if 0
 213         & ( S3C2410_SDIDSTA_CRCFAIL | S3C2410_SDIDSTA_RXCRCFAIL |
 214             S3C2410_SDIDSTA_DATATIMEOUT )
 215 #endif
 216         ;
 217
 218     SDIDSTA |= S3C2410_SDIDSTA_CLEAR_BITS;  /* needed to clear int  */
 219
 220     dbgprintf ("SDI %x\n", transfer_error[curr_card]);
 221
 222     semaphore_release(&transfer_completion_signal);
 223
 224     /* Ack the interrupt */
 225     SRCPND = SDI_MASK;
 226     INTPND = SDI_MASK;
 227 }
 228
 229 #if 0
 230 void dma_callback (void)
 231 {
 232     const int status = SDIDSTA;
 233
 234     transfer_error[0] = status & (S3C2410_SDIDSTA_CRCFAIL |
 235         S3C2410_SDIDSTA_RXCRCFAIL   |
 236         S3C2410_SDIDSTA_DATATIMEOUT );
 237
 238     SDIDSTA |= S3C2410_SDIDSTA_CLEAR_BITS;  /* needed to clear int  */
 239
 240     dbgprintf ("dma_cb\n");
 241     semaphore_release(&transfer_completion_signal);
 242 }
 243 #endif
 244
 245 static void init_sdi_controller(const int card_no)
 246 {
 247     (void)card_no;
 248
 249 /*****************************************************************************/
 250 #ifdef MINI2440
 251     /* Specific to Mini2440 */
 252
 253     /* Enable pullups on SDCMD and SDDAT pins */
 254     S3C2440_GPIO_PULLUP (GPEUP, 6, GPIO_PULLUP_ENABLE);
 255     S3C2440_GPIO_PULLUP (GPEUP, 7, GPIO_PULLUP_ENABLE);
 256     S3C2440_GPIO_PULLUP (GPEUP, 8, GPIO_PULLUP_ENABLE);
 257     S3C2440_GPIO_PULLUP (GPEUP, 9, GPIO_PULLUP_ENABLE);
 258     S3C2440_GPIO_PULLUP (GPEUP, 10, GPIO_PULLUP_ENABLE);
 259
 260     /* Enable special function for SDCMD, SDCLK and SDDAT pins */
 261     S3C2440_GPIO_CONFIG (GPECON, 5, GPIO_FUNCTION);
 262     S3C2440_GPIO_CONFIG (GPECON, 6, GPIO_FUNCTION);
 263     S3C2440_GPIO_CONFIG (GPECON, 7, GPIO_FUNCTION);
 264     S3C2440_GPIO_CONFIG (GPECON, 8, GPIO_FUNCTION);
 265     S3C2440_GPIO_CONFIG (GPECON, 9, GPIO_FUNCTION);
 266     S3C2440_GPIO_CONFIG (GPECON, 10, GPIO_FUNCTION);
 267
 268     /* Card Detect input */
 269     S3C2440_GPIO_CONFIG (GPGCON, 8, GPIO_INPUT);
 270     /* enable external irq 8-23 on the internal interrupt controller */
 271     INTMSK &= ~1<<5;
 272     /* enable GPG8 IRQ on the external interrupt controller */
 273     EINTMASK &= ~(1<<16);
 274
 275
 276     /* Write Protect input */
 277     S3C2440_GPIO_CONFIG (GPHCON, 8, GPIO_INPUT);
 278 /*****************************************************************************/
 279 #else
 280 #error Unsupported target
 281 #endif
 282 /*****************************************************************************/
 283
 284     /* About 400KHz for initial comms with card */
 285     SDIPRE   = PCLK / INITIAL_CLK - 1;
 286     /* Byte order=Type A (Little Endian), clock enable */
 287     SDICON   = S3C2410_SDICON_CLOCKTYPE;
 288     SDIFSTA  |= S3C2440_SDIFSTA_FIFORESET;
 289     SDIBSIZE = SD_BLOCK_SIZE;
 290     SDIDTIMER= 0x7fffff;      /* Set timeout count - max value */
 291
 292     /* Enable interupt on Data Finish or data transfer error */
 293     /* Clear pending source */
 294     SRCPND = SDI_MASK;
 295     INTPND = SDI_MASK;
 296
 297 #if 1
 298     /* Enable interrupt in controller */
 299     bitclr32(&INTMOD, SDI_MASK);
 300     bitclr32(&INTMSK, SDI_MASK);
 301
 302     SDIIMSK |= S3C2410_SDIIMSK_DATAFINISH
 303                | S3C2410_SDIIMSK_DATATIMEOUT
 304                | S3C2410_SDIIMSK_DATACRC
 305                | S3C2410_SDIIMSK_CRCSTATUS
 306                | S3C2410_SDIIMSK_FIFOFAIL
 307                ;
 308 #endif
 309 }
 310
 311 static bool send_cmd(const int card_no, const int cmd, const int arg,
 312                      const int flags, long *response)
 313 {
 314     bool ret;
 315     unsigned val, status;
 316     (void)card_no;
 317
 318 #ifdef SD_DEBUG
 319     get_regs (reg_copy);
 320 #endif
 321     /* A major bodge. For some reason a delay is required here */
 322     mci_delay();
 323     dbgprintf ("send_cmd: c=%3.3d a=%08x f=%02x  \n", cmd, arg, flags);
 324
 325 #ifdef SD_DEBUG
 326     get_regs (reg_copy2);
 327     dump_regs (reg_copy, reg_copy2);
 328 #endif
 329
 330 #if 0
 331     while (SDICSTA & S3C2410_SDICMDSTAT_XFERING)
 332         ; /* wait ?? */
 333 #endif
 334     /* set up new command */
 335
 336     if (flags & MCI_ARG)
 337         SDICARG = arg;
 338     else
 339         SDICARG = 0;
 340
 341     val = cmd | S3C2410_SDICMDCON_CMDSTART | S3C2410_SDICMDCON_SENDERHOST;
 342     if(flags & MCI_RESP)
 343     {
 344         val |= S3C2410_SDICMDCON_WAITRSP;
 345         if(flags & MCI_LONG_RESP)
 346             val |= S3C2410_SDICMDCON_LONGRSP;
 347     }
 348
 349     /* Clear command/data status flags */
 350     SDICSTA |= 0x0f << 9;
 351     SDIDSTA |= S3C2410_SDIDSTA_CLEAR_BITS;
 352
 353     /* Initiate the command */
 354     SDICCON = val;
 355
 356     if (flags & MCI_RESP)
 357     {
 358         /* wait for response or timeout */
 359         do
 360         {
 361             status = SDICSTA;
 362         } while ( (status & (S3C2410_SDICMDSTAT_RSPFIN |
 363                              S3C2410_SDICMDSTAT_CMDTIMEOUT) ) == 0);
 364         debug_r1(cmd);
 365         if (status & S3C2410_SDICMDSTAT_CMDTIMEOUT)
 366             ret = false;
 367         else if (status & (S3C2410_SDICMDSTAT_RSPFIN))
 368         {
 369             /* resp received */
 370             if(flags & MCI_LONG_RESP)
 371             {
 372                 /* store the response in reverse word order */
 373                 response[0] = SDIRSP3;
 374                 response[1] = SDIRSP2;
 375                 response[2] = SDIRSP1;
 376                 response[3] = SDIRSP0;
 377             }
 378             else
 379                 response[0] = SDIRSP0;
 380             ret = true;
 381         }
 382         else
 383             ret = true;
 384     }
 385     else
 386     {
 387         /* wait for command completion or timeout */
 388         do
 389         {
 390             status = SDICSTA;
 391         } while ( (status & (S3C2410_SDICMDSTAT_CMDSENT |
 392                           S3C2410_SDICMDSTAT_CMDTIMEOUT)) == 0);
 393         debug_r1(cmd);
 394         if (status & S3C2410_SDICMDSTAT_CMDTIMEOUT)
 395             ret = false;
 396         else
 397             ret = true;
 398     }
 399
 400     /* Clear Command status flags */
 401     SDICSTA |= 0x0f << 9;
 402
 403     mci_delay();
 404
 405     return ret;
 406 }
 407
 408 static int sd_init_card(const int card_no)
 409 {
 410     unsigned long temp_reg[4];
 411     unsigned long response;
 412     long init_timeout;
 413     bool sdhc;
 414     int i;
 415
 416     if(!send_cmd(card_no, SD_GO_IDLE_STATE, 0, MCI_NO_FLAGS, NULL))
 417         return -1;
 418
 419     mci_delay();
 420
 421     sdhc = false;
 422     if(send_cmd(card_no, SD_SEND_IF_COND, 0x1AA, MCI_RESP|MCI_ARG, &response))
 423         if((response & 0xFFF) == 0x1AA)
 424             sdhc = true;
 425
 426     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 427     init_timeout = current_tick + HZ;
 428
 429     do {
 430         /* timeout */
 431         if(current_tick > init_timeout)
 432             return -2;
 433
 434         /* app_cmd */
 435         if( !send_cmd(card_no, SD_APP_CMD, 0, MCI_RESP|MCI_ARG, &response) ||
 436             !(response & (1<<5)) )
 437         {
 438             return -3;
 439         }
 440
 441         /* acmd41 */
 442         if(!send_cmd(card_no, SD_APP_OP_COND, (sdhc ? 0x40FF8000 : (1<<23)),
 443                         MCI_RESP|MCI_ARG, &card_info[card_no].ocr))
 444         {
 445             return -4;
 446         }
 447
 448     } while(!(card_info[card_no].ocr & (1<<31)));
 449
 450     /* send CID */
 451     if(!send_cmd(card_no, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP|MCI_ARG,
 452                             temp_reg))
 453         return -5;
 454
 455     for(i=0; i<4; i++)
 456         card_info[card_no].cid[3-i] = temp_reg[i];
 457
 458     /* send RCA */
 459     if(!send_cmd(card_no, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP|MCI_ARG,
 460                 &card_info[card_no].rca))
 461         return -6;
 462
 463     /* send CSD */
 464     if(!send_cmd(card_no, SD_SEND_CSD, card_info[card_no].rca,
 465                  MCI_RESP|MCI_LONG_RESP|MCI_ARG, temp_reg))
 466         return -7;
 467
 468     for(i=0; i<4; i++)
 469         card_info[card_no].csd[3-i] = temp_reg[i];
 470
 471     sd_parse_csd(&card_info[card_no]);
 472
 473     if(!send_cmd(card_no, SD_SELECT_CARD, card_info[card_no].rca, MCI_ARG, NULL))
 474         return -9;
 475
 476     if(!send_cmd(card_no, SD_APP_CMD, card_info[card_no].rca, MCI_ARG, NULL))
 477         return -10;
 478
 479     if(!send_cmd(card_no, SD_SET_BUS_WIDTH, card_info[card_no].rca | 2, MCI_ARG, NULL))
 480         return -11;
 481
 482     if(!send_cmd(card_no, SD_SET_BLOCKLEN, card_info[card_no].blocksize, MCI_ARG,
 483                  NULL))
 484         return -12;
 485
 486     card_info[card_no].initialized = 1;
 487
 488     /* full speed for controller clock */
 489     SDIPRE   = PCLK / SD_CLK - 1;
 490     mci_delay();
 491
 492     return EC_OK;
 493 }
 494
 495 /*****************************************************************************
 496     Generic functions
 497  *****************************************************************************/
 498
 499 static inline bool card_detect_target(void)
 500 {
 501     /* TODO - use interrupt on change? */
 502 #ifdef MINI2440
 503     return (GPGDAT & SD_CD) == 0;
 504 #else
 505 #error Unsupported target
 506 #endif
 507 }
 508
 509
 510 /*****************************************************************************/
 511 #ifdef HAVE_HOTSWAP
 512
 513 static int sd1_oneshot_callback(struct timeout *tmo)
 514 {
 515     (void)tmo;
 516
 517     /* This is called only if the state was stable for 300ms - check state
 518      * and post appropriate event. */
 519     if (card_detect_target())
 520     {
 521         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
 522     }
 523     else
 524         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
 525     return 0;
 526 }
 527
 528 void EINT8_23(void)
 529 {
 530     static struct timeout sd1_oneshot;
 531     EINTPEND = (1<<16); /* ack irq on external, then internal irq controller */
 532     SRCPND = (1<<5);
 533     INTPND = (1<<5);
 534     /* add task to inform the system about the SD insertion
 535      * sanity check if it's still inserted after 300ms  */
 536     timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
 537 }
 538
 539 bool sd_removable(IF_MD_NONVOID(int card_no))
 540 {
 541 #ifndef HAVE_MULTIDRIVE
 542     const int card_no = 0;
 543 #endif
 544     dbgprintf ("sd_remov (hs) [%d] %d\n", card_no, card_no == CARD_NUM_SLOT );
 545     return (card_no == CARD_NUM_SLOT);
 546 }
 547
 548 bool sd_present(IF_MD_NONVOID(int card_no))
 549 {
 550 #ifdef HAVE_MULTIDRIVE
 551     (void)card_no;
 552 #endif
 553     dbgprintf ("sd_pres (hs) [%d] %d\n", card_no, card_detect_target());
 554     return card_detect_target();
 555 }
 556
 557 /*****************************************************************************/
 558 #else
 559
 560 bool sd_removable(IF_MD_NONVOID(int card_no))
 561 {
 562 #ifndef HAVE_MULTIDRIVE
 563     const int card_no = 0;
 564 #endif
 565     (void)card_no;
 566
 567     /* not applicable */
 568     dbgprintf ("sd_remov");
 569     return false;
 570 }
 571
 572 #endif /* HAVE_HOTSWAP */
 573 /*****************************************************************************/
 574
 575 static void sd_thread(void) NORETURN_ATTR;
 576 static void sd_thread(void)
 577 {
 578     struct queue_event ev;
 579
 580     /* TODO */
 581     while (1)
 582     {
 583         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 584         switch ( ev.id )
 585         {
 586 #ifdef HAVE_HOTSWAP
 587         case SYS_HOTSWAP_INSERTED:
 588         case SYS_HOTSWAP_EXTRACTED:
 589         {
 590             int success = 1;
 591             fat_lock();          /* lock-out FAT activity first -
 592                                     prevent deadlocking via disk_mount that
 593                                     would cause a reverse-order attempt with
 594                                     another thread */
 595             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 596                                     into driver that bypass the fat cache */
 597
 598             /* We now have exclusive control of fat cache and ata */
 599
 600             disk_unmount(0);     /* release "by force", ensure file
 601                                     descriptors aren't leaked and any busy
 602                                     ones are invalid if mounting */
 603
 604             /* Force card init for new card, re-init for re-inserted one or
 605              * clear if the last attempt to init failed with an error. */
 606             card_info[0].initialized = 0;
 607
 608             if (ev.id == SYS_HOTSWAP_INSERTED)
 609             {
 610                 /* FIXME: once sd_enabled is implement properly,
 611                  * reinitializing the controllers might be needed */
 612                 sd_enable(true);
 613                 if (success < 0) /* initialisation failed */
 614                     panicf("SD init failed : %d", success);
 615                 success = disk_mount(0); /* 0 if fail */
 616             }
 617
 618             /* notify the system about the changed filesystems
 619              */
 620             if (success)
 621                 queue_broadcast(SYS_FS_CHANGED, 0);
 622
 623             /* Access is now safe */
 624             mutex_unlock(&sd_mtx);
 625             fat_unlock();
 626             sd_enable(false);
 627         }
 628             break;
 629 #endif
 630         }
 631     }
 632 }
 633
 634 static int sd_wait_for_state(const int card_no, unsigned int state)
 635 {
 636     unsigned long response = 0;
 637     unsigned int timeout = HZ; /* ticks */
 638     long t = current_tick;
 639
 640     while (1)
 641     {
 642         long tick;
 643
 644         if(!send_cmd(card_no, SD_SEND_STATUS, card_info[card_no].rca,
 645                     MCI_RESP|MCI_ARG, &response))
 646             return -1;
 647
 648         if( (SD_R1_CURRENT_STATE(response) == state) )
 649             return 0;
 650
 651         if(TIME_AFTER(current_tick, t + timeout))
 652             return -2;
 653
 654         if (TIME_AFTER((tick = current_tick), next_yield))
 655         {
 656             yield();
 657             timeout += current_tick - tick;
 658             next_yield = tick + MIN_YIELD_PERIOD;
 659         }
 660     }
 661 }
 662
 663 static int sd_transfer_sectors(int card_no, unsigned long start,
 664                                int count, void* buf, const bool write)
 665 {
 666     int ret = EC_OK;
 667     unsigned loops = 0;
 668     struct dma_request request;
 669
 670     mutex_lock(&sd_mtx);
 671     sd_enable(true);
 672     set_leds(SD_ACTIVE_LED);
 673
 674 #ifdef HAVE_MULTIDRIVE
 675     curr_card = card_no;
 676 #endif
 677     if (card_info[card_no].initialized <= 0)
 678     {
 679         ret = sd_init_card(card_no);
 680         if (!(card_info[card_no].initialized))
 681             goto sd_transfer_error;
 682     }
 683
 684     last_disk_activity = current_tick;
 685
 686     ret = sd_wait_for_state(card_no, SD_TRAN);
 687     if (ret < 0)
 688     {
 689         ret -= 20;
 690         goto sd_transfer_error;
 691     }
 692
 693     dma_retain();
 694
 695     while(count)
 696     {
 697         /* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH
 698          * register, so we have to transfer maximum 127 sectors at a time. */
 699         unsigned int transfer = (count >= 128) ? 127 : count; /* sectors */
 700         void *dma_buf;
 701         const int cmd =
 702             write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 703         unsigned long start_addr = start;
 704
 705         dma_buf = aligned_buffer;
 706         if(transfer > UNALIGNED_NUM_SECTORS)
 707             transfer = UNALIGNED_NUM_SECTORS;
 708         if(write)
 709             memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 710
 711         /* Set start_addr to the correct unit (blocks or bytes) */
 712         if(!(card_info[card_no].ocr & SD_OCR_CARD_CAPACITY_STATUS))/* not SDHC */
 713             start_addr *= SD_BLOCK_SIZE;
 714
 715         /* TODO? */
 716         SDIFSTA = SDIFSTA | S3C2440_SDIFSTA_FIFORESET;
 717         SDIDCON = S3C2440_SDIDCON_DS_WORD   |
 718                   S3C2410_SDIDCON_BLOCKMODE | S3C2410_SDIDCON_WIDEBUS |
 719                   S3C2410_SDIDCON_DMAEN     |
 720                   S3C2440_SDIDCON_DATSTART  |
 721                   ( transfer << 0);
 722         if (write)
 723             SDIDCON |= S3C2410_SDIDCON_TXAFTERRESP | S3C2410_SDIDCON_XFER_TXSTART;
 724         else
 725             SDIDCON |= S3C2410_SDIDCON_RXAFTERCMD | S3C2410_SDIDCON_XFER_RXSTART;
 726
 727         SDIDSTA |= S3C2410_SDIDSTA_CLEAR_BITS;  /* needed to clear int  */
 728         SRCPND = SDI_MASK;
 729         INTPND = SDI_MASK;
 730
 731         /* Initiate read/write command */
 732         if(!send_cmd(card_no, cmd, start_addr, MCI_ARG | MCI_RESP, NULL))
 733         {
 734             ret -= 3*20;
 735             goto sd_transfer_error;
 736         }
 737
 738         if(write)
 739         {
 740             request.source_addr    = dma_buf;
 741             request.source_control = DISRCC_LOC_AHB | DISRCC_INC_AUTO;
 742             request.dest_addr      = &SDIDAT_LLE;
 743             request.dest_control   = DISRCC_LOC_APB | DISRCC_INC_FIXED;
 744             request.count          = transfer * SD_BLOCK_SIZE / sizeof(long);
 745             request.source_map     = DMA_SRC_MAP_SDI;
 746             request.control        = DCON_DMD_HS | DCON_SYNC_APB |
 747                                      DCON_HW_SEL |
 748                                      DCON_NO_RELOAD | DCON_DSZ_WORD;
 749             request.callback       = NULL;
 750
 751             dma_enable_channel(0, &request);
 752         }
 753         else
 754         {
 755             request.source_addr    = &SDIDAT_LLE;
 756             request.source_control = DISRCC_LOC_APB | DISRCC_INC_FIXED;
 757             request.dest_addr      = dma_buf;
 758             request.dest_control   = DISRCC_LOC_AHB | DISRCC_INC_AUTO;
 759             request.count          = transfer * SD_BLOCK_SIZE / sizeof(long);
 760             request.source_map     = DMA_SRC_MAP_SDI;
 761             request.control        = DCON_DMD_HS | DCON_SYNC_APB |
 762                                      DCON_HW_SEL |
 763                                      DCON_NO_RELOAD | DCON_DSZ_WORD;
 764             request.callback       = NULL;
 765
 766             dma_enable_channel(0, &request);
 767         }
 768
 769 #if 0
 770         /* FIXME : we should check if the timeouts calculated from the card's
 771          * CSD are lower, and use them if it is the case
 772          * Note : the OF doesn't seem to use them anyway */
 773         MCI_DATA_TIMER(drive) = write ?
 774                 SD_MAX_WRITE_TIMEOUT : SD_MAX_READ_TIMEOUT;
 775         MCI_DATA_LENGTH(drive) = transfer * card_info[drive].blocksize;
 776         MCI_DATA_CTRL(drive) =  (1<<0) /* enable */                     |
 777                                 (!write<<1) /* transfer direction */    |
 778                                 (1<<3) /* DMA */                        |
 779                                 (9<<4) /* 2^9 = 512 */ ;
 780 #endif
 781
 782         semaphore_wait(&transfer_completion_signal, 100 /*TIMEOUT_BLOCK*/);
 783
 784         /* wait for DMA to finish */
 785         while (DSTAT0 & DSTAT_STAT_BUSY)
 786             ;
 787
 788 #if 0
 789         status = SDIDSTA;
 790         while ((status & (S3C2410_SDIDSTA_DATATIMEOUT|S3C2410_SDIDSTA_XFERFINISH)) == 0)
 791         {
 792             status = SDIDSTA;
 793         }
 794         dbgprintf("%x \n", status);
 795 #endif
 796         if( transfer_error[card_no] & S3C2410_SDIDSTA_XFERFINISH )
 797         {
 798             if(!write)
 799                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 800             buf += transfer * SD_BLOCK_SIZE;
 801             start += transfer;
 802             count -= transfer;
 803             loops = 0;  /* reset errors counter */
 804         }
 805         else
 806         {
 807             dbgprintf ("SD transfer error : 0x%x\n", transfer_error[card_no]);
 808
 809             if(loops++ > MAX_TRANSFER_ERRORS)
 810             {
 811                 led_flash(LED1|LED2, LED3|LED4);
 812                 /* panicf("SD transfer error : 0x%x", transfer_error[card_no]); */
 813             }
 814         }
 815
 816         last_disk_activity = current_tick;
 817
 818         if(!send_cmd(card_no, SD_STOP_TRANSMISSION, 0, MCI_RESP, NULL))
 819         {
 820             ret = -4*20;
 821             goto sd_transfer_error;
 822         }
 823
 824 #if 0
 825         ret = sd_wait_for_state(card_no, SD_TRAN);
 826         if (ret < 0)
 827         {
 828             ret -= 5*20;
 829             goto sd_transfer_error;
 830         }
 831 #endif
 832     }
 833
 834     ret = EC_OK;
 835
 836 sd_transfer_error:
 837
 838     dma_release();
 839
 840     clear_leds(SD_ACTIVE_LED);
 841     sd_enable(false);
 842
 843     if (ret)    /* error */
 844         card_info[card_no].initialized = 0;
 845
 846     mutex_unlock(&sd_mtx);
 847     return ret;
 848 }
 849
 850 int sd_read_sectors(IF_MD2(int card_no,) unsigned long start, int incount,
 851                      void* inbuf)
 852 {
 853     int ret;
 854
 855 #ifdef HAVE_MULTIDRIVE
 856     dbgprintf ("sd_read %d %x %d\n", card_no, start, incount);
 857 #else
 858     dbgprintf ("sd_read %x %d\n", start, incount);
 859 #endif
 860 #ifdef HAVE_HOTSWAP_STORAGE_AS_MAIN
 861     if (!card_detect_target())
 862         ret = 0; /* assume success */
 863     else
 864 #endif
 865         ret = sd_transfer_sectors(card_no, start, incount, inbuf, false);
 866     dbgprintf ("sd_read, ret=%d\n", ret);
 867     return ret;
 868 }
 869
 870 /*****************************************************************************/
 871 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 872                       const void* outbuf)
 873 {
 874 #ifdef BOOTLOADER /* we don't need write support in bootloader */
 875 #ifdef HAVE_MULTIDRIVE
 876     (void) drive;
 877 #endif
 878     (void) start;
 879     (void) count;
 880     (void) outbuf;
 881     return -1;
 882 #else
 883 #ifdef HAVE_MULTIDRIVE
 884     dbgprintf ("sd_write %d %x %d\n", drive, start, count);
 885 #else
 886     dbgprintf ("sd_write %x %d\n", start, count);
 887 #endif
 888 #ifdef HAVE_HOTSWAP_STORAGE_AS_MAIN
 889     if (!card_detect_target())
 890         return 0; /* assume success */
 891     else
 892 #endif
 893         return sd_transfer_sectors(drive, start, count, (void*)outbuf, true);
 894 #endif
 895 }
 896 /*****************************************************************************/
 897
 898 void sd_enable(bool on)
 899 {
 900     dbgprintf ("sd_enable %d\n", on);
 901     /* TODO: enable/disable SDI clock */
 902
 903     if (sd_enabled == on)
 904         return; /* nothing to do */
 905     if (on)
 906     {
 907         sd_enabled = true;
 908     }
 909     else
 910     {
 911         sd_enabled = false;
 912     }
 913 }
 914
 915 int sd_init(void)
 916 {
 917     int ret = EC_OK;
 918     dbgprintf ("\n==============================\n");
 919     dbgprintf ("             sd_init\n");
 920     dbgprintf ("==============================\n");
 921
 922     init_sdi_controller (0);
 923 #ifndef BOOTLOADER
 924     sd_enabled = true;
 925     sd_enable(false);
 926 #endif
 927     semaphore_init(&transfer_completion_signal, 1, 0);
 928     /* init mutex */
 929     mutex_init(&sd_mtx);
 930     queue_init(&sd_queue, true);
 931     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 932             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 933
 934     uncached_buffer = UNCACHED_ADDR(&aligned_buffer[0]);
 935
 936 #ifdef HAVE_HOTSWAP
 937     /*
 938      * prepare detecting of SD insertion (not extraction) */
 939     unsigned long for_extint = EXTINT2;
 940     unsigned long for_gpgcon = GPGCON;
 941     for_extint &= ~0x7;
 942 #ifdef HAVE_HOTSWAP_STORAGE_AS_MAIN
 943     for_extint |=  0x2; /* detect falling edge only (0 means SD inserted) */
 944 #else
 945     for_extint |=  0x3; /* detect both, raising and falling, edges */
 946 #endif
 947     for_gpgcon &= ~(0x3<<16);
 948     for_gpgcon |=  (0x2<<16); /* enable interrupt on pin 8 */
 949     EXTINT2 = for_extint;
 950     GPGCON = for_gpgcon;
 951 #endif
 952
 953     initialized = true;
 954     return ret;
 955 }
 956
 957 long sd_last_disk_activity(void)
 958 {
 959     return last_disk_activity;
 960 }
 961
 962 tCardInfo *card_get_info_target(int card_no)
 963 {
 964     return &card_info[card_no];
 965 }
 966
 967 /*****************************************************************************/
 968 #ifdef CONFIG_STORAGE_MULTI
 969
 970 int sd_num_drives(int first_drive)
 971 {
 972     dbgprintf ("sd_num_drv");
 973 #if 0
 974     /* Store which logical drive number(s) we have been assigned */
 975     sd_first_drive = first_drive;
 976 #endif
 977
 978     return NUM_CARDS;
 979 }
 980
 981 void sd_sleepnow(void)
 982 {
 983 }
 984
 985 bool sd_disk_is_active(void)
 986 {
 987     return false;
 988 }
 989
 990 int sd_soft_reset(void)
 991 {
 992     return 0;
 993 }
 994
 995 int sd_spinup_time(void)
 996 {
 997     return 0;
 998 }
 999
1000 #endif /* CONFIG_STORAGE_MULTI */
1001 /*****************************************************************************/
1002