firmware/target/arm/imx233/ssp-imx233.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2011 by amaury Pouly
  11  *
  12  * Based on Rockbox iriver bootloader by Linus Nielsen Feltzing
  13  * and the ipodlinux bootloader by Daniel Palffy and Bernard Leach
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * as published by the Free Software Foundation; either version 2
  18  * of the License, or (at your option) any later version.
  19  *
  20  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  21  * KIND, either express or implied.
  22  *
  23  ****************************************************************************/
  24 #include "system.h"
  25 #include "kernel.h"
  26 #include "ssp-imx233.h"
  27 #include "clkctrl-imx233.h"
  28 #include "pinctrl-imx233.h"
  29 #include "dma-imx233.h"
  30
  31 /* Used for DMA */
  32 struct ssp_dma_command_t
  33 {
  34     struct apb_dma_command_t dma;
  35     /* PIO words */
  36     uint32_t ctrl0;
  37     uint32_t cmd0;
  38     uint32_t cmd1;
  39 };
  40
  41 static bool ssp_in_use[2];
  42 static int ssp_nr_in_use = 0;
  43 static struct mutex ssp_mutex[2];
  44 static struct semaphore ssp_sema[2];
  45 static struct ssp_dma_command_t ssp_dma_cmd[2];
  46 static uint32_t ssp_bus_width[2];
  47 static unsigned ssp_log_block_size[2];
  48 static ssp_detect_cb_t ssp_detect_cb[2];
  49
  50 void INT_SSP(int ssp)
  51 {
  52     /* reset dma channel on error */
  53     if(imx233_dma_is_channel_error_irq(APB_SSP(ssp)))
  54         imx233_dma_reset_channel(APB_SSP(ssp));
  55     /* clear irq flags */
  56     imx233_dma_clear_channel_interrupt(APB_SSP(ssp));
  57     semaphore_release(&ssp_sema[ssp - 1]);
  58 }
  59
  60 void INT_SSP1_DMA(void)
  61 {
  62     INT_SSP(1);
  63 }
  64
  65 void INT_SSP2_DMA(void)
  66 {
  67     INT_SSP(2);
  68 }
  69
  70 void INT_SSP1_ERROR(void)
  71 {
  72     panicf("ssp1 error");
  73 }
  74
  75 void INT_SSP2_ERROR(void)
  76 {
  77     panicf("ssp2 error");
  78 }
  79
  80 void imx233_ssp_init(void)
  81 {
  82     /* power down */
  83     __REG_SET(HW_SSP_CTRL0(1)) = __BLOCK_CLKGATE;
  84     __REG_SET(HW_SSP_CTRL0(2)) = __BLOCK_CLKGATE;
  85
  86     ssp_nr_in_use = 0;
  87     semaphore_init(&ssp_sema[0], 1, 0);
  88     semaphore_init(&ssp_sema[1], 1, 0);
  89     mutex_init(&ssp_mutex[0]);
  90     mutex_init(&ssp_mutex[1]);
  91     ssp_bus_width[0] = ssp_bus_width[1] = HW_SSP_CTRL0__BUS_WIDTH__ONE_BIT;
  92 }
  93
  94 void imx233_ssp_start(int ssp)
  95 {
  96     if(ssp_in_use[ssp - 1])
  97         return;
  98     ssp_in_use[ssp - 1] = true;
  99     /* Gate block */
 100     imx233_reset_block(&HW_SSP_CTRL0(ssp));
 101     /* Gate dma channel */
 102     imx233_dma_clkgate_channel(APB_SSP(ssp), true);
 103     /* If first block to start, start SSP clock */
 104     if(ssp_nr_in_use == 0)
 105     {
 106         /** 2.3.1: the clk_ssp maximum frequency is 102.858 MHz */
 107         /* fracdiv = 18 => clk_io = pll = 480Mhz
 108          * intdiv = 5 => clk_ssp = 96Mhz */
 109         imx233_set_fractional_divisor(CLK_IO, 18);
 110         imx233_enable_clock(CLK_SSP, false);
 111         imx233_set_clock_divisor(CLK_SSP, 5);
 112         imx233_set_bypass_pll(CLK_SSP, false); /* use IO */
 113         imx233_enable_clock(CLK_SSP, true);
 114     }
 115     ssp_nr_in_use++;
 116 }
 117
 118 void imx233_ssp_stop(int ssp)
 119 {
 120     if(!ssp_in_use[ssp - 1])
 121         return;
 122     ssp_in_use[ssp - 1] = false;
 123     /* Gate off */
 124     __REG_SET(HW_SSP_CTRL0(ssp)) = __BLOCK_CLKGATE;
 125     /* Gate off dma */
 126     imx233_dma_clkgate_channel(APB_SSP(ssp), false);
 127     /* If last block to stop, stop SSP clock */
 128     ssp_nr_in_use--;
 129     if(ssp_nr_in_use == 0)
 130     {
 131         imx233_enable_clock(CLK_SSP, false);
 132         imx233_set_fractional_divisor(CLK_IO, 0);
 133     }
 134 }
 135
 136 void imx233_ssp_softreset(int ssp)
 137 {
 138     imx233_reset_block(&HW_SSP_CTRL0(ssp));
 139 }
 140
 141 void imx233_ssp_set_timings(int ssp, int divide, int rate, int timeout)
 142 {
 143     HW_SSP_TIMING(ssp) = divide << HW_SSP_TIMING__CLOCK_DIVIDE_BP | rate |
 144         timeout << HW_SSP_TIMING__CLOCK_TIMEOUT_BP;
 145 }
 146
 147 void imx233_ssp_setup_ssp1_sd_mmc_pins(bool enable_pullups, unsigned bus_width,
 148     unsigned drive_strength, bool use_alt)
 149 {
 150     /* SSP_{CMD,SCK} */
 151     imx233_set_pin_drive_strength(2, 0, drive_strength);
 152     imx233_set_pin_drive_strength(2, 6, drive_strength);
 153     imx233_set_pin_function(2, 0, PINCTRL_FUNCTION_MAIN);
 154     imx233_set_pin_function(2, 6, PINCTRL_FUNCTION_MAIN);
 155     imx233_enable_pin_pullup(2, 0, enable_pullups);
 156     /* SSP_DATA{0-3} */
 157     for(unsigned i = 0; i < MIN(bus_width, 4); i++)
 158     {
 159         imx233_set_pin_drive_strength(2, 2 + i, drive_strength);
 160         imx233_set_pin_function(2, 2 + i, PINCTRL_FUNCTION_MAIN);
 161         imx233_enable_pin_pullup(2, 2 + i, enable_pullups);
 162     }
 163
 164     /* SSP_DATA{4-7} */
 165     for(unsigned i = 4; i < bus_width; i++)
 166     {
 167         if(use_alt)
 168         {
 169             imx233_set_pin_drive_strength(0, 22 + i, drive_strength);
 170             imx233_set_pin_function(0, 22 + i, PINCTRL_FUNCTION_ALT2);
 171             imx233_enable_pin_pullup(0, 22 + i, enable_pullups);
 172         }
 173         else
 174         {
 175             imx233_set_pin_drive_strength(0, 4 + i, drive_strength);
 176             imx233_set_pin_function(0, 4 + i, PINCTRL_FUNCTION_ALT2);
 177             imx233_enable_pin_pullup(0, 4 + i, enable_pullups);
 178         }
 179     }
 180 }
 181
 182 void imx233_ssp_setup_ssp2_sd_mmc_pins(bool enable_pullups, unsigned bus_width,
 183     unsigned drive_strength)
 184 {
 185     /* SSP_{CMD,SCK} */
 186     imx233_set_pin_drive_strength(0, 20, drive_strength);
 187     imx233_set_pin_drive_strength(0, 24, drive_strength);
 188     imx233_set_pin_function(0, 20, PINCTRL_FUNCTION_ALT2);
 189     imx233_set_pin_function(0, 24, PINCTRL_FUNCTION_ALT2);
 190     imx233_enable_pin_pullup(0, 20, enable_pullups);
 191     /* SSP_DATA{0-7}*/
 192     for(unsigned i = 0; i < bus_width; i++)
 193     {
 194         imx233_set_pin_drive_strength(0, i, drive_strength);
 195         imx233_set_pin_function(0, i, PINCTRL_FUNCTION_ALT2);
 196         imx233_enable_pin_pullup(0, i, enable_pullups);
 197     }
 198
 199     imx233_enable_gpio_output_mask(0, 0x11000ff, false);
 200     imx233_set_gpio_output_mask(0, 0x11000ff, false);
 201 }
 202
 203 void imx233_ssp_set_mode(int ssp, unsigned mode)
 204 {
 205     switch(mode)
 206     {
 207         case HW_SSP_CTRL1__SSP_MODE__SD_MMC:
 208             /* clear mode and word length */
 209             __REG_CLR(HW_SSP_CTRL1(ssp)) =
 210                 HW_SSP_CTRL1__SSP_MODE_BM | HW_SSP_CTRL1__WORD_LENGTH_BM;
 211             /* set mode, set word length to 8-bit, polarity and enable dma */
 212             __REG_SET(HW_SSP_CTRL1(ssp)) = mode |
 213                 HW_SSP_CTRL1__WORD_LENGTH__EIGHT_BITS << HW_SSP_CTRL1__WORD_LENGTH_BP |
 214                 HW_SSP_CTRL1__POLARITY | HW_SSP_CTRL1__DMA_ENABLE;
 215             break;
 216         default: return;
 217     }
 218 }
 219
 220 void imx233_ssp_set_bus_width(int ssp, unsigned width)
 221 {
 222     switch(width)
 223     {
 224         case 1: ssp_bus_width[ssp - 1] = HW_SSP_CTRL0__BUS_WIDTH__ONE_BIT; break;
 225         case 4: ssp_bus_width[ssp - 1] = HW_SSP_CTRL0__BUS_WIDTH__FOUR_BIT; break;
 226         case 8: ssp_bus_width[ssp - 1] = HW_SSP_CTRL0__BUS_WIDTH__EIGHT_BIT; break;
 227     }
 228 }
 229
 230 void imx233_ssp_set_block_size(int ssp, unsigned log_block_size)
 231 {
 232     ssp_log_block_size[ssp - 1] = log_block_size;
 233 }
 234
 235 enum imx233_ssp_error_t imx233_ssp_sd_mmc_transfer(int ssp, uint8_t cmd,
 236     uint32_t cmd_arg, enum imx233_ssp_resp_t resp, void *buffer, unsigned block_count,
 237     bool wait4irq, bool read, uint32_t *resp_ptr)
 238 {
 239     mutex_lock(&ssp_mutex[ssp - 1]);
 240     /* Enable all interrupts */
 241     imx233_enable_interrupt(INT_SRC_SSP_DMA(ssp), true);
 242     imx233_dma_enable_channel_interrupt(APB_SSP(ssp), true);
 243
 244     unsigned xfer_size = block_count * (1 << ssp_log_block_size[ssp - 1]);
 245
 246     ssp_dma_cmd[ssp - 1].cmd0 = cmd | HW_SSP_CMD0__APPEND_8CYC |
 247         ssp_log_block_size[ssp - 1] << HW_SSP_CMD0__BLOCK_SIZE_BP |
 248         (block_count - 1) << HW_SSP_CMD0__BLOCK_COUNT_BP;
 249     ssp_dma_cmd[ssp - 1].cmd1 = cmd_arg;
 250     /* setup all flags and run */
 251     ssp_dma_cmd[ssp - 1].ctrl0 = xfer_size | HW_SSP_CTRL0__ENABLE |
 252         (buffer ?  0 : HW_SSP_CTRL0__IGNORE_CRC) |
 253         (wait4irq ? HW_SSP_CTRL0__WAIT_FOR_IRQ : 0) |
 254         (resp != SSP_NO_RESP ? HW_SSP_CTRL0__GET_RESP : 0) |
 255         (resp == SSP_LONG_RESP ? HW_SSP_CTRL0__LONG_RESP : 0) |
 256         (ssp_bus_width[ssp - 1] << HW_SSP_CTRL0__BUS_WIDTH_BP) |
 257         (buffer ? HW_SSP_CTRL0__DATA_XFER : 0) |
 258         (read ? HW_SSP_CTRL0__READ : 0);
 259     /* setup the dma parameters */
 260     ssp_dma_cmd[ssp - 1].dma.buffer = buffer;
 261     ssp_dma_cmd[ssp - 1].dma.next = NULL;
 262     ssp_dma_cmd[ssp - 1].dma.cmd =
 263         (buffer == NULL ? HW_APB_CHx_CMD__COMMAND__NO_XFER :
 264          read ? HW_APB_CHx_CMD__COMMAND__WRITE : HW_APB_CHx_CMD__COMMAND__READ) |
 265         HW_APB_CHx_CMD__IRQONCMPLT | HW_APB_CHx_CMD__SEMAPHORE |
 266         HW_APB_CHx_CMD__WAIT4ENDCMD |
 267         (3 << HW_APB_CHx_CMD__CMDWORDS_BP) |
 268         (xfer_size << HW_APB_CHx_CMD__XFER_COUNT_BP);
 269
 270     __REG_CLR(HW_SSP_CTRL1(ssp)) = HW_SSP_CTRL1__ALL_IRQ;
 271     imx233_dma_reset_channel(APB_SSP(ssp));
 272     imx233_dma_start_command(APB_SSP(ssp), &ssp_dma_cmd[ssp - 1].dma);
 273
 274     /* the SSP hardware already has a timeout but we never know; 1 sec is a maximum
 275      * for all operations */
 276     enum imx233_ssp_error_t ret;
 277
 278     if(semaphore_wait(&ssp_sema[ssp - 1], HZ) == OBJ_WAIT_TIMEDOUT)
 279     {
 280         imx233_dma_reset_channel(APB_SSP(ssp));
 281         ret = SSP_TIMEOUT;
 282     }
 283     else if((HW_SSP_CTRL1(ssp) & HW_SSP_CTRL1__ALL_IRQ) == 0)
 284         ret =  SSP_SUCCESS;
 285     else if(HW_SSP_CTRL1(ssp) & (HW_SSP_CTRL1__RESP_TIMEOUT_IRQ |
 286             HW_SSP_CTRL1__DATA_TIMEOUT_IRQ | HW_SSP_CTRL1__RECV_TIMEOUT_IRQ))
 287         ret = SSP_TIMEOUT;
 288     else
 289         ret = SSP_ERROR;
 290
 291     if(resp_ptr != NULL)
 292     {
 293         if(resp != SSP_NO_RESP)
 294             *resp_ptr++ = HW_SSP_SDRESP0(ssp);
 295         if(resp == SSP_LONG_RESP)
 296         {
 297             *resp_ptr++ = HW_SSP_SDRESP1(ssp);
 298             *resp_ptr++ = HW_SSP_SDRESP2(ssp);
 299             *resp_ptr++ = HW_SSP_SDRESP3(ssp);
 300         }
 301     }
 302     mutex_unlock(&ssp_mutex[ssp - 1]);
 303     return ret;
 304 }
 305
 306 void imx233_ssp_sd_mmc_power_up_sequence(int ssp)
 307 {
 308     __REG_CLR(HW_SSP_CMD0(ssp)) = HW_SSP_CMD0__SLOW_CLKING_EN;
 309     __REG_SET(HW_SSP_CMD0(ssp)) = HW_SSP_CMD0__CONT_CLKING_EN;
 310     mdelay(1);
 311     __REG_CLR(HW_SSP_CMD0(ssp)) = HW_SSP_CMD0__CONT_CLKING_EN;
 312 }
 313
 314 static int ssp_detect_oneshot_callback(int ssp)
 315 {
 316     if(ssp_detect_cb[ssp - 1])
 317         ssp_detect_cb[ssp - 1](ssp);
 318
 319     return 0;
 320 }
 321
 322 static int ssp1_detect_oneshot_callback(struct timeout *tmo)
 323 {
 324     (void) tmo;
 325     return ssp_detect_oneshot_callback(1);
 326 }
 327
 328 static int ssp2_detect_oneshot_callback(struct timeout *tmo)
 329 {
 330     (void) tmo;
 331     return ssp_detect_oneshot_callback(2);
 332 }
 333
 334 static void detect_irq(int bank, int pin)
 335 {
 336     static struct timeout ssp1_detect_oneshot;
 337     static struct timeout ssp2_detect_oneshot;
 338     if(bank == 2 && pin == 1)
 339         timeout_register(&ssp1_detect_oneshot, ssp1_detect_oneshot_callback, (3*HZ/10), 0);
 340     else if(bank == 0 && pin == 19)
 341         timeout_register(&ssp2_detect_oneshot, ssp2_detect_oneshot_callback, (3*HZ/10), 0);
 342 }
 343
 344 void imx233_ssp_sdmmc_setup_detect(int ssp, bool enable, ssp_detect_cb_t fn, bool first_time)
 345 {
 346     int bank = ssp == 1 ? 2 : 0;
 347     int pin = ssp == 1 ? 1 : 19;
 348     ssp_detect_cb[ssp - 1] = fn;
 349     if(enable)
 350     {
 351         imx233_set_pin_function(bank, pin, PINCTRL_FUNCTION_GPIO);
 352         imx233_enable_gpio_output(bank, pin, false);
 353     }
 354     if(first_time && imx233_ssp_sdmmc_detect(ssp))
 355         detect_irq(bank, pin);
 356     imx233_setup_pin_irq(bank, pin, enable, true, !imx233_ssp_sdmmc_detect(ssp), detect_irq);
 357 }
 358
 359 bool imx233_ssp_sdmmc_detect(int ssp)
 360 {
 361     return !!(HW_SSP_STATUS(ssp) & HW_SSP_STATUS__CARD_DETECT);
 362 }