firmware/target/arm/ata-nand-telechips.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2008 Rob Purchase
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "nand.h"
  22 #include "ata-nand-target.h"
  23 #include "system.h"
  24 #include <string.h>
  25 #include "led.h"
  26 #include "panic.h"
  27 #include "nand_id.h"
  28 #include "storage.h"
  29
  30 #define SECTOR_SIZE 512
  31
  32 /* ECC on read is implemented on the assumption that MLC-style 4-bit correction
  33    is always used regardless of NAND chip type. This assumption is true for at
  34    least D2 (MLC) and M200 (SLC). */
  35 #define USE_ECC_CORRECTION
  36
  37 /* for compatibility */
  38 int ata_spinup_time = 0;
  39
  40 long last_disk_activity = -1;
  41
  42 /** static, private data **/
  43 static bool initialized = false;
  44
  45 static long next_yield = 0;
  46 #define MIN_YIELD_PERIOD 1000
  47
  48 static struct mutex ata_mtx SHAREDBSS_ATTR;
  49
  50 #if defined(COWON_D2) || defined(IAUDIO_7)
  51 #define FTL_V2
  52 #define MAX_WRITE_CACHES    8
  53 #else
  54 #define FTL_V1
  55 #define MAX_WRITE_CACHES    4
  56 #endif
  57
  58 /* Sector type identifiers - main data area */
  59
  60 #define SECTYPE_MAIN_LPT           0x12
  61 #define SECTYPE_MAIN_DATA          0x13
  62 #define SECTYPE_MAIN_RANDOM_CACHE  0x15
  63 #define SECTYPE_MAIN_INPLACE_CACHE 0x17
  64
  65 /* We don't touch the hidden area at all - these are for reference */
  66 #define SECTYPE_HIDDEN_LPT           0x22
  67 #define SECTYPE_HIDDEN_DATA          0x23
  68 #define SECTYPE_HIDDEN_RANDOM_CACHE  0x25
  69 #define SECTYPE_HIDDEN_INPLACE_CACHE 0x27
  70
  71 #ifdef FTL_V1
  72 #define SECTYPE_FIRMWARE 0x40
  73 #else
  74 #define SECTYPE_FIRMWARE 0xE0
  75 #endif
  76
  77 /* Offsets to data within sector's spare area */
  78
  79 #define OFF_CACHE_PAGE_LOBYTE 2
  80 #define OFF_CACHE_PAGE_HIBYTE 3
  81 #define OFF_SECTOR_TYPE       4
  82
  83 #ifdef FTL_V2
  84 #define OFF_LOG_SEG_LOBYTE    7
  85 #define OFF_LOG_SEG_HIBYTE    6
  86 #else
  87 #define OFF_LOG_SEG_LOBYTE    6
  88 #define OFF_LOG_SEG_HIBYTE    7
  89 #endif
  90
  91 /* Chip characteristics, initialised by nand_get_chip_info() */
  92
  93 static struct nand_info* nand_data = NULL;
  94
  95 static int total_banks         = 0;
  96 static int pages_per_bank      = 0;
  97 static int sectors_per_page    = 0;
  98 static int bytes_per_segment   = 0;
  99 static int sectors_per_segment = 0;
 100 static int segments_per_bank   = 0;
 101 static int pages_per_segment   = 0;
 102
 103 /* Maximum values for static buffers */
 104
 105 #define MAX_PAGE_SIZE          4096
 106 #define MAX_SPARE_SIZE         128
 107 #define MAX_BLOCKS_PER_BANK    8192
 108 #define MAX_PAGES_PER_BLOCK    128
 109 #define MAX_BANKS              4
 110 #define MAX_BLOCKS_PER_SEGMENT 4
 111
 112 #define MAX_SEGMENTS (MAX_BLOCKS_PER_BANK * MAX_BANKS / MAX_BLOCKS_PER_SEGMENT)
 113
 114 /* Logical/Physical translation table */
 115
 116 struct lpt_entry
 117 {
 118     short bank;
 119     short phys_segment;
 120 };
 121 #ifdef BOOTLOADER
 122 static struct lpt_entry lpt_lookup[MAX_SEGMENTS];
 123 #else
 124 /* core_alloc()'d in nand_init() when the correct size has been determined */
 125 #include "core_alloc.h"
 126 static int lpt_handle;
 127 #endif
 128
 129 /* Write Caches */
 130
 131 struct write_cache
 132 {
 133     short log_segment;
 134     short inplace_bank;
 135     short inplace_phys_segment;
 136     short inplace_pages_used;
 137     short random_bank;
 138     short random_phys_segment;
 139     short page_map[MAX_PAGES_PER_BLOCK * MAX_BLOCKS_PER_SEGMENT];
 140 };
 141 static struct write_cache write_caches[MAX_WRITE_CACHES];
 142
 143 static int write_caches_in_use = 0;
 144
 145
 146 /* Conversion functions */
 147
 148 static int phys_segment_to_page_addr(int phys_segment, int page_in_seg)
 149 {
 150     int page_addr = 0;
 151
 152     switch (nand_data->planes)
 153     {
 154         case 1:
 155         {
 156             page_addr = (phys_segment * nand_data->pages_per_block);
 157             break;
 158         }
 159
 160         case 2:
 161         case 4:
 162         {
 163             page_addr = phys_segment * nand_data->pages_per_block * 2;
 164
 165             if (page_in_seg & 1)
 166             {
 167                 /* Data is located in block+1 */
 168                 page_addr += nand_data->pages_per_block;
 169             }
 170
 171             if (nand_data->planes == 4 && page_in_seg & 2)
 172             {
 173                 /* Data is located in 2nd half of bank */
 174                 page_addr +=
 175                     (nand_data->blocks_per_bank/2) * nand_data->pages_per_block;
 176             }
 177
 178             break;
 179         }
 180     }
 181
 182     page_addr += (page_in_seg / nand_data->planes);
 183
 184     return page_addr;
 185 }
 186
 187
 188 /* NAND physical access functions */
 189
 190 static void nand_chip_select(int bank)
 191 {
 192     if (bank == -1)
 193     {
 194         /* Disable both chip selects */
 195         NAND_GPIO_CLEAR(CS_GPIO_BIT);
 196         NFC_CTRL |= NFC_CS0 | NFC_CS1;
 197     }
 198     else
 199     {
 200         /* NFC chip select */
 201         if (bank & 1)
 202         {
 203             NFC_CTRL &= ~NFC_CS0;
 204             NFC_CTRL |= NFC_CS1;
 205         }
 206         else
 207         {
 208             NFC_CTRL |= NFC_CS0;
 209             NFC_CTRL &= ~NFC_CS1;
 210         }
 211
 212         /* Secondary chip select */
 213         if (bank & 2)
 214             NAND_GPIO_SET(CS_GPIO_BIT);
 215         else
 216             NAND_GPIO_CLEAR(CS_GPIO_BIT);
 217     }
 218 }
 219
 220
 221 static void nand_read_id(int bank, unsigned char* id_buf)
 222 {
 223     int i;
 224
 225     /* Enable NFC bus clock */
 226     BCLKCTR |= DEV_NAND;
 227
 228     /* Reset NAND controller */
 229     NFC_RST = 0;
 230
 231     /* Set slow cycle timings since the chip is as yet unidentified */
 232     NFC_CTRL = (NFC_CTRL &~0xFFF) | 0x353;
 233
 234     nand_chip_select(bank);
 235
 236     /* Set write protect */
 237     NAND_GPIO_CLEAR(WE_GPIO_BIT);
 238
 239     /* Reset command */
 240     NFC_CMD = 0xFF;
 241
 242     /* Set 8-bit data width */
 243     NFC_CTRL &= ~NFC_16BIT;
 244
 245     /* Read ID command, single address cycle */
 246     NFC_CMD   = 0x90;
 247     NFC_SADDR = 0x00;
 248
 249     /* Read the 5 chip ID bytes */
 250     for (i = 0; i < 5; i++)
 251     {
 252         id_buf[i] = NFC_SDATA & 0xFF;
 253     }
 254
 255     nand_chip_select(-1);
 256
 257     /* Disable NFC bus clock */
 258     BCLKCTR &= ~DEV_NAND;
 259 }
 260
 261
 262 static void nand_read_uid(int bank, unsigned int* uid_buf)
 263 {
 264     int i;
 265
 266     /* Enable NFC bus clock */
 267     BCLKCTR |= DEV_NAND;
 268
 269     /* Set cycle timing (stp = 1, pw = 3, hold = 1) */
 270     NFC_CTRL = (NFC_CTRL &~0xFFF) | 0x131;
 271
 272     nand_chip_select(bank);
 273
 274     /* Set write protect */
 275     NAND_GPIO_CLEAR(WE_GPIO_BIT);
 276
 277     /* Set 8-bit data width */
 278     NFC_CTRL &= ~NFC_16BIT;
 279
 280     /* Undocumented (SAMSUNG specific?) commands set the chip into a
 281        special mode allowing a normally-hidden UID block to be read. */
 282     NFC_CMD = 0x30;
 283     NFC_CMD = 0x65;
 284
 285     /* Read command */
 286     NFC_CMD = 0x00;
 287
 288     /* Write row/column address */
 289     for (i = 0; i < nand_data->col_cycles; i++) NFC_SADDR = 0;
 290     for (i = 0; i < nand_data->row_cycles; i++) NFC_SADDR = 0;
 291
 292     /* End of read */
 293     NFC_CMD = 0x30;
 294
 295     /* Wait until complete */
 296     while (!(NFC_CTRL & NFC_READY)) {};
 297
 298     /* Copy data to buffer (data repeats after 8 words) */
 299     for (i = 0; i < 8; i++)
 300     {
 301         uid_buf[i] = NFC_WDATA;
 302     }
 303
 304     /* Reset the chip back to normal mode */
 305     NFC_CMD = 0xFF;
 306
 307     nand_chip_select(-1);
 308
 309     /* Disable NFC bus clock */
 310     BCLKCTR &= ~DEV_NAND;
 311 }
 312
 313
 314 static void nand_setup_read(int bank, int row, int column)
 315 {
 316     int i;
 317
 318     /* Enable NFC bus clock */
 319     BCLKCTR |= DEV_NAND;
 320
 321     /* Set cycle timing (stp = 1, pw = 3, hold = 1) */
 322     NFC_CTRL = (NFC_CTRL &~0xFFF) | 0x131;
 323
 324     nand_chip_select(bank);
 325
 326     /* Set write protect */
 327     NAND_GPIO_CLEAR(WE_GPIO_BIT);
 328
 329     /* Set 8-bit data width */
 330     NFC_CTRL &= ~NFC_16BIT;
 331
 332     /* Read command */
 333     NFC_CMD = 0x00;
 334
 335     /* Write column address */
 336     for (i = 0; i < nand_data->col_cycles; i++)
 337     {
 338         NFC_SADDR = column & 0xFF;
 339         column = column >> 8;
 340     }
 341
 342     /* Write row address */
 343     for (i = 0; i < nand_data->row_cycles; i++)
 344     {
 345         NFC_SADDR = row & 0xFF;
 346         row = row >> 8;
 347     }
 348
 349     /* End of read command */
 350     NFC_CMD = 0x30;
 351
 352     /* Wait until complete */
 353     while (!(NFC_CTRL & NFC_READY)) {};
 354 }
 355
 356
 357 static void nand_end_read(void)
 358 {
 359     nand_chip_select(-1);
 360
 361     /* Disable NFC bus clock */
 362     BCLKCTR &= ~DEV_NAND;
 363 }
 364
 365
 366 static void nand_read_raw(int bank, int row, int column, int size, void* buf)
 367 {
 368     int i;
 369
 370     nand_setup_read(bank, row, column);
 371
 372     /* Read data into page buffer */
 373     if (((unsigned int)buf & 3) || (size & 3))
 374     {
 375         /* Use byte copy since either the buffer or size are not word-aligned */
 376         /* TODO: Byte copy only where necessary (use words for mid-section) */
 377         for (i = 0; i < size; i++)
 378         {
 379             ((unsigned char*)buf)[i] = NFC_SDATA;
 380         }
 381     }
 382     else
 383     {
 384         /* Use 4-byte copy as buffer and size are both word-aligned */
 385         for (i = 0; i < (size/4); i++)
 386         {
 387             ((unsigned int*)buf)[i] = NFC_WDATA;
 388         }
 389     }
 390
 391     nand_end_read();
 392 }
 393
 394
 395 static void nand_get_chip_info(void)
 396 {
 397     unsigned char manuf_id;
 398     unsigned char id_buf[8];
 399
 400     /* Read chip id from bank 0 */
 401     nand_read_id(0, id_buf);
 402
 403     manuf_id = id_buf[0];
 404
 405     /* Identify the chip geometry */
 406     nand_data = nand_identify(id_buf);
 407
 408     if (nand_data == NULL)
 409     {
 410         panicf("Unknown NAND: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
 411                 id_buf[0],id_buf[1],id_buf[2],id_buf[3],id_buf[4]);
 412     }
 413
 414     pages_per_bank = nand_data->blocks_per_bank * nand_data->pages_per_block;
 415
 416     segments_per_bank = nand_data->blocks_per_bank / nand_data->planes;
 417
 418     bytes_per_segment = nand_data->page_size * nand_data->pages_per_block
 419         * nand_data->planes;
 420
 421     sectors_per_page = nand_data->page_size / SECTOR_SIZE;
 422
 423     sectors_per_segment = bytes_per_segment / SECTOR_SIZE;
 424
 425     pages_per_segment = sectors_per_segment / sectors_per_page;
 426
 427     /* Establish how many banks are present */
 428     nand_read_id(1, id_buf);
 429
 430     if (id_buf[0] == manuf_id)
 431     {
 432         /* Bank 1 is populated, now check if banks 2/3 are valid */
 433         nand_read_id(2, id_buf);
 434
 435         if (id_buf[0] == manuf_id)
 436         {
 437             /* Bank 2 returned matching id - check if 2/3 are shadowing 0/1 */
 438             unsigned int uid_buf0[8];
 439             unsigned int uid_buf2[8];
 440
 441             nand_read_uid(0, uid_buf0);
 442             nand_read_uid(2, uid_buf2);
 443
 444             if (memcmp(uid_buf0, uid_buf2, 32) == 0)
 445             {
 446                 /* UIDs match, assume banks 2/3 are shadowing 0/1 */
 447                 total_banks = 2;
 448             }
 449             else
 450             {
 451                 /* UIDs differ, assume banks 2/3 are valid */
 452                 total_banks = 4;
 453             }
 454         }
 455         else
 456         {
 457             /* Bank 2 returned differing id - assume 2/3 are junk */
 458             total_banks = 2;
 459         }
 460     }
 461     else
 462     {
 463         /* Bank 1 returned differing id - assume it is junk */
 464         total_banks = 1;
 465     }
 466
 467     /*
 468        Sanity checks:
 469        1. "BMP" tag at block 0, page 0, offset <page_size> [always present]
 470        2. On most D2s, <page_size>+3 is 'M' and <page_size>+4 is no. of banks.
 471           This is not present on some older players (formatted with early FW?)
 472      */
 473
 474     nand_read_raw(0, 0,                 /* bank, page */
 475                   nand_data->page_size, /* offset */
 476                   8, id_buf);           /* length, dest */
 477
 478     if (strncmp(id_buf, "BMP", 3)) panicf("BMP tag not present");
 479
 480     if (id_buf[3] == 'M')
 481     {
 482         if (id_buf[4] != total_banks) panicf("BMPM total_banks mismatch");
 483     }
 484 }
 485
 486
 487 static bool nand_read_sector_of_phys_page(int bank, int page,
 488                                           int sector, void* buf)
 489 {
 490     bool ret = true;
 491     int i;
 492     int page_offset = sector * (SECTOR_SIZE + 16);
 493
 494 #ifdef USE_ECC_CORRECTION
 495     unsigned long spare_buf[4];
 496
 497     /* Set up the ECC controller to monitor reads from NFC_WDATA */
 498     BCLKCTR |= DEV_ECC;
 499     ECC_BASE = (unsigned long)&NFC_WDATA;
 500     ECC_CTRL |= ECC_M4EN;
 501     ECC_CTRL &= ~ECC_ENC;
 502     ECC_CTRL |= ECC_READY;
 503     ECC_CLR = 0;
 504 #endif
 505
 506     /* Read the sector data */
 507     nand_setup_read(bank, page, page_offset);
 508
 509     /* Read data into page buffer */
 510     if ((unsigned int)buf & 3)
 511     {
 512         /* If unaligned, read into a temporary buffer and copy to destination.
 513            This way, reads are always done through NFC_WDATA - otherwise they
 514            would not be 'seen' by the ECC controller. */
 515         static char temp_buf[SECTOR_SIZE];
 516
 517         unsigned int* ptr = (unsigned int*) temp_buf;
 518
 519         for (i = 0; i < (SECTOR_SIZE/4); i++)
 520         {
 521             *ptr++ = NFC_WDATA;
 522         }
 523
 524         memcpy(buf, temp_buf, SECTOR_SIZE);
 525     }
 526     else
 527     {
 528         /* Use straight word copy as buffer and size are both word-aligned */
 529         unsigned int* ptr = (unsigned int*) buf;
 530
 531         for (i = 0; i < (SECTOR_SIZE/4); i++)
 532         {
 533             *ptr++ = NFC_WDATA;
 534         }
 535     }
 536
 537 #ifdef USE_ECC_CORRECTION
 538     /* Stop monitoring before we read the OOB data */
 539     ECC_CTRL &= ~ECC_M4EN;
 540     BCLKCTR &= ~DEV_ECC;
 541
 542     /* Read a further 4 words (sector OOB data) */
 543     spare_buf[0] = NFC_WDATA;
 544     spare_buf[1] = NFC_WDATA;
 545     spare_buf[2] = NFC_WDATA;
 546     spare_buf[3] = NFC_WDATA;
 547
 548     /* Calculate MLC4 ECC using bytes 0,1,8-15 */
 549     BCLKCTR |= DEV_ECC;
 550     ECC_CTRL |= ECC_M4EN;
 551
 552     MLC_ECC0W = *(unsigned short*)spare_buf;
 553     MLC_ECC1W = spare_buf[2];
 554     MLC_ECC2W = spare_buf[3];
 555
 556     while (!(ECC_CTRL & ECC_READY)) {};
 557
 558     int errors = ECC_ERR_NUM & 7;
 559
 560     switch (errors)
 561     {
 562         case 4:     /* nothing to correct */
 563             break;
 564
 565         case 7:     /* fail, can't correct */
 566             ret = false;
 567             break;
 568
 569         default:    /* between 1 and 4 errors */
 570         {
 571             int i;
 572             unsigned char* char_buf = (unsigned char*)buf;
 573
 574             for (i = 0; i < errors + 1; i++)
 575             {
 576                 int offset = 0x207 - ECC_ERRADDR(i);
 577                 char_buf[offset] ^= ECC_ERRDATA(i);
 578             }
 579         }
 580     }
 581
 582     /* Disable ECC block */
 583     ECC_CTRL &= ~ECC_M4EN;
 584     BCLKCTR &= ~DEV_ECC;
 585 #endif
 586
 587     nand_end_read();
 588
 589     return ret;
 590 }
 591
 592
 593 static bool nand_read_sector_of_phys_segment(int bank, int phys_segment,
 594                                              int page_in_seg, int sector,
 595                                              void* buf)
 596 {
 597     int page_addr = phys_segment_to_page_addr(phys_segment,
 598                                               page_in_seg);
 599
 600     return nand_read_sector_of_phys_page(bank, page_addr, sector, buf);
 601 }
 602
 603
 604 static bool nand_read_sector_of_logical_segment(int log_segment, int sector,
 605                                                 void* buf)
 606 {
 607     int page_in_segment = sector / sectors_per_page;
 608     int sector_in_page  = sector % sectors_per_page;
 609
 610 #ifndef BOOTLOADER
 611     struct lpt_entry* lpt_lookup = core_get_data(lpt_handle);
 612 #endif
 613     int bank = lpt_lookup[log_segment].bank;
 614     int phys_segment = lpt_lookup[log_segment].phys_segment;
 615
 616     /* Check if any of the write caches refer to this segment/page.
 617        If present we need to read the cached page instead. */
 618
 619     int cache_num = 0;
 620     bool found = false;
 621
 622     while (!found && cache_num < write_caches_in_use)
 623     {
 624         if (write_caches[cache_num].log_segment == log_segment)
 625         {
 626             if (write_caches[cache_num].page_map[page_in_segment] != -1)
 627             {
 628                 /* data is located in random pages cache */
 629                 found = true;
 630
 631                 bank = write_caches[cache_num].random_bank;
 632                 phys_segment = write_caches[cache_num].random_phys_segment;
 633
 634                 page_in_segment =
 635                     write_caches[cache_num].page_map[page_in_segment];
 636             }
 637             else if (write_caches[cache_num].inplace_pages_used != -1 &&
 638                      write_caches[cache_num].inplace_pages_used > page_in_segment)
 639             {
 640                 /* data is located in in-place pages cache */
 641                 found = true;
 642
 643                 bank = write_caches[cache_num].inplace_bank;
 644                 phys_segment = write_caches[cache_num].inplace_phys_segment;
 645             }
 646         }
 647         cache_num++;
 648     }
 649
 650     return nand_read_sector_of_phys_segment(bank, phys_segment,
 651                                             page_in_segment,
 652                                             sector_in_page, buf);
 653 }
 654
 655
 656 /* Miscellaneous helper functions */
 657
 658 static inline unsigned char get_sector_type(char* spare_buf)
 659 {
 660     return spare_buf[OFF_SECTOR_TYPE];
 661 }
 662
 663 static inline unsigned short get_log_segment_id(int phys_seg, char* spare_buf)
 664 {
 665     (void)phys_seg;
 666
 667     return ((spare_buf[OFF_LOG_SEG_HIBYTE] << 8) |
 668              spare_buf[OFF_LOG_SEG_LOBYTE])
 669 #if defined(FTL_V1)
 670             + 984 * (phys_seg / 1024)
 671 #endif
 672             ;
 673 }
 674
 675 static inline unsigned short get_cached_page_id(char* spare_buf)
 676 {
 677     return (spare_buf[OFF_CACHE_PAGE_HIBYTE] << 8) |
 678             spare_buf[OFF_CACHE_PAGE_LOBYTE];
 679 }
 680
 681 static int find_write_cache(int log_segment)
 682 {
 683     int i;
 684
 685     for (i = 0; i < write_caches_in_use; i++)
 686         if (write_caches[i].log_segment == log_segment)
 687             return i;
 688
 689     return -1;
 690 }
 691
 692
 693 static void read_random_writes_cache(int bank, int phys_segment)
 694 {
 695     int page = 0;
 696     short log_segment;
 697     unsigned char spare_buf[16];
 698
 699     nand_read_raw(bank, phys_segment_to_page_addr(phys_segment, page),
 700                   SECTOR_SIZE, /* offset to first sector's spare */
 701                   16, spare_buf);
 702
 703     log_segment = get_log_segment_id(phys_segment, spare_buf);
 704
 705     if (log_segment == -1)
 706         return;
 707
 708     /* Find which cache this is related to */
 709     int cache_no = find_write_cache(log_segment);
 710
 711     if (cache_no == -1)
 712     {
 713         if (write_caches_in_use < MAX_WRITE_CACHES)
 714         {
 715             cache_no = write_caches_in_use;
 716             write_caches_in_use++;
 717         }
 718         else
 719         {
 720             panicf("Max NAND write caches reached");
 721         }
 722     }
 723
 724     write_caches[cache_no].log_segment = log_segment;
 725     write_caches[cache_no].random_bank = bank;
 726     write_caches[cache_no].random_phys_segment = phys_segment;
 727
 728 #ifndef FTL_V1
 729     /* Loop over each page in the phys segment (from page 1 onwards).
 730        Read spare for 1st sector, store location of page in array. */
 731     for (page = 1;
 732          page < (nand_data->pages_per_block * nand_data->planes);
 733          page++)
 734     {
 735         unsigned short cached_page;
 736
 737         nand_read_raw(bank, phys_segment_to_page_addr(phys_segment, page),
 738                       SECTOR_SIZE, /* offset to first sector's spare */
 739                       16, spare_buf);
 740
 741         cached_page = get_cached_page_id(spare_buf);
 742
 743         if (cached_page != 0xFFFF)
 744             write_caches[cache_no].page_map[cached_page] = page;
 745     }
 746 #endif /* !FTL_V1 */
 747 }
 748
 749
 750 static void read_inplace_writes_cache(int bank, int phys_segment)
 751 {
 752     int page = 0;
 753     short log_segment;
 754     unsigned char spare_buf[16];
 755
 756     nand_read_raw(bank, phys_segment_to_page_addr(phys_segment, page),
 757                   SECTOR_SIZE, /* offset to first sector's spare */
 758                   16, spare_buf);
 759
 760     log_segment = get_log_segment_id(phys_segment, spare_buf);
 761
 762     if (log_segment == -1)
 763         return;
 764
 765     /* Find which cache this is related to */
 766     int cache_no = find_write_cache(log_segment);
 767
 768     if (cache_no == -1)
 769     {
 770         if (write_caches_in_use < MAX_WRITE_CACHES)
 771         {
 772             cache_no = write_caches_in_use;
 773             write_caches_in_use++;
 774         }
 775         else
 776         {
 777             panicf("Max NAND write caches reached");
 778         }
 779     }
 780
 781     write_caches[cache_no].log_segment = log_segment;
 782
 783     /* Find how many pages have been written to the new segment */
 784     while (log_segment != -1 &&
 785            page < (nand_data->pages_per_block * nand_data->planes) - 1)
 786     {
 787         page++;
 788         nand_read_raw(bank, phys_segment_to_page_addr(phys_segment, page),
 789                       SECTOR_SIZE, 16, spare_buf);
 790
 791         log_segment = get_log_segment_id(phys_segment, spare_buf);
 792     }
 793
 794     if (page != 0)
 795     {
 796         write_caches[cache_no].inplace_bank = bank;
 797         write_caches[cache_no].inplace_phys_segment = phys_segment;
 798         write_caches[cache_no].inplace_pages_used = page;
 799     }
 800 }
 801
 802
 803 int nand_read_sectors(IF_MD2(int drive,) unsigned long start, int incount,
 804                      void* inbuf)
 805 {
 806 #ifdef HAVE_MULTIDRIVE
 807     (void)drive; /* unused for now */
 808 #endif
 809
 810     int ret = 0;
 811
 812     mutex_lock(&ata_mtx);
 813
 814     led(true);
 815
 816     while (incount > 0)
 817     {
 818         int done = 0;
 819         int segment = start / sectors_per_segment;
 820         int secmod = start % sectors_per_segment;
 821
 822         while (incount > 0 && secmod < sectors_per_segment)
 823         {
 824             if (!nand_read_sector_of_logical_segment(segment, secmod, inbuf))
 825             {
 826                 ret = -1;
 827                 goto nand_read_error;
 828             }
 829
 830             if (TIME_AFTER(USEC_TIMER, next_yield))
 831             {
 832                 next_yield = USEC_TIMER + MIN_YIELD_PERIOD;
 833                 yield();
 834             }
 835
 836             inbuf += SECTOR_SIZE;
 837             incount--;
 838             secmod++;
 839             done++;
 840         }
 841
 842         if (done < 0)
 843         {
 844             ret = -1;
 845             goto nand_read_error;
 846         }
 847         start += done;
 848     }
 849
 850 nand_read_error:
 851
 852     mutex_unlock(&ata_mtx);
 853     led(false);
 854
 855     return ret;
 856 }
 857
 858 int nand_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 859                       const void* outbuf)
 860 {
 861 #ifdef HAVE_MULTIDRIVE
 862     (void)drive; /* unused for now */
 863 #endif
 864
 865     /* TODO: Learn more about TNFTL and implement this one day... */
 866     (void)start;
 867     (void)count;
 868     (void)outbuf;
 869     return -1;
 870 }
 871
 872 #ifdef HAVE_STORAGE_FLUSH
 873 int nand_flush(void)
 874 {
 875     return 0;
 876 }
 877 #endif
 878
 879 #ifdef STORAGE_GET_INFO
 880 void nand_get_info(IF_MD2(int drive,) struct storage_info *info)
 881 {
 882 #ifdef HAVE_MULTIDRIVE
 883     (void)drive; /* unused for now */
 884 #endif
 885
 886     /* firmware version */
 887     info->revision="0.00";
 888
 889     info->vendor="Rockbox";
 890     info->product="Internal Storage";
 891
 892     /* blocks count */
 893     info->num_sectors = sectors_per_segment * segments_per_bank * total_banks;
 894     info->sector_size = SECTOR_SIZE;
 895 }
 896 #endif
 897
 898
 899 int nand_init(void)
 900 {
 901     int bank, phys_segment, lptbuf_size;
 902     unsigned char spare_buf[16];
 903
 904     if (initialized) return 0;
 905
 906     mutex_init(&ata_mtx);
 907
 908 #ifdef CPU_TCC77X
 909     CSCFG2 = 0x018a8010 | tcc77x_cscfg_bw(TCC77X_CSCFG_BW8);
 910
 911     GPIOC_FUNC &= ~(CS_GPIO_BIT | WE_GPIO_BIT);
 912     GPIOC_FUNC |= 0x1;
 913 #endif
 914
 915     /* Set GPIO direction for chip select & write protect */
 916     NAND_GPIO_OUT_EN(CS_GPIO_BIT | WE_GPIO_BIT);
 917
 918     /* Get chip characteristics and number of banks */
 919     nand_get_chip_info();
 920
 921 #ifndef BOOTLOADER
 922     /* Use chip info to allocate the correct size LPT buffer */
 923     lptbuf_size = sizeof(struct lpt_entry) * segments_per_bank * total_banks;
 924     lpt_handle = core_alloc("lpt lookup", lptbuf_size);
 925     struct lpt_entry* lpt_lookup = core_get_data(lpt_handle);
 926 #else
 927     /* Use a static array in the bootloader */
 928     lptbuf_size = sizeof(lpt_lookup);
 929 #endif
 930
 931     memset(lpt_lookup, 0xff, lptbuf_size);
 932     memset(write_caches, 0xff, sizeof(write_caches));
 933
 934     write_caches_in_use = 0;
 935
 936     /* Scan banks to build up block translation table */
 937     for (bank = 0; bank < total_banks; bank++)
 938     {
 939         for (phys_segment = 0; phys_segment < segments_per_bank; phys_segment++)
 940         {
 941             /* Read spare bytes from first sector of each segment */
 942             nand_read_raw(bank, phys_segment_to_page_addr(phys_segment, 0),
 943                           SECTOR_SIZE, /* offset */
 944                           16, spare_buf);
 945
 946             int type = get_sector_type(spare_buf);
 947
 948 #ifdef FTL_V2
 949             if (type == SECTYPE_MAIN_INPLACE_CACHE)
 950             {
 951                 /* Since this type of segment is written to sequentially, its
 952                    job is complete if the final page has been written. In this
 953                    case we need to treat it as a normal data segment. */
 954                 nand_read_raw(bank, phys_segment_to_page_addr
 955                                 (phys_segment, pages_per_segment - 1),
 956                               SECTOR_SIZE, 16, spare_buf);
 957
 958                 if (get_sector_type(spare_buf) != 0xff)
 959                 {
 960                     type = SECTYPE_MAIN_DATA;
 961                 }
 962             }
 963 #endif
 964
 965             switch (type)
 966             {
 967                 case SECTYPE_MAIN_DATA:
 968                 {
 969                     /* Main data area segment */
 970                     unsigned short log_segment =
 971                         get_log_segment_id(phys_segment, spare_buf);
 972
 973                     if (log_segment < segments_per_bank * total_banks)
 974                     {
 975 #ifndef BOOTLOADER
 976                         lpt_lookup = core_get_data(lpt_handle);
 977 #endif
 978                         if (lpt_lookup[log_segment].bank == -1 ||
 979                             lpt_lookup[log_segment].phys_segment == -1)
 980                         {
 981                             lpt_lookup[log_segment].bank = bank;
 982                             lpt_lookup[log_segment].phys_segment = phys_segment;
 983                         }
 984                         else
 985                         {
 986                             //panicf("duplicate data segment 0x%x!", log_segment);
 987                         }
 988                     }
 989                     break;
 990                 }
 991
 992                 case SECTYPE_MAIN_RANDOM_CACHE:
 993                 {
 994                     /* Newly-written random page data (Main data area) */
 995                     read_random_writes_cache(bank, phys_segment);
 996                     break;
 997                 }
 998
 999                 case SECTYPE_MAIN_INPLACE_CACHE:
1000                 {
1001                     /* Newly-written sequential page data (Main data area) */
1002                     read_inplace_writes_cache(bank, phys_segment);
1003                     break;
1004                 }
1005             }
1006         }
1007     }
1008
1009     initialized = true;
1010
1011     return 0;
1012 }
1013
1014 long nand_last_disk_activity(void)
1015 {
1016     return last_disk_activity;
1017 }
1018
1019 void nand_sleep(void)
1020 {
1021 }
1022
1023 void nand_spin(void)
1024 {
1025 }
1026
1027 void nand_spindown(int seconds)
1028 {
1029     (void)seconds;
1030 }
1031
1032 #ifdef CONFIG_STORAGE_MULTI
1033
1034 int nand_num_drives(int first_drive)
1035 {
1036     /* We don't care which logical drive number we have been assigned */
1037     (void)first_drive;
1038
1039     return 1;
1040 }
1041
1042 void nand_sleepnow(void)
1043 {
1044 }
1045
1046 bool nand_disk_is_active(void)
1047 {
1048     return false;
1049 }
1050
1051 int nand_soft_reset(void)
1052 {
1053     return 0;
1054 }
1055
1056 int nand_spinup_time(void)
1057 {
1058     return 0;
1059 }
1060
1061 void nand_enable(bool onoff)
1062 {
1063     (void)onoff;
1064 }
1065
1066 #endif /* CONFIG_STORAGE_MULTI */