firmware/target/arm/imx233/dma-imx233.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2011 by Amaury Pouly
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef __DMA_IMX233_H__
  22 #define __DMA_IMX233_H__
  23
  24 #include "cpu.h"
  25 #include "system.h"
  26 #include "system-target.h"
  27
  28 /********
  29  * APHB *
  30  ********/
  31
  32 #define HW_APBH_BASE        0x80004000
  33
  34 /* APHB channels */
  35 #define HW_APBH_SSP(ssp)    ssp
  36 #define HW_APBH_NAND(dev)   (4 + (ssp))
  37
  38 #define HW_APBH_CTRL0       (*(volatile uint32_t *)(HW_APBH_BASE + 0x0))
  39 #define HW_APBH_CTRL0__FREEZE_CHANNEL(i)    (1 << (i))
  40 #define HW_APBH_CTRL0__CLKGATE_CHANNEL(i)   (1 << ((i) + 8))
  41 #define HW_APBH_CTRL0__RESET_CHANNEL(i)     (1 << ((i) + 16))
  42 #define HW_APBH_CTRL0__APB_BURST4_EN        (1 << 28)
  43 #define HW_APBH_CTRL0__APB_BURST8_EN        (1 << 29)
  44
  45 #define HW_APBH_CTRL1       (*(volatile uint32_t *)(HW_APBH_BASE + 0x10))
  46 #define HW_APBH_CTRL1__CHx_CMDCMPLT_IRQ(i)      (1 << (i))
  47 #define HW_APBH_CTRL1__CHx_CMDCMPLT_IRQ_EN(i)   (1 << ((i) + 16))
  48
  49 #define HW_APBH_CTRL2       (*(volatile uint32_t *)(HW_APBH_BASE + 0x20))
  50 #define HW_APBH_CTRL2__CHx_ERROR_IRQ(i)         (1 << (i))
  51 #define HW_APBH_CTRL2__CHx_ERROR_STATUS(i)      (1 << ((i) + 16))
  52
  53 #define HW_APBH_CHx_CURCMDAR(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x40 + 0x70 * (i)))
  54
  55 #define HW_APBH_CHx_NXTCMDAR(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x50 + 0x70 * (i)))
  56
  57 #define HW_APBH_CHx_CMD(i)      (*(volatile uint32_t *)(HW_APBH_BASE + 0x60 + 0x70 * (i)))
  58
  59 #define HW_APBH_CHx_BAR(i)      (*(volatile uint32_t *)(HW_APBH_BASE + 0x70 + 0x70 * (i)))
  60
  61 #define HW_APBH_CHx_SEMA(i)     (*(volatile uint32_t *)(HW_APBH_BASE + 0x80 + 0x70 * (i)))
  62
  63 #define HW_APBH_CHx_DEBUG1(i)   (*(volatile uint32_t *)(HW_APBH_BASE + 0x90 + 0x70 * (i)))
  64
  65 #define HW_APBH_CHx_DEBUG2(i)   (*(volatile uint32_t *)(HW_APBH_BASE + 0xa0 + 0x70 * (i)))
  66 #define HW_APBH_CHx_DEBUG2__AHB_BYTES_BP    0
  67 #define HW_APBH_CHx_DEBUG2__AHB_BYTES_BM    0xffff
  68 #define HW_APBH_CHx_DEBUG2__APB_BYTES_BP    16
  69 #define HW_APBH_CHx_DEBUG2__APB_BYTES_BM    0xffff0000
  70
  71 /********
  72  * APHX *
  73  ********/
  74
  75 /* APHX channels */
  76 #define HW_APBX_AUDIO_ADC   0
  77 #define HW_APBX_AUDIO_DAC   1
  78 #define HW_APBX_I2C         3
  79
  80 #define HW_APBX_BASE        0x80024000
  81
  82 #define HW_APBX_CTRL0       (*(volatile uint32_t *)(HW_APBX_BASE + 0x0))
  83
  84 #define HW_APBX_CTRL1       (*(volatile uint32_t *)(HW_APBX_BASE + 0x10))
  85 #define HW_APBX_CTRL1__CHx_CMDCMPLT_IRQ(i)      (1 << (i))
  86 #define HW_APBX_CTRL1__CHx_CMDCMPLT_IRQ_EN(i)   (1 << ((i) + 16))
  87
  88 #define HW_APBX_CTRL2       (*(volatile uint32_t *)(HW_APBX_BASE + 0x20))
  89 #define HW_APBX_CTRL2__CHx_ERROR_IRQ(i)         (1 << (i))
  90 #define HW_APBX_CTRL2__CHx_ERROR_STATUS(i)      (1 << ((i) + 16))
  91
  92 #define HW_APBX_CHANNEL_CTRL    (*(volatile uint32_t *)(HW_APBX_BASE + 0x30))
  93 #define HW_APBX_CHANNEL_CTRL__FREEZE_CHANNEL(i) (1 << (i))
  94 #define HW_APBX_CHANNEL_CTRL__RESET_CHANNEL(i)  (1 << ((i) + 16))
  95
  96 #define HW_APBX_CHx_CURCMDAR(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x100 + (i) * 0x70))
  97
  98 #define HW_APBX_CHx_NXTCMDAR(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x110 + (i) * 0x70))
  99
 100 #define HW_APBX_CHx_CMD(i)      (*(volatile uint32_t *)(HW_APBX_BASE + 0x120 + (i) * 0x70))
 101
 102 #define HW_APBX_CHx_BAR(i)      (*(volatile uint32_t *)(HW_APBX_BASE + 0x130 + (i) * 0x70))
 103
 104 #define HW_APBX_CHx_SEMA(i)     (*(volatile uint32_t *)(HW_APBX_BASE + 0x140 + (i) * 0x70))
 105
 106 #define HW_APBX_CHx_DEBUG1(i)   (*(volatile uint32_t *)(HW_APBX_BASE + 0x150 + (i) * 0x70))
 107
 108 #define HW_APBX_CHx_DEBUG2(i)   (*(volatile uint32_t *)(HW_APBX_BASE + 0x160 + (i) * 0x70))
 109 #define HW_APBX_CHx_DEBUG2__AHB_BYTES_BP    0
 110 #define HW_APBX_CHx_DEBUG2__AHB_BYTES_BM    0xffff
 111 #define HW_APBX_CHx_DEBUG2__APB_BYTES_BP    16
 112 #define HW_APBX_CHx_DEBUG2__APB_BYTES_BM    0xffff0000
 113
 114 /**********
 115  * COMMON *
 116  **********/
 117
 118 /* DMA structures should be cache aligned and be padded so that their size
 119  * is a multiple of a cache line size. Otherwise some nasty side effects
 120  * could occur with adjacents data fields.
 121  * The same apply to DMA buffers for the same reasons */
 122 struct apb_dma_command_t
 123 {
 124     struct apb_dma_command_t *next;
 125     uint32_t cmd;
 126     void *buffer;
 127     /* PIO words follow */
 128 } __attribute__((packed));
 129
 130 #define DMA_INFO_CURCMDADDR (1 << 0)
 131 #define DMA_INFO_NXTCMDADDR (1 << 1)
 132 #define DMA_INFO_CMD        (1 << 2)
 133 #define DMA_INFO_BAR        (1 << 3)
 134 #define DMA_INFO_APB_BYTES  (1 << 4)
 135 #define DMA_INFO_AHB_BYTES  (1 << 5)
 136 #define DMA_INFO_FREEZED    (1 << 6)
 137 #define DMA_INFO_GATED      (1 << 7)
 138 #define DMA_INFO_INTERRUPT  (1 << 8)
 139 #define DMA_INFO_ALL        0x1ff
 140
 141 struct imx233_dma_info_t
 142 {
 143     unsigned long cur_cmd_addr;
 144     unsigned long nxt_cmd_addr;
 145     unsigned long cmd;
 146     unsigned long bar;
 147     unsigned apb_bytes;
 148     unsigned ahb_bytes;
 149     bool freezed;
 150     bool gated;
 151     bool int_enabled;
 152     bool int_cmdcomplt;
 153     bool int_error;
 154     int nr_unaligned;
 155 };
 156
 157 #define APBH_DMA_CHANNEL(i)     i
 158 #define APBX_DMA_CHANNEL(i)     ((i) | 0x10)
 159 #define APB_IS_APBX_CHANNEL(x)  ((x) & 0x10)
 160 #define APB_GET_DMA_CHANNEL(x)  ((x) & 0xf)
 161
 162 #define APB_SSP(ssp)        APBH_DMA_CHANNEL(HW_APBH_SSP(ssp))
 163 #define APB_AUDIO_ADC       APBX_DMA_CHANNEL(HW_APBX_AUDIO_ADC)
 164 #define APB_AUDIO_DAC       APBX_DMA_CHANNEL(HW_APBX_AUDIO_DAC)
 165 #define APB_I2C             APBX_DMA_CHANNEL(HW_APBX_I2C)
 166 #define APB_NAND(dev)       APBH_DMA_CHANNEL(HW_APBH_NAND(dev))
 167
 168 #define HW_APB_CHx_CMD__COMMAND_BM         0x3
 169 #define HW_APB_CHx_CMD__COMMAND_BP         0
 170 #define HW_APB_CHx_CMD__COMMAND__NO_XFER   0
 171 #define HW_APB_CHx_CMD__COMMAND__WRITE     1
 172 #define HW_APB_CHx_CMD__COMMAND__READ      2
 173 #define HW_APB_CHx_CMD__COMMAND__SENSE     3
 174 #define HW_APB_CHx_CMD__CHAIN              (1 << 2)
 175 #define HW_APB_CHx_CMD__IRQONCMPLT         (1 << 3)
 176 /* those two are only available on APHB */
 177 #define HW_APBH_CHx_CMD__NANDLOCK          (1 << 4)
 178 #define HW_APBH_CHx_CMD__NANDWAIT4READY    (1 << 5)
 179 #define HW_APB_CHx_CMD__SEMAPHORE          (1 << 6)
 180 #define HW_APB_CHx_CMD__WAIT4ENDCMD        (1 << 7)
 181 /* An errata advise not to use it */
 182 #define HW_APB_CHx_CMD__HALTONTERMINATE    (1 << 8)
 183 #define HW_APB_CHx_CMD__CMDWORDS_BM         0xf000
 184 #define HW_APB_CHx_CMD__CMDWORDS_BP         12
 185 #define HW_APB_CHx_CMD__XFER_COUNT_BM       0xffff0000
 186 #define HW_APB_CHx_CMD__XFER_COUNT_BP       16
 187 /* For software use */
 188 #define HW_APB_CHx_CMD__UNUSED_BP           8
 189 #define HW_APB_CHx_CMD__UNUSED_BM           (0xf << 8)
 190 #define HW_APB_CHx_CMD__UNUSED_MAGIC        (0xa << 8)
 191
 192 #define HW_APB_CHx_SEMA__PHORE_BM           0xff0000
 193 #define HW_APB_CHx_SEMA__PHORE_BP           16
 194
 195 /* A single descriptor cannot transfer more than 2^16 bytes but because of the
 196  * weird 0=64KiB, it's safer to restrict to 2^15 */
 197 #define IMX233_MAX_SINGLE_DMA_XFER_SIZE     (1 << 15)
 198
 199 void imx233_dma_init(void);
 200 void imx233_dma_reset_channel(unsigned chan);
 201 /* only apbh channel have clkgate control */
 202 void imx233_dma_clkgate_channel(unsigned chan, bool enable_clock);
 203
 204 void imx233_dma_freeze_channel(unsigned chan, bool freeze);
 205 void imx233_dma_enable_channel_interrupt(unsigned chan, bool enable);
 206 /* clear both channel complete and error bits */
 207 void imx233_dma_clear_channel_interrupt(unsigned chan);
 208 bool imx233_dma_is_channel_error_irq(unsigned chan);
 209 /* assume no command is in progress */
 210 void imx233_dma_start_command(unsigned chan, struct apb_dma_command_t *cmd);
 211 /* return value of the semaphore */
 212 int imx233_dma_wait_completion(unsigned chan, unsigned tmo);
 213 /* get some info
 214  * WARNING: if channel is not freezed, data might not be coherent ! */
 215 struct imx233_dma_info_t imx233_dma_get_info(unsigned chan, unsigned flags);
 216
 217 #endif // __DMA_IMX233_H__