We have a 3.9 release, update builds.pm
[maemo-rb.git] / bootloader / rk27xx.c
blobd94b08034593c8d1d713214c764c86246a3d420e
1 #include "config.h"
2 #include <stdlib.h>
3 #include <stdio.h>
4 #include <string.h>
5 #include "inttypes.h"
6 #include "string.h"
7 #include "cpu.h"
8 #include "system.h"
9 #include "lcd.h"
10 #include "kernel.h"
11 #include "thread.h"
12 #include "backlight.h"
13 #include "backlight-target.h"
14 #include "font.h"
15 #include "common.h"
16 #include "version.h"
18 // 441 Hz samples table, 44100 Hz and 441 Hz -> 100 samples
19 const int16_t samples[] = {
20 0, 2057, 4106, 6139, 8148, 10125, 12062, 13951, 15785, 17557,
21 19259, 20886, 22430, 23886, 25247, 26509, 27666, 28713, 29648, 30465,
22 31163, 31737, 32186, 32508, 32702, 32767, 32702, 32508, 32186, 31737,
23 31163, 30465, 29648, 28713, 27666, 26509, 25247, 23886, 22430, 20886,
24 19259, 17557, 15785, 13951, 12062, 10125, 8148, 6139, 4106, 2057,
25 0, -2057, -4106, -6139, -8148, -10125, -12062, -13951, -15785, -17557,
26 -19259, -20886, -22430, -23886, -25247, -26509, -27666, -28713, -29648, -30465,
27 -31163, -31737, -32186, -32508, -32702, -32767, -32702, -32508, -32186, -31737,
28 -31163, -30465, -29648, -28713, -27666, -26509, -25247, -23886, -22430, -20886,
29 -19259, -17557, -15785, -13951, -12062, -10125, -8148, -6139, -4106, -2057 };
31 extern int show_logo( void );
33 void INT_HDMA(void)
35 #if 0
36 // static uint32_t i;
37 // printf("hdma int: %d", i++);
39 HDMA_ISRC0 = (uint32_t)&samples;
40 HDMA_IDST0 = (uint32_t)&I2S_TXR;
41 HDMA_ICNT0 = (sizeof(samples)/4) - 1;
42 HDMA_CON0 = (1<<22)| // slice mode
43 (1<<21)| // channel enable
44 (1<<18)| // interrupt mode
45 (5<<13)| // transfer mode inc8
46 (6<<9) | // hdreq from i2s tx
47 (0<<7) | // source address increment
48 (1<<5) | // destination address fixed
49 (2<<3) | // data size word
50 (1<<0); // enable hardware triggered dma
52 HDMA_ISR = (1<<13) | // mask ch1 page overflow
53 (1<<11) | // mask ch1 page count down
54 (1<<9); // mask ch1 interrupts
55 #endif
56 return;
59 static int codec_write(uint8_t reg, uint8_t data)
61 uint8_t tmp = data;
62 return i2c_write(0x27<<1, reg<<1, 1, &tmp);
65 void main(void)
67 int i;
69 _backlight_init();
71 system_init();
72 kernel_init();
73 enable_irq();
75 lcd_init_device();
76 _backlight_on();
77 font_init();
78 lcd_setfont(FONT_SYSFIXED);
80 show_logo();
81 sleep(HZ*2);
83 printf("show logo passed");
84 // I2S init
85 SCU_CLKCFG &= ~((1<<17) | (1<<16)); // enable i2s, i2c pclk
86 //SCU_CLKCFG |= ((1<<17) | (1<<16));
87 I2S_OPR = (1<<17) | // reset Tx
88 (1<<16) | // reset Rx
89 (1<<6) | // disable HDMA Req1
90 (1<<5); // disable HDMA Req2
92 I2S_TXCTL = (1<<16) | // LRCK/SCLK = 64
93 (4<<8) | // MCLK/SCK = 4
94 (1<<4) | // 16bit samples
95 (0<<3) | // stereo mode
96 (0<<1); // I2S
98 I2S_RXCTL = (1<<16) | // LRCK/SCLK = 64
99 (4<<8) | // MCLK/SCK = 4
100 (1<<4) | // 16bit samples
101 (0<<3) | // stereo mode
102 (0<<1); // I2S
104 I2S_FIFOSTS = (1<<18) | // Tx int trigger half full
105 (1<<16); // Rx int trigger half full
107 // I2S start
108 I2S_OPR = (1<<17) | (1<<16);
109 sleep(HZ/100);
111 I2S_OPR = (0<<6) | // req channel 1 enable
112 (1<<5) | // req channel 2 disable
113 (0<<4) | // HDMA req channel 1 Tx
114 (0<<2) | // normal I2S operation (no loopback)
115 (1<<1); // Tx start
117 printf("I2S config passed");
119 HDMA_ISRC0 = (uint32_t)&samples;
120 HDMA_IDST0 = (uint32_t)&I2S_TXR;
121 HDMA_ICNT0 = (sizeof(samples)/4) - 1;
122 HDMA_ISCNT0 = 7;
123 HDMA_IPNCNTD0 = 1;
124 HDMA_CON0 = (1<<22)| // slice mode
125 (1<<21)| // channel enable
126 (1<<18)| // interrupt mode
127 (5<<13)| // transfer mode inc8
128 (6<<9) | // hdreq from i2s tx
129 (0<<7) | // source address increment
130 (1<<5) | // destination address fixed
131 (2<<3) | // data size word
132 (1<<0); // enable hardware triggered dma
134 HDMA_ISR = (1<<13) | // mask ch1 page overflow
135 (1<<11) | // mask ch1 page count down
136 (1<<9); // mask ch1 interrupts
138 INTC_IMR |= (1<<12);
139 INTC_IECR |= (1<<12);
141 printf("HDMA config passed");
143 i2c_init();
145 printf("I2C config passed");
147 // codec init
148 codec_write(0x00, (1<<3)|(1<<2)|(1<<1)|(1<<0)); // AICR
149 codec_write(0x01, (1<<7)|(1<<5)|(1<<3)); // CR1
150 codec_write(0x02, (1<<2)); // CR2
151 codec_write(0x03, 0); // CCR1
152 codec_write(0x04, (2<<4)|(2<<0)); // CCR2
153 codec_write(0x07, (3<<5)|(3<<0)); // CCR
156 codec_write(0x0f, 0x1f|(2<<6)); // CGR6
157 codec_write(0x14, (1<<1)); // TR1
158 codec_write(0x05, (1<<6)|(1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|(1<<0)); // PMR1
159 sleep(HZ/100);
161 codec_write(0x06, (1<<3)|(1<<2)|(1<<0)); // PMR2
164 codec_write(0x05, (1<<6)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|(1<<0)); // PMR1
165 codec_write(0x05, (1<<4)|(1<<3)|(1<<2)|(1<<1)|(1<<0)); // PMR1
168 // DACout mode
169 codec_write(0x01, (1<<7)|(1<<3)|(1<<5)|(1<<4)); // CR1
170 codec_write(0x05, (1<<4)|(1<<3)|(1<<2)|(1<<1)|(1<<0)); //PMR1
171 // codec_write(0x06, (1<<3)|(1<<2)); // PMR2
173 printf("codec init passed");
175 codec_write(0x01, (1<<7)|(1<<3)); // CR1
177 codec_write(0x0a, 0); // 0dB digital gain
178 codec_write(0x11, 15|(2<<6)); //
180 while(1)
182 printf("HDMA_CCNT0: 0x%0x FIFOSTS: 0x%0x", HDMA_CCNT0, I2S_FIFOSTS);