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Add "elfzip" target to make which creates a zip of all elf files, as mapzip does...
[maemo-rb.git] / firmware / export / imx31l.h
blobca4ab0c0198cd371f6b5deed24319c5f0d1249dd
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2006 by James Espinoza
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21 #ifndef __IMX31L_H__
22 #define __IMX31L_H__
23
24 /* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/
25
26 #define REG8_PTR_T volatile unsigned char *
27 #define REG16_PTR_T volatile unsigned short *
28 #define REG32_PTR_T volatile unsigned long *
29
30 /* Place in the section with the framebuffer */
31 #define TTB_BASE_ADDR (CSD0_BASE_ADDR + (MEMORYSIZE*0x100000) - TTB_SIZE)
32 #define TTB_SIZE (0x4000)
33 #define IRAM_SIZE (0x4000)
34 #define TTB_BASE ((unsigned long *)TTB_BASE_ADDR)
35 #define FRAME_SIZE (240*320*2)
36 /* Rockbox framebuffer address, not retail OS */
37 #define FRAME_PHYS_ADDR (TTB_BASE_ADDR - FRAME_SIZE)
38 #define FRAME ((void *)(FRAME_PHYS_ADDR+0x100000-CSD0_BASE_ADDR))
39
40 #define CACHEALIGN_BITS 5
41 #define CACHEALIGN_SIZE 32
42 #define NOCACHE_BASE CSD0_BASE_ADDR
43
44 /* USBOTG */
45 #define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048)))
46 #define USB_NUM_ENDPOINTS 8
47 #define USB_DEVBSS_ATTR NOCACHEBSS_ATTR
48 #define USB_BASE OTG_BASE_ADDR
49 #define QHARRAY_SIZE ((64*USB_NUM_ENDPOINTS*2 + 2047) & (0xffffffff - 2047))
50 #define QHARRAY_PHYS_ADDR ((FRAME_PHYS_ADDR - QHARRAY_SIZE) & (0xffffffff - 2047))
51
52 /*
53 * AIPS 1
54 */
55 #define IRAM_BASE_ADDR 0x1fffc000
56 #define L2CC_BASE_ADDR 0x30000000
57 #define AIPS1_BASE_ADDR 0x43F00000
58 #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
59 #define MAX_BASE_ADDR 0x43F04000
60 #define EVTMON_BASE_ADDR 0x43F08000
61 #define CLKCTL_BASE_ADDR 0x43F0C000
62 #define ETB_SLOT4_BASE_ADDR 0x43F10000
63 #define ETB_SLOT5_BASE_ADDR 0x43F14000
64 #define ECT_CTIO_BASE_ADDR 0x43F18000
65 #define I2C1_BASE_ADDR 0x43F80000
66 #define I2C3_BASE_ADDR 0x43F84000
67 #define OTG_BASE_ADDR 0x43F88000
68 #define ATA_BASE_ADDR 0x43F8C000
69 #define UART1_BASE_ADDR 0x43F90000
70 #define UART2_BASE_ADDR 0x43F94000
71 #define I2C2_BASE_ADDR 0x43F98000
72 #define OWIRE_BASE_ADDR 0x43F9C000
73 #define SSI1_BASE_ADDR 0x43FA0000
74 #define CSPI1_BASE_ADDR 0x43FA4000
75 #define KPP_BASE_ADDR 0x43FA8000
76 #define IOMUXC_BASE_ADDR 0x43FAC000
77 #define UART4_BASE_ADDR 0x43FB0000
78 #define UART5_BASE_ADDR 0x43FB4000
79 #define ECT_IP1_BASE_ADDR 0x43FB8000
80 #define ECT_IP2_BASE_ADDR 0x43FBC000
81
82 /*
83 * SPBA
84 */
85 #define SPBA_BASE_ADDR 0x50000000
86 #define MMC_SDHC1_BASE_ADDR 0x50004000
87 #define MMC_SDHC2_BASE_ADDR 0x50008000
88 #define UART3_BASE_ADDR 0x5000C000
89 #define CSPI2_BASE_ADDR 0x50010000
90 #define SSI2_BASE_ADDR 0x50014000
91 #define SIM_BASE_ADDR 0x50018000
92 #define IIM_BASE_ADDR 0x5001C000
93 #define ATA_DMA_BASE_ADDR 0x50020000
94 #define SPBA_CTRL_BASE_ADDR 0x5003C000
95
96 /*
97 * AIPS 2
98 */
99 #define AIPS2_BASE_ADDR 0x53F00000
100 #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
101 #define CCM_BASE_ADDR 0x53F80000
102 #define CSPI3_BASE_ADDR 0x53F84000
103 #define FIRI_BASE_ADDR 0x53F8C000
104 #define GPT1_BASE_ADDR 0x53F90000
105 #define EPIT1_BASE_ADDR 0x53F94000
106 #define EPIT2_BASE_ADDR 0x53F98000
107 #define GPIO3_BASE_ADDR 0x53FA4000
108 #define SCC_BASE 0x53FAC000
109 #define SCM_BASE 0x53FAE000
110 #define SMN_BASE 0x53FAF000
111 #define RNGA_BASE_ADDR 0x53FB0000
112 #define IPU_CTRL_BASE_ADDR 0x53FC0000
113 #define AUDMUX_BASE 0x53FC4000
114 #define MPEG4_ENC_BASE 0x53FC8000
115 #define GPIO1_BASE_ADDR 0x53FCC000
116 #define GPIO2_BASE_ADDR 0x53FD0000
117 #define SDMA_BASE_ADDR 0x53FD4000
118 #define RTC_BASE_ADDR 0x53FD8000
119 #define WDOG_BASE_ADDR 0x53FDC000
120 #define PWM_BASE_ADDR 0x53FE0000
121 #define RTIC_BASE_ADDR 0x53FEC000
122
123 #define WDOG1_BASE_ADDR WDOG_BASE_ADDR
124 #define CRM_MCU_BASE_ADDR CCM_BASE_ADDR
125
126 /* IIM */
127 #define IIM_PREV (*(REG32_PTR_T)(IIM_BASE_ADDR + 0x20))
128 #define IIM_PREV_SIG (0x1f << 3)
129 #define IIM_PREV_SIG_IMX31 (0x01 << 3) /* i.MX31 */
130 #define IIM_SREV (*(REG32_PTR_T)(IIM_BASE_ADDR + 0x24))
131 #define IIM_SREV_SREV (0xff << 0)
132 #define IIM_SREV_1_0 0x00 /* i.MX31/L 1.0, L38W */
133 #define IIM_SREV_1_1 0x10 /* i.MX31 1.1, 2L38W */
134 #define IIM_SREV_1_1L 0x11 /* i.MX31L 1.1, 2L38W */
135 #define IIM_SREV_1_15 0x12 /* i.MX31 1.15, 2L38W/3L38W */
136 #define IIM_SREV_1_15L 0x13 /* i.MX31L 1.15, 2L38W/3L38W */
137 #define IIM_SREV_1_2 0x14 /* i.MX31 1.2, 3L38W, M45G */
138 #define IIM_SREV_1_2L 0x15 /* i.MX31L 1.2, 3L38W, M45G */
139 #define IIM_SREV_2_0_1 0x28 /* i.MX31 2.0/2.0.1, M91E */
140 #define IIM_SREV_2_0_1L 0x29 /* i.MX31L 2.0/2.0.1, M91E */
141
142 /* IOMUXC */
143 #define IOMUXC_GPR (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+0x008))
144
145 /* SW_MUX_CTL_* */
146 #define IOMUXC_MUX_OUT (0x7 << 4)
147 #define IOMUXC_MUX_OUT_POS (4)
148 #define IOMUXC_MUX_IN (0xf << 0)
149 #define IOMUXC_MUX_IN_POS (0)
150 #define IOMUXC_MUX_MASK (0x7f)
151
152 #define IOMUXC_MUX_OUT_GPIO (0x0 << IOMUXC_MUX_OUT_POS)
153 #define IOMUXC_MUX_OUT_FUNCTIONAL (0x1 << IOMUXC_MUX_OUT_POS)
154 #define IOMUXC_MUX_OUT_ALT1 (0x2 << IOMUXC_MUX_OUT_POS)
155 #define IOMUXC_MUX_OUT_ALT2 (0x3 << IOMUXC_MUX_OUT_POS)
156 #define IOMUXC_MUX_OUT_ALT3 (0x4 << IOMUXC_MUX_OUT_POS)
157 #define IOMUXC_MUX_OUT_ALT4 (0x5 << IOMUXC_MUX_OUT_POS)
158 #define IOMUXC_MUX_OUT_ALT5 (0x6 << IOMUXC_MUX_OUT_POS)
159 #define IOMUXC_MUX_OUT_ALT6 (0x7 << IOMUXC_MUX_OUT_POS)
160
161 #define IOMUXC_MUX_IN_NONE (0x0 << IOMUXC_MUX_IN_POS)
162 #define IOMUXC_MUX_IN_GPIO (0x1 << IOMUXC_MUX_IN_POS)
163 #define IOMUXC_MUX_IN_FUNCTIONAL (0x2 << IOMUXC_MUX_IN_POS)
164 #define IOMUXC_MUX_IN_ALT1 (0x4 << IOMUXC_MUX_IN_POS)
165 #define IOMUXC_MUX_IN_ALT2 (0x8 << IOMUXC_MUX_IN_POS)
166
167 /* SW_PAD_CTL_* */
168 #define IOMUXC_PAD_LOOPBACK (0x1 << 9) /* Route output to input */
169 /* Pullup, pulldown and keeper enable */
170 #define IOMUXC_PAD_PUE_PKE (0x3 << 7)
171 #define IOMUXC_PAD_PUE_PKE_DISABLE (0x0 << 7)
172 #define IOMUXC_PAD_PUE_PKE_DISABLE_2 (0x1 << 7) /* Same as 0x0 */
173 #define IOMUXC_PAD_PUE_PKE_KEEPER (0x2 << 7)
174 #define IOMUXC_PAD_PUE_PKE_PULLUPDOWN (0x3 << 7) /* Enb. Pull up or down */
175 /* Pullup/down resistance */
176 #define IOMUXC_PAD_PUS (0x3 << 5)
177 #define IOMUXC_PAD_PUS_DOWN_100K (0x0 << 5)
178 #define IOMUXC_PAD_PUS_UP_100K (0x1 << 5)
179 #if 0 /* Completeness */
180 #define IOMUXC_PAD_PUS_UP_47K (0x2 << 5) /* Not in IMX31/L */
181 #define IOMUXC_PAD_PUS_UP_22K (0x3 << 5) /* Not in IMX31/L */
182 #endif
183 #define IOMUXC_PAD_HYS (0x1 << 4) /* Schmitt trigger input */
184 #define IOMUXC_PAD_ODE (0x1 << 3) /* Open drain output 0=CMOS pushpull*/
185 #define IOMUXC_PAD_DSE (0x3 << 1)
186 #define IOMUXC_PAD_DSE_STD (0x0 << 1) /* Drive strength */
187 #define IOMUXC_PAD_DSE_HIGH (0x1 << 1)
188 #define IOMUXC_PAD_DSE_MAX (0x2 << 1)
189 #define IOMUXC_PAD_DSE_MAX_2 (0x3 << 1) /* Same as 0x2 */
190 #define IOMUXC_PAD_SRE (0x1 << 0) /* Slew rate, 1=fast */
191
192 #define IOMUXC_PAD_MASK (0x3ff)
193
194 /* RNGA */
195 #define RNGA_CONTROL (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00))
196
197 #define RNGA_CONTROL_SLEEP (1 << 4)
198
199 /* IPU */
200 #define IPU_IPU_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x000))
201 #define IPU_IPU_CHA_BUF0_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x004))
202 #define IPU_IPU_CHA_BUF1_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x008))
203 #define IPU_IPU_CHA_DB_MODE_SEL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00C))
204 #define IPU_IPU_CHA_CUR_BUF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x010))
205 #define IPU_IPU_FS_PROC_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x014))
206 #define IPU_IPU_FS_DISP_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x018))
207 #define IPU_IPU_TASKS_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x01C))
208 #define IPU_IPU_IMA_ADDR (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x020))
209 #define IPU_IPU_IMA_DATA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x024))
210 #define IPU_IPU_INT_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x028))
211 #define IPU_IPU_INT_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x02C))
212 #define IPU_IPU_INT_CTRL_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x030))
213 #define IPU_IPU_INT_CTRL_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x034))
214 #define IPU_IPU_INT_CTRL_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x038))
215 #define IPU_IPU_INT_STAT_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x03C))
216 #define IPU_IPU_INT_STAT_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x040))
217 #define IPU_IPU_INT_STAT_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x044))
218 #define IPU_IPU_INT_STAT_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x048))
219 #define IPU_IPU_INT_STAT_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04C))
220 #define IPU_IPU_BRK_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x050))
221 #define IPU_IPU_BRK_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x054))
222 #define IPU_IPU_BRK_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x058))
223 #define IPU_IPU_DIAGB_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x060))
224 #define IPU_CSI_SENS_FRM_SIZE (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x064))
225 #define IPU_CSI_ACT_FRM_SIZE (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x068))
226 #define IPU_CSI_OUT_FRM_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x06C))
227 #define IPU_CSI_TST_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x070))
228 #define IPU_CSI_CCIR_CODE_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x074))
229 #define IPU_CSI_CCIR_CODE_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x078))
230 #define IPU_CSI_CCIR_CODE_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x07C))
231 #define IPU_CSI_FLASH_STROBE_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x080))
232 #define IPU_CSI_FLASH_STROBE_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x084))
233 #define IPU_IC_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x088))
234 #define IPU_IC_PRP_ENC_RSC (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x08C))
235 #define IPU_IC_PRP_VF_RSC (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x090))
236 #define IPU_IC_PP_RSC (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x094))
237 #define IPU_IC_CMBP_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x098))
238 #define IPU_IC_CMBP_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x09C))
239 #define IPU_PF_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0A0))
240 #define IPU_IDMAC_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0A4))
241 #define IPU_IDMAC_CHA_EN (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0A8))
242 #define IPU_IDMAC_CHA_PRI (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0AC))
243 #define IPU_IDMAC_CHA_BUSY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0B0))
244 #define IPU_SDC_COM_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0B4))
245 #define IPU_SDC_GRAPH_WIND_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0B8))
246 #define IPU_SDC_FG_POS (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0BC))
247 #define IPU_SDC_BG_POS (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C0))
248 #define IPU_SDC_CUR_POS (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C4))
249 #define IPU_SDC_CUR_BLINK_PWM_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C8))
250 #define IPU_SDC_CUR_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0CC))
251 #define IPU_SDC_HOR_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0D0))
252 #define IPU_SDC_VER_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0D4))
253 #define IPU_SDC_SHARP_CONF_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0D8))
254 #define IPU_SDC_SHARP_CONF_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0DC))
255 #define IPU_SDC_ADC_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0E0))
256 #define IPU_ADC_SYSCHA1_SA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0E4))
257 #define IPU_ADC_SYSCHA2_SA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0E8))
258 #define IPU_ADC_PRPCHAN_SA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0EC))
259 #define IPU_ADC_PPCHAN_SA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0F0))
260 #define IPU_ADC_DISP0_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0F4))
261 #define IPU_ADC_DISP0_RD_AP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0F8))
262 #define IPU_ADC_DISP0_RDM (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0FC))
263 #define IPU_ADC_DISP0_SS (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x100))
264 #define IPU_ADC_DISP1_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x104))
265 #define IPU_ADC_DISP1_RD_AP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x108))
266 #define IPU_ADC_DISP1_RDM (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x10C))
267 #define IPU_ADC_DISP2_SS (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x110))
268 #define IPU_ADC_DISP2_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x114))
269 #define IPU_ADC_DISP2_RD_AP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x118))
270 #define IPU_ADC_DISP2_RDM (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x11C))
271 #define IPU_ADC_DISP_VSYNC (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x120))
272 #define IPU_ADC_DISP_IF_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x124))
273 #define IPU_ADC_DISP_SIG_POL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x128))
274 #define IPU_DI_SER_DISP1_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x12C))
275 #define IPU_DI_SER_DISP2_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x130))
276 #define IPU_DI_HSP_CLK_PER (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x134))
277 #define IPU_DI_DISP0_TIME_CONF_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x138))
278 #define IPU_DI_DISP0_TIME_CONF_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x13C))
279 #define IPU_DI_DISP0_TIME_CONF_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x140))
280 #define IPU_DI_DISP1_TIME_CONF_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x144))
281 #define IPU_DI_DISP1_TIME_CONF_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x148))
282 #define IPU_DI_DISP1_TIME_CONF_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x14C))
283 #define IPU_DI_DISP2_TIME_CONF_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x150))
284 #define IPU_DI_DISP2_TIME_CONF_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x154))
285 #define IPU_DI_DISP2_TIME_CONF_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x158))
286 #define IPU_DI_DISP3_TIME_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x15C))
287 #define IPU_DI_DISP0_DB0_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x160))
288 #define IPU_DI_DISP0_DB1_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x164))
289 #define IPU_DI_DISP0_DB2_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x168))
290 #define IPU_DI_DISP0_CB0_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x16C))
291 #define IPU_DI_DISP0_CB1_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x170))
292 #define IPU_DI_DISP0_CB2_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x174))
293 #define IPU_DI_DISP1_DB0_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x178))
294 #define IPU_DI_DISP1_DB1_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x17C))
295 #define IPU_DI_DISP1_DB2_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x180))
296 #define IPU_DI_DISP1_CB0_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x184))
297 #define IPU_DI_DISP1_CB1_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x188))
298 #define IPU_DI_DISP1_CB2_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x18C))
299 #define IPU_DI_DISP2_DB0_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x190))
300 #define IPU_DI_DISP2_DB1_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x194))
301 #define IPU_DI_DISP2_DB2_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x198))
302 #define IPU_DI_DISP2_CB0_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x19C))
303 #define IPU_DI_DISP2_CB1_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1A0))
304 #define IPU_DI_DISP2_CB2_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1A4))
305 #define IPU_DI_DISP3_B0_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1A8))
306 #define IPU_DI_DISP3_B1_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1AC))
307 #define IPU_DI_DISP3_B2_MAP (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1B0))
308 #define IPU_DI_DISP_ACC_CC (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1B4))
309 #define IPU_DI_DISP_LLA_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1B8))
310 #define IPU_DI_DISP_LLA_DATA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1BC))
311
312 /* IPU_CONF */
313 #define IPU_IPU_CONF_PXL_ENDIAN (1 << 8)
314 #define IPU_IPU_CONF_DU_EN (1 << 7)
315 #define IPU_IPU_CONF_DI_EN (1 << 6)
316 #define IPU_IPU_CONF_ADC_EN (1 << 5)
317 #define IPU_IPU_CONF_SDC_EN (1 << 4)
318 #define IPU_IPU_CONF_PF_EN (1 << 3)
319 #define IPU_IPU_CONF_ROT_EN (1 << 2)
320 #define IPU_IPU_CONF_IC_EN (1 << 1)
321 #define IPU_IPU_CONF_CSI_EN (1 << 0)
322
323 /* ATA */
324 #define ATA_TIME_OFF (*(REG8_PTR_T)(ATA_BASE_ADDR+0x00))
325 #define ATA_TIME_ON (*(REG8_PTR_T)(ATA_BASE_ADDR+0x01))
326 /* PIO */
327 #define ATA_TIME_1 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x02))
328 #define ATA_TIME_2W (*(REG8_PTR_T)(ATA_BASE_ADDR+0x03))
329 #define ATA_TIME_2R (*(REG8_PTR_T)(ATA_BASE_ADDR+0x04))
330 #define ATA_TIME_AX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x05))
331 #define ATA_TIME_PIO_RDX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x06))
332 #define ATA_TIME_4 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x07))
333 #define ATA_TIME_9 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x08))
334 /* MDMA */
335 #define ATA_TIME_M (*(REG8_PTR_T)(ATA_BASE_ADDR+0x09))
336 #define ATA_TIME_JN (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0A))
337 #define ATA_TIME_D (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0B))
338 #define ATA_TIME_K (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0C))
339 /* UDMA */
340 #define ATA_TIME_ACK (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0D))
341 #define ATA_TIME_ENV (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0E))
342 #define ATA_TIME_RPX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0F))
343 #define ATA_TIME_ZAH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x10))
344 #define ATA_TIME_MLIX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x11))
345 #define ATA_TIME_DVH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x12))
346 #define ATA_TIME_DZFS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x13))
347 #define ATA_TIME_DVS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x14))
348 #define ATA_TIME_CVH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x15))
349 #define ATA_TIME_SS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x16))
350 #define ATA_TIME_CYC (*(REG8_PTR_T)(ATA_BASE_ADDR+0x17))
351 /* */
352 #define ATA_FIFO_DATA_32 (*(REG32_PTR_T)(ATA_BASE_ADDR+0x18))
353 #define ATA_FIFO_DATA_16 (*(REG16_PTR_T)(ATA_BASE_ADDR+0x1c))
354 #define ATA_FIFO_FILL (*(REG8_PTR_T)(ATA_BASE_ADDR+0x20))
355 /* Actually ATA_CONTROL but conflicts arise */
356 #define ATA_INTF_CONTROL (*(REG8_PTR_T)(ATA_BASE_ADDR+0x24))
357 #define ATA_INTERRUPT_PENDING (*(REG8_PTR_T)(ATA_BASE_ADDR+0x28))
358 #define ATA_INTERRUPT_ENABLE (*(REG8_PTR_T)(ATA_BASE_ADDR+0x2c))
359 #define ATA_INTERRUPT_CLEAR (*(REG8_PTR_T)(ATA_BASE_ADDR+0x30))
360 #define ATA_FIFO_ALARM (*(REG8_PTR_T)(ATA_BASE_ADDR+0x34))
361 #define ATA_DRIVE_DATA (*(REG16_PTR_T)(ATA_BASE_ADDR+0xA0))
362 #define ATA_DRIVE_FEATURES (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA4))
363 #define ATA_DRIVE_SECTOR_COUNT (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA8))
364 #define ATA_DRIVE_SECTOR_NUM (*(REG8_PTR_T)(ATA_BASE_ADDR+0xAC))
365 #define ATA_DRIVE_CYL_LOW (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB0))
366 #define ATA_DRIVE_CYL_HIGH (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB4))
367 #define ATA_DRIVE_CYL_HEAD (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB8))
368 #define ATA_DRIVE_STATUS (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* rd */
369 #define ATA_DRIVE_COMMAND (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* wr */
370 #define ATA_ALT_DRIVE_STATUS (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* rd */
371 #define ATA_DRIVE_CONTROL (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* wr */
372
373 /* ATA_INTF_CONTROL flags */
374 #define ATA_FIFO_RST (1 << 7)
375 #define ATA_ATA_RST (1 << 6)
376 #define ATA_FIFO_TX_EN (1 << 5)
377 #define ATA_FIFO_RCV_EN (1 << 4)
378 #define ATA_DMA_PENDING (1 << 3)
379 #define ATA_DMA_ULTRA_SELECTED (1 << 2)
380 #define ATA_DMA_WRITE (1 << 1)
381 #define ATA_IORDY_EN (1 << 0)
382
383 /* ATA_INTERRUPT_PENDING, ATA_INTERRUPT_ENABLE, ATA_INTERRUPT_CLEAR flags */
384 #define ATA_INTRQ1 (1 << 7) /* INTRQ to the DMA */
385 #define ATA_FIFO_UNDERFLOW (1 << 6)
386 #define ATA_FIFO_OVERFLOW (1 << 5)
387 #define ATA_CONTROLLER_IDLE (1 << 4)
388 #define ATA_INTRQ2 (1 << 3) /* INTRQ to the MCU */
389
390 /* EPIT */
391 #define EPITCR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00))
392 #define EPITSR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x04))
393 #define EPITLR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x08))
394 #define EPITCMPR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x0C))
395 #define EPITCNT1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x10))
396
397 #define EPITCR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x00))
398 #define EPITSR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x04))
399 #define EPITLR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x08))
400 #define EPITCMPR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x0C))
401 #define EPITCNT2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x10))
402
403 #define EPITCR_CLKSRC_OFF (0 << 24)
404 #define EPITCR_CLKSRC_IPG_CLK (1 << 24)
405 #define EPITCR_CLKSRC_IPG_CLK_HIGHFREQ (2 << 24)
406 #define EPITCR_CLKSRC_IPG_CLK_32K (3 << 24)
407 #define EPITCR_OM_DISCONNECTED (0 << 22)
408 #define EPITCR_OM_TOGGLE (1 << 22)
409 #define EPITCR_OM_CLEAR (2 << 22)
410 #define EPITCR_OM_SET (3 << 22)
411 #define EPITCR_STOPEN (1 << 21)
412 #define EPITCR_DOZEN (1 << 20)
413 #define EPITCR_WAITEN (1 << 19)
414 #define EPITCR_DBGEN (1 << 18)
415 #define EPITCR_IOVW (1 << 17)
416 #define EPITCR_SWR (1 << 16)
417 #define EPITCR_PRESCALER (0xfff << 4) /* Divide by n+1 */
418 #define EPITCR_PRESCALER_POS (4)
419 #define EPITCR_RLD (1 << 3)
420 #define EPITCR_OCIEN (1 << 2)
421 #define EPITCR_ENMOD (1 << 1)
422 #define EPITCR_EN (1 << 0)
423
424 #define EPITSR_OCIF (1 << 0)
425
426 /* GPT */
427 #define GPTCR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x00))
428 #define GPTPR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x04))
429 #define GPTSR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x08))
430 #define GPTIR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x0C))
431 #define GPTOCR1 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x10))
432 #define GPTOCR2 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x14))
433 #define GPTOCR3 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x18))
434 #define GPTICR1 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x1C))
435 #define GPTICR2 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x20))
436 #define GPTCNT (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x24))
437
438 /* GPTCR */
439 #define GPTCR_FO3 (0x1 << 31)
440 #define GPTCR_FO2 (0x1 << 30)
441 #define GPTCR_FO1 (0x1 << 29)
442
443 #define GPTCR_OM3 (0x7 << 26)
444 #define GPTCR_OM3_DISCONNECTED (0x0 << 26)
445 #define GPTCR_OM3_TOGGLE (0x1 << 26)
446 #define GPTCR_OM3_CLEAR (0x2 << 26)
447 #define GPTCR_OM3_SET (0x3 << 26)
448 #define GPTCR_OM3_SINGLE_COUNT (0x4 << 26)
449 /* 0x5-0x7 same as 0x4 */
450
451 #define GPTCR_OM2 (0x7 << 23)
452 #define GPTCR_OM2_DISCONNECTED (0x0 << 23)
453 #define GPTCR_OM2_TOGGLE (0x1 << 23)
454 #define GPTCR_OM2_CLEAR (0x2 << 23)
455 #define GPTCR_OM2_SET (0x3 << 23)
456 #define GPTCR_OM2_SINGLE_COUNT (0x4 << 23)
457
458 /* 0x5-0x7 same as 0x4 */
459 #define GPTCR_OM1 (0x7 << 20)
460 #define GPTCR_OM1_DISCONNECTED (0x0 << 20)
461 #define GPTCR_OM1_TOGGLE (0x1 << 20)
462 #define GPTCR_OM1_CLEAR (0x2 << 20)
463 #define GPTCR_OM1_SET (0x3 << 20)
464 #define GPTCR_OM1_SINGLE_COUNT (0x4 << 20)
465
466 /* 0x5-0x7 same as 0x4 */
467 #define GPTCR_IM2 (0x3 << 18)
468 #define GPTCR_IM2_DISABLED (0x0 << 18)
469 #define GPTCR_IM2_RISING (0x1 << 18)
470 #define GPTCR_IM2_FALLING (0x2 << 18)
471 #define GPTCR_IM2_BOTH (0x3 << 18)
472
473 #define GPTCR_IM1 (0x3 << 16)
474 #define GPTCR_IM1_DISABLED (0x0 << 16)
475 #define GPTCR_IM1_RISING (0x1 << 16)
476 #define GPTCR_IM1_FALLING (0x2 << 16)
477 #define GPTCR_IM1_BOTH (0x3 << 16)
478
479 #define GPTCR_SWR (0x1 << 15)
480 #define GPTCR_FRR (0x1 << 9)
481
482 #define GPTCR_CLKSRC (0x7 << 6)
483 #define GPTCR_CLKSRC_NONE (0x0 << 6)
484 #define GPTCR_CLKSRC_IPG_CLK (0x1 << 6)
485 #define GPTCR_CLKSRC_IPG_CLK_HIGHFREQ (0x2 << 6)
486 #define GPTCR_CLKSRC_IPG_CLK_32K (0x4 << 6)
487 /* Other values not defined */
488
489 #define GPTCR_STOPEN (0x1 << 5)
490 #define GPTCR_DOZEN (0x1 << 4)
491 #define GPTCR_WAITEN (0x1 << 3)
492 #define GPTCR_DBGEN (0x1 << 2)
493 #define GPTCR_ENMODE (0x1 << 1)
494 #define GPTCR_EN (0x1 << 0)
495
496 /* GPTSR */
497 #define GPTSR_ROV (0x1 << 5)
498 #define GPTSR_IF2 (0x1 << 4)
499 #define GPTSR_IF1 (0x1 << 3)
500 #define GPTSR_OF3 (0x1 << 2)
501 #define GPTSR_OF2 (0x1 << 1)
502 #define GPTSR_OF1 (0x1 << 0)
503
504 /* GPTIR */
505 #define GPTIR_ROV (0x1 << 5)
506 #define GPTIR_IF2IE (0x1 << 4)
507 #define GPTIR_IF1IE (0x1 << 3)
508 #define GPTIR_OF3IE (0x1 << 2)
509 #define GPTIR_OF2IE (0x1 << 1)
510 #define GPTIR_OF1IE (0x1 << 0)
511
512 /* GPIO */
513 #define GPIO1_DR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x00))
514 #define GPIO1_GDIR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x04))
515 #define GPIO1_PSR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x08))
516 #define GPIO1_ICR1 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x0C))
517 #define GPIO1_ICR2 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x10))
518 #define GPIO1_IMR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x14))
519 #define GPIO1_ISR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x18))
520
521 #define GPIO2_DR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x00))
522 #define GPIO2_GDIR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x04))
523 #define GPIO2_PSR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x08))
524 #define GPIO2_ICR1 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x0C))
525 #define GPIO2_ICR2 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x10))
526 #define GPIO2_IMR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x14))
527 #define GPIO2_ISR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x18))
528
529 #define GPIO3_DR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x00))
530 #define GPIO3_GDIR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x04))
531 #define GPIO3_PSR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x08))
532 #define GPIO3_ICR1 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x0C))
533 #define GPIO3_ICR2 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x10))
534 #define GPIO3_IMR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x14))
535 #define GPIO3_ISR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18))
536
537 /* CSPI */
538 #define CSPI_RXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x00))
539 #define CSPI_TXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x04))
540 #define CSPI_CONREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x08))
541 #define CSPI_INTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x0C))
542 #define CSPI_DMAREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x10))
543 #define CSPI_STATREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x14))
544 #define CSPI_PERIODREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x18))
545 #define CSPI_TESTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x1C0))
546
547 #define CSPI_RXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x00))
548 #define CSPI_TXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x04))
549 #define CSPI_CONREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x08))
550 #define CSPI_INTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x0C))
551 #define CSPI_DMAREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x10))
552 #define CSPI_STATREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x14))
553 #define CSPI_PERIODREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x18))
554 #define CSPI_TESTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x1C0))
555
556 #define CSPI_RXDATA3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x00))
557 #define CSPI_TXDATA3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x04))
558 #define CSPI_CONREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x08))
559 #define CSPI_INTREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x0C))
560 #define CSPI_DMAREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x10))
561 #define CSPI_STATREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x14))
562 #define CSPI_PERIODREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x18))
563 #define CSPI_TESTREG3 (*(REG32_PTR_T)(CSPI3_BASE_ADDR+0x1C0))
564
565 /* CSPI CONREG flags/fields */
566 #define CSPI_CONREG_CHIP_SELECT_SS0 (0 << 24)
567 #define CSPI_CONREG_CHIP_SELECT_SS1 (1 << 24)
568 #define CSPI_CONREG_CHIP_SELECT_SS2 (2 << 24)
569 #define CSPI_CONREG_CHIP_SELECT_SS3 (3 << 24)
570 #define CSPI_CONREG_CHIP_SELECT_MASK (3 << 24)
571 #define CSPI_CONREG_DRCTL_DONT_CARE (0 << 20)
572 #define CSPI_CONREG_DRCTL_TRIG_FALLING (1 << 20)
573 #define CSPI_CONREG_DRCTL_TRIG_LOW (2 << 20)
574 #define CSPI_CONREG_DRCTL_TRIG_RSV (3 << 20)
575 #define CSPI_CONREG_DRCTL_MASK (3 << 20)
576 #define CSPI_CONREG_DATA_RATE_DIV_4 (0 << 16)
577 #define CSPI_CONREG_DATA_RATE_DIV_8 (1 << 16)
578 #define CSPI_CONREG_DATA_RATE_DIV_16 (2 << 16)
579 #define CSPI_CONREG_DATA_RATE_DIV_32 (3 << 16)
580 #define CSPI_CONREG_DATA_RATE_DIV_64 (4 << 16)
581 #define CSPI_CONREG_DATA_RATE_DIV_128 (5 << 16)
582 #define CSPI_CONREG_DATA_RATE_DIV_256 (6 << 16)
583 #define CSPI_CONREG_DATA_RATE_DIV_512 (7 << 16)
584 #define CSPI_CONREG_DATA_RATE_DIV_MASK (7 << 16)
585 #define CSPI_BITCOUNT(n) ((n) << 8)
586 #define CSPI_CONREG_SSPOL (1 << 7)
587 #define CSPI_CONREG_SSCTL (1 << 6)
588 #define CSPI_CONREG_PHA (1 << 5)
589 #define CSPI_CONREG_POL (1 << 4)
590 #define CSPI_CONREG_SMC (1 << 3)
591 #define CSPI_CONREG_XCH (1 << 2)
592 #define CSPI_CONREG_MODE (1 << 1)
593 #define CSPI_CONREG_EN (1 << 0)
594
595 /* CSPI INTREG flags */
596 #define CSPI_INTREG_TCEN (1 << 8)
597 #define CSPI_INTREG_BOEN (1 << 7)
598 #define CSPI_INTREG_ROEN (1 << 6)
599 #define CSPI_INTREG_RFEN (1 << 5)
600 #define CSPI_INTREG_RHEN (1 << 4)
601 #define CSPI_INTREG_RREN (1 << 3)
602 #define CSPI_INTREG_TFEN (1 << 2)
603 #define CSPI_INTREG_THEN (1 << 1)
604 #define CSPI_INTREG_TEEN (1 << 0)
605
606 /* CSPI DMAREG flags */
607 #define CSPI_DMAREG_RFDEN (1 << 5)
608 #define CSPI_DMAREG_RHDEN (1 << 4)
609 #define CSPI_DMAREG_THDEN (1 << 1)
610 #define CSPI_DMAREG_TEDEN (1 << 0)
611
612 /* CSPI STATREG flags */
613 #define CSPI_STATREG_TC (1 << 8) /* w1c */
614 #define CSPI_STATREG_BO (1 << 7) /* w1c */
615 #define CSPI_STATREG_RO (1 << 6)
616 #define CSPI_STATREG_RF (1 << 5)
617 #define CSPI_STATREG_RH (1 << 4)
618 #define CSPI_STATREG_RR (1 << 3)
619 #define CSPI_STATREG_TF (1 << 2)
620 #define CSPI_STATREG_TH (1 << 1)
621 #define CSPI_STATREG_TE (1 << 0)
622
623 /* CSPI PERIODREG flags */
624 #define CSPI_PERIODREG_CSRC (1 << 15)
625
626 /* CSPI TESTREG flags */
627 #define CSPI_TESTREG_SWAP (1 << 15)
628 #define CSPI_TESTREG_LBC (1 << 14)
629
630 /* I2C */
631 #define I2C_IADR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x0))
632 #define I2C_IFDR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x4))
633 #define I2C_I2CR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x8))
634 #define I2C_I2SR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0xC))
635 #define I2C_I2DR1 (*(REG16_PTR_T)(I2C1_BASE_ADDR+0x10))
636
637 #define I2C_IADR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x0))
638 #define I2C_IFDR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x4))
639 #define I2C_I2CR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x8))
640 #define I2C_I2SR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0xC))
641 #define I2C_I2DR2 (*(REG16_PTR_T)(I2C2_BASE_ADDR+0x10))
642
643 #define I2C_IADR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x0))
644 #define I2C_IFDR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x4))
645 #define I2C_I2CR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x8))
646 #define I2C_I2SR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0xC))
647 #define I2C_I2DR3 (*(REG16_PTR_T)(I2C3_BASE_ADDR+0x10))
648
649 /* IADR - [7:1] Address */
650
651 /* IFDR */
652 #define I2C_IFDR_DIV30 0x00
653 #define I2C_IFDR_DIV32 0x01
654 #define I2C_IFDR_DIV36 0x02
655 #define I2C_IFDR_DIV42 0x03
656 #define I2C_IFDR_DIV48 0x04
657 #define I2C_IFDR_DIV52 0x05
658 #define I2C_IFDR_DIV60 0x06
659 #define I2C_IFDR_DIV72 0x07
660 #define I2C_IFDR_DIV80 0x08
661 #define I2C_IFDR_DIV88 0x09
662 #define I2C_IFDR_DIV104 0x0a
663 #define I2C_IFDR_DIV128 0x0b
664 #define I2C_IFDR_DIV144 0x0c
665 #define I2C_IFDR_DIV160 0x0d
666 #define I2C_IFDR_DIV192 0x0e
667 #define I2C_IFDR_DIV240 0x0f
668 #define I2C_IFDR_DIV288 0x10
669 #define I2C_IFDR_DIV320 0x11
670 #define I2C_IFDR_DIV384 0x12
671 #define I2C_IFDR_DIV480 0x13
672 #define I2C_IFDR_DIV576 0x14
673 #define I2C_IFDR_DIV640 0x15
674 #define I2C_IFDR_DIV768 0x16
675 #define I2C_IFDR_DIV960 0x17
676 #define I2C_IFDR_DIV1152 0x18
677 #define I2C_IFDR_DIV1280 0x19
678 #define I2C_IFDR_DIV1536 0x1a
679 #define I2C_IFDR_DIV1920 0x1b
680 #define I2C_IFDR_DIV2304 0x1c
681 #define I2C_IFDR_DIV2560 0x1d
682 #define I2C_IFDR_DIV3072 0x1e
683 #define I2C_IFDR_DIV3840 0x1f
684 #define I2C_IFDR_DIV22 0x20
685 #define I2C_IFDR_DIV24 0x21
686 #define I2C_IFDR_DIV26 0x22
687 #define I2C_IFDR_DIV28 0x23
688 #define I2C_IFDR_DIV32_2 0x24
689 #define I2C_IFDR_DIV36_2 0x25
690 #define I2C_IFDR_DIV40 0x26
691 #define I2C_IFDR_DIV44 0x27
692 #define I2C_IFDR_DIV48_2 0x28
693 #define I2C_IFDR_DIV56 0x29
694 #define I2C_IFDR_DIV64 0x2a
695 #define I2C_IFDR_DIV72_2 0x2b
696 #define I2C_IFDR_DIV80_2 0x2c
697 #define I2C_IFDR_DIV96 0x2d
698 #define I2C_IFDR_DIV112 0x2e
699 #define I2C_IFDR_DIV128_2 0x2f
700 #define I2C_IFDR_DIV160_2 0x30
701 #define I2C_IFDR_DIV192_2 0x31
702 #define I2C_IFDR_DIV224 0x32
703 #define I2C_IFDR_DIV256 0x33
704 #define I2C_IFDR_DIV320_2 0x34
705 #define I2C_IFDR_DIV384_2 0x35
706 #define I2C_IFDR_DIV448 0x36
707 #define I2C_IFDR_DIV512 0x37
708 #define I2C_IFDR_DIV640_2 0x38
709 #define I2C_IFDR_DIV768_2 0x39
710 #define I2C_IFDR_DIV896 0x3a
711 #define I2C_IFDR_DIV1024 0x3b
712 #define I2C_IFDR_DIV1280_2 0x3c
713 #define I2C_IFDR_DIV1536_2 0x3d
714 #define I2C_IFDR_DIV1792 0x3e
715 #define I2C_IFDR_DIV2048 0x3f
716
717 /* I2CR */
718 #define I2C_I2CR_IEN (1 << 7)
719 #define I2C_I2CR_IIEN (1 << 6)
720 #define I2C_I2CR_MSTA (1 << 5)
721 #define I2C_I2CR_MTX (1 << 4)
722 #define I2C_I2CR_TXAK (1 << 3)
723 #define I2C_I2CR_RSATA (1 << 2)
724
725 /* I2SR */
726 #define I2C_I2SR_ICF (1 << 7)
727 #define I2C_I2SR_IAAS (1 << 6)
728 #define I2C_I2SR_IBB (1 << 5)
729 #define I2C_I2SR_IAL (1 << 4)
730 #define I2C_I2SR_SRW (1 << 2)
731 #define I2C_I2SR_IIF (1 << 1)
732 #define I2C_I2SR_RXAK (1 << 0)
733
734 /* I2DR - [7:0] Data */
735
736 /* AUDMUX */
737 #define AUDMUX_PTCR1 (*(REG32_PTR_T)(AUDMUX_BASE+0x00))
738 #define AUDMUX_PDCR1 (*(REG32_PTR_T)(AUDMUX_BASE+0x04))
739 #define AUDMUX_PTCR2 (*(REG32_PTR_T)(AUDMUX_BASE+0x08))
740 #define AUDMUX_PDCR2 (*(REG32_PTR_T)(AUDMUX_BASE+0x0C))
741 #define AUDMUX_PTCR3 (*(REG32_PTR_T)(AUDMUX_BASE+0x10))
742 #define AUDMUX_PDCR3 (*(REG32_PTR_T)(AUDMUX_BASE+0x14))
743 #define AUDMUX_PTCR4 (*(REG32_PTR_T)(AUDMUX_BASE+0x18))
744 #define AUDMUX_PDCR4 (*(REG32_PTR_T)(AUDMUX_BASE+0x1C))
745 #define AUDMUX_PTCR5 (*(REG32_PTR_T)(AUDMUX_BASE+0x20))
746 #define AUDMUX_PDCR5 (*(REG32_PTR_T)(AUDMUX_BASE+0x24))
747 #define AUDMUX_PTCR6 (*(REG32_PTR_T)(AUDMUX_BASE+0x28))
748 #define AUDMUX_PDCR6 (*(REG32_PTR_T)(AUDMUX_BASE+0x2C))
749 #define AUDMUX_PTCR7 (*(REG32_PTR_T)(AUDMUX_BASE+0x30))
750 #define AUDMUX_PDCR7 (*(REG32_PTR_T)(AUDMUX_BASE+0x34))
751 #define AUDMUX_CNMCR (*(REG32_PTR_T)(AUDMUX_BASE+0x38))
752
753 #define AUDMUX_PTCR_TFS_DIR (1 << 31)
754
755 #define AUDMUX_PTCR_TFSEL (0xf << 27)
756 #define AUDMUX_PTCR_TFSEL_TXFS (0x0 << 27)
757 #define AUDMUX_PTCR_TFSEL_RXFS (0x8 << 27)
758 #define AUDMUX_PTCR_TFSEL_PORT1 (0x0 << 27)
759 #define AUDMUX_PTCR_TFSEL_PORT2 (0x1 << 27)
760 #define AUDMUX_PTCR_TFSEL_PORT3 (0x2 << 27)
761 #define AUDMUX_PTCR_TFSEL_PORT4 (0x3 << 27)
762 #define AUDMUX_PTCR_TFSEL_PORT5 (0x4 << 27)
763 #define AUDMUX_PTCR_TFSEL_PORT6 (0x5 << 27)
764 #define AUDMUX_PTCR_TFSEL_PORT7 (0x6 << 27)
765
766 #define AUDMUX_PTCR_TCLKDIR (1 << 26)
767
768 #define AUDMUX_PTCR_TCSEL (0xf << 22)
769 #define AUDMUX_PTCR_TCSEL_TXFS (0x0 << 22)
770 #define AUDMUX_PTCR_TCSEL_RXFS (0x8 << 22)
771 #define AUDMUX_PTCR_TCSEL_PORT1 (0x0 << 22)
772 #define AUDMUX_PTCR_TCSEL_PORT2 (0x1 << 22)
773 #define AUDMUX_PTCR_TCSEL_PORT3 (0x2 << 22)
774 #define AUDMUX_PTCR_TCSEL_PORT4 (0x3 << 22)
775 #define AUDMUX_PTCR_TCSEL_PORT5 (0x4 << 22)
776 #define AUDMUX_PTCR_TCSEL_PORT6 (0x5 << 22)
777 #define AUDMUX_PTCR_TCSEL_PORT7 (0x6 << 22)
778
779 #define AUDMUX_PTCR_RFS_DIR (1 << 21)
780
781 #define AUDMUX_PTCR_RFSSEL (0xf << 17)
782 #define AUDMUX_PTCR_RFSSEL_TXFS (0x0 << 17)
783 #define AUDMUX_PTCR_RFSSEL_RXFS (0x8 << 17)
784 #define AUDMUX_PTCR_RFSSEL_PORT1 (0x0 << 17)
785 #define AUDMUX_PTCR_RFSSEL_PORT2 (0x1 << 17)
786 #define AUDMUX_PTCR_RFSSEL_PORT3 (0x2 << 17)
787 #define AUDMUX_PTCR_RFSSEL_PORT4 (0x3 << 17)
788 #define AUDMUX_PTCR_RFSSEL_PORT5 (0x4 << 17)
789 #define AUDMUX_PTCR_RFSSEL_PORT6 (0x5 << 17)
790 #define AUDMUX_PTCR_RFSSEL_PORT7 (0x6 << 17)
791
792 #define AUDMUX_PTCR_RCLKDIR (1 << 16)
793
794 #define AUDMUX_PTCR_RCSEL (0xf << 12)
795 #define AUDMUX_PTCR_RCSEL_TXFS (0x0 << 12)
796 #define AUDMUX_PTCR_RCSEL_RXFS (0x8 << 12)
797 #define AUDMUX_PTCR_RCSEL_PORT1 (0x0 << 12)
798 #define AUDMUX_PTCR_RCSEL_PORT2 (0x1 << 12)
799 #define AUDMUX_PTCR_RCSEL_PORT3 (0x2 << 12)
800 #define AUDMUX_PTCR_RCSEL_PORT4 (0x3 << 12)
801 #define AUDMUX_PTCR_RCSEL_PORT5 (0x4 << 12)
802 #define AUDMUX_PTCR_RCSEL_PORT6 (0x5 << 12)
803 #define AUDMUX_PTCR_RCSEL_PORT7 (0x6 << 12)
804 #define AUDMUX_PTCR_SYN (1 << 11)
805
806 #define AUDMUX_PDCR_RXDSEL (0x7 << 13)
807 #define AUDMUX_PDCR_RXDSEL_PORT1 (0 << 13)
808 #define AUDMUX_PDCR_RXDSEL_PORT2 (1 << 13)
809 #define AUDMUX_PDCR_RXDSEL_PORT3 (2 << 13)
810 #define AUDMUX_PDCR_RXDSEL_PORT4 (3 << 13)
811 #define AUDMUX_PDCR_RXDSEL_PORT5 (4 << 13)
812 #define AUDMUX_PDCR_RXDSEL_PORT6 (5 << 13)
813 #define AUDMUX_PDCR_RXDSEL_PORT7 (6 << 13)
814 #define AUDMUX_PDCR_TXRXEN (1 << 12)
815
816 #define AUDMUX_CNMCR_BEN (1 << 18)
817 #define AUDMUX_CNMCR_FSPOL (1 << 17)
818 #define AUDMUX_CNMCR_CLKPOL (1 << 16)
819
820 #define AUDMUX_CNMCR_CNTHI (0xff << 8)
821 #define AUDMUX_CNMCR_CNTHI_POS (8)
822
823 #define AUDMUX_CNMCR_CNTLOW (0xff << 0)
824 #define AUDMUX_CNMCR_CNTLOW_POS (0)
825
826 /* SSI */
827 #define SSI_STX0_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x00))
828 #define SSI_STX1_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x04))
829 #define SSI_SRX0_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x08))
830 #define SSI_SRX1_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x0C))
831 #define SSI_SCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x10))
832 #define SSI_SISR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x14))
833 #define SSI_SIER1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x18))
834 #define SSI_STCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x1C))
835 #define SSI_SRCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x20))
836 #define SSI_STCCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x24))
837 #define SSI_SRCCR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x28))
838 #define SSI_SFCSR1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x2C))
839 #define SSI_SACNT1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x38))
840 #define SSI_SACADD1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x3C))
841 #define SSI_SACDAT1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x40))
842 #define SSI_SATAG1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x44))
843 #define SSI_STMSK1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x48))
844 #define SSI_SRMSK1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x4C))
845
846 #define SSI_STX0_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x00))
847 #define SSI_STX1_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x04))
848 #define SSI_SRX0_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x08))
849 #define SSI_SRX1_2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x0C))
850 #define SSI_SCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x10))
851 #define SSI_SISR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x14))
852 #define SSI_SIER2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x18))
853 #define SSI_STCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x1C))
854 #define SSI_SRCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x20))
855 #define SSI_STCCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x24))
856 #define SSI_SRCCR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x28))
857 #define SSI_SFCSR2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x2C))
858 #define SSI_SACNT2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x38))
859 #define SSI_SACADD2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x3C))
860 #define SSI_SACDAT2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x40))
861 #define SSI_SATAG2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x44))
862 #define SSI_STMSK2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x48))
863 #define SSI_SRMSK2 (*(REG32_PTR_T)(SSI2_BASE_ADDR+0x4C))
864
865 /* SSI SCR */
866 #define SSI_SCR_CLK_IST (0x1 << 9)
867 #define SSI_SCR_TCHN_EN (0x1 << 8)
868 #define SSI_SCR_SYS_CLK_EN (0x1 << 7)
869
870 #define SSI_SCR_I2S_MODE (0x3 << 5)
871 #define SSI_SCR_I2S_MODE_NORMAL (0x0 << 5)
872 #define SSI_SCR_I2S_MODE_MASTER (0x1 << 5)
873 #define SSI_SCR_I2S_MODE_SLAVE (0x2 << 5)
874 #define SSI_SCR_I2S_MODE_NOR2 (0x3 << 5)
875
876 #define SSI_SCR_SYN (0x1 << 4)
877 #define SSI_SCR_NET (0x1 << 3)
878 #define SSI_SCR_RE (0x1 << 2)
879 #define SSI_SCR_TE (0x1 << 1)
880 #define SSI_SCR_SSIEN (0x1 << 0)
881
882 /* SSI SISR */
883 #define SSI_SISR_CMDAU (0x1 << 18)
884 #define SSI_SISR_CMDDU (0x1 << 17)
885 #define SSI_SISR_RXT (0x1 << 16)
886 #define SSI_SISR_RDR1 (0x1 << 15)
887 #define SSI_SISR_RDR0 (0x1 << 14)
888 #define SSI_SISR_TDE1 (0x1 << 13)
889 #define SSI_SISR_TDE0 (0x1 << 12)
890 #define SSI_SISR_ROE1 (0x1 << 11)
891 #define SSI_SISR_ROE0 (0x1 << 10)
892 #define SSI_SISR_TUE1 (0x1 << 9)
893 #define SSI_SISR_TUE0 (0x1 << 8)
894 #define SSI_SISR_TFS (0x1 << 7)
895 #define SSI_SISR_RFS (0x1 << 6)
896 #define SSI_SISR_TLS (0x1 << 5)
897 #define SSI_SISR_RLS (0x1 << 4)
898 #define SSI_SISR_RFF1 (0x1 << 3)
899 #define SSI_SISR_RFF2 (0x1 << 2)
900 #define SSI_SISR_TFE1 (0x1 << 1)
901 #define SSI_SISR_TFE0 (0x1 << 0)
902
903 /* SSI SIER */
904 #define SSI_SIER_RDMAE (0x1 << 22)
905 #define SSI_SIER_RIE (0x1 << 21)
906 #define SSI_SIER_TDMAE (0x1 << 20)
907 #define SSI_SIER_TIE (0x1 << 19)
908 #define SSI_SIER_CMDAU (0x1 << 18)
909 #define SSI_SIER_CMDDU (0x1 << 17)
910 #define SSI_SIER_RXT (0x1 << 16)
911 #define SSI_SIER_RDR1 (0x1 << 15)
912 #define SSI_SIER_RDR0 (0x1 << 14)
913 #define SSI_SIER_TDE1 (0x1 << 13)
914 #define SSI_SIER_TDE0 (0x1 << 12)
915 #define SSI_SIER_ROE1 (0x1 << 11)
916 #define SSI_SIER_ROE0 (0x1 << 10)
917 #define SSI_SIER_TUE1 (0x1 << 9)
918 #define SSI_SIER_TUE0 (0x1 << 8)
919 #define SSI_SIER_TFS (0x1 << 7)
920 #define SSI_SIER_RFS (0x1 << 6)
921 #define SSI_SIER_TLS (0x1 << 5)
922 #define SSI_SIER_RLS (0x1 << 4)
923 #define SSI_SIER_RFF1 (0x1 << 3)
924 #define SSI_SIER_RFF0 (0x1 << 2)
925 #define SSI_SIER_TFE1 (0x1 << 1)
926 #define SSI_SIER_TFE0 (0x1 << 0)
927
928 /* SSI STCR */
929 #define SSI_STCR_TXBIT0 (0x1 << 9)
930 #define SSI_STCR_TFEN1 (0x1 << 8)
931 #define SSI_STCR_TFEN0 (0x1 << 7)
932 #define SSI_STCR_TFDIR (0x1 << 6)
933 #define SSI_STCR_TXDIR (0x1 << 5)
934 #define SSI_STCR_TSHFD (0x1 << 4)
935 #define SSI_STCR_TSCKP (0x1 << 3)
936 #define SSI_STCR_TFSI (0x1 << 2)
937 #define SSI_STCR_TFSL (0x1 << 1)
938 #define SSI_STCR_TEFS (0x1 << 0)
939
940 /* SSI SRCR */
941 #define SSI_SRCR_RXEXT (0x1 << 10)
942 #define SSI_SRCR_RXBIT0 (0x1 << 9)
943 #define SSI_SRCR_RFEN1 (0x1 << 8)
944 #define SSI_SRCR_RFEN0 (0x1 << 7)
945 #define SSI_SRCR_RFDIR (0x1 << 6)
946 #define SSI_SRCR_RXDIR (0x1 << 5)
947 #define SSI_SRCR_RSHFD (0x1 << 4)
948 #define SSI_SRCR_RSCKP (0x1 << 3)
949 #define SSI_SRCR_RFSI (0x1 << 2)
950 #define SSI_SRCR_RFSL (0x1 << 1)
951 #define SSI_SRCR_REFS (0x1 << 0)
952
953 /* SSI STCCR/SRCCR */
954 #define SSI_STRCCR_DIV2 (0x1 << 18)
955 #define SSI_STRCCR_PSR (0x1 << 17)
956
957 #define SSI_STRCCR_WL (0xf << 13)
958 #define SSI_STRCCR_WL8 (0x3 << 13)
959 #define SSI_STRCCR_WL10 (0x4 << 13)
960 #define SSI_STRCCR_WL12 (0x5 << 13)
961 #define SSI_STRCCR_WL16 (0x7 << 13)
962 #define SSI_STRCCR_WL18 (0x8 << 13)
963 #define SSI_STRCCR_WL20 (0x9 << 13)
964 #define SSI_STRCCR_WL22 (0xa << 13)
965 #define SSI_STRCCR_WL24 (0xb << 13)
966
967 #define SSI_STRCCR_DC (0x1f << 8)
968 #define SSI_STRCCR_DC_POS (8)
969
970 #define SSI_STRCCR_PM (0xf << 0)
971 #define SSI_STRCCR_PM_POS (0)
972
973 /* SSI SFCSR */
974 #define SSI_SFCSR_RFCNT1 (0xf << 28)
975 #define SSI_SFCSR_RFCNT1_POS (28)
976
977 #define SSI_SFCSR_TFCNT1 (0xf << 24)
978 #define SSI_SFCSR_TFCNN1_POS (24)
979
980 #define SSI_SFCSR_RFWM1 (0xf << 20)
981 #define SSI_SFCSR_RFWM1_POS (20)
982
983 #define SSI_SFCSR_TFWM1 (0xf << 16)
984 #define SSI_SFCSR_TFWM1_POS (16)
985
986 #define SSI_SFCSR_RFCNT0 (0xf << 12)
987 #define SSI_SFCSR_RFCNT0_POS (12)
988
989 #define SSI_SFCSR_TFCNT0 (0xf << 8)
990 #define SSI_SFCSR_TFCNT0_POS (8)
991
992 #define SSI_SFCSR_RFWM0 (0xf << 4)
993 #define SSI_SFCSR_RFWM0_POS (4)
994
995 #define SSI_SFCSR_TFWM0 (0xf << 0)
996 #define SSI_SFCSR_TFWM0_POS (0)
997
998 /* SACNT */
999 #define SSI_SACNT_FRDIV (0x3f << 5)
1000 #define SSI_SACNT_FRDIV_POS (5)
1001
1002 #define SSI_SACNT_WR (0x1 << 4)
1003 #define SSI_SACNT_RD (0x1 << 3)
1004 #define SSI_SACNT_TIF (0x1 << 2)
1005 #define SSI_SACNT_FV (0x1 << 1)
1006 #define SSI_SACNT_AC97EN (0x1 << 0)
1007
1008 /* RTC */
1009 #define RTC_HOURMIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00))
1010 #define RTC_SECONDS (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04))
1011 #define RTC_ALRM_HM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x08))
1012 #define RTC_ALRM_SEC (*(REG32_PTR_T)(RTC_BASE_ADDR+0x0C))
1013 #define RTC_CTL (*(REG32_PTR_T)(RTC_BASE_ADDR+0x10))
1014 #define RTC_ISR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x14))
1015 #define RTC_IENR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x18))
1016 #define RTC_STPWCH (*(REG32_PTR_T)(RTC_BASE_ADDR+0x1C))
1017 #define RTC_DAYR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x20))
1018 #define RTC_DAYALARM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x24))
1019
1020 /* Watchdog */
1021 #define WDOG_WCR (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x00))
1022 #define WDOG_WSR (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x02))
1023 #define WDOG_WRSR (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x04))
1024
1025 #define WDOG_WCR_WT (0xff << 8)
1026 #define WDOG_WCR_WT_POS (8)
1027
1028 #define WDOG_WCR_WOE (0x1 << 6)
1029 #define WDOG_WCR_WDA (0x1 << 5)
1030 #define WDOG_WCR_SRS (0x1 << 4)
1031 #define WDOG_WCR_WRE (0x1 << 3)
1032 #define WDOG_WCR_WDE (0x1 << 2)
1033 #define WDOG_WCR_WDBG (0x1 << 1)
1034 #define WDOG_WCR_WDZST (0x1 << 0)
1035
1036 #define WDOG_WRSR_JRST (0x1 << 5)
1037 #define WDOG_WRSR_PWR (0x1 << 4)
1038 #define WDOG_WRSR_EXT (0x1 << 3)
1039 #define WDOG_WRSR_CMON (0x1 << 2)
1040 #define WDOG_WRSR_TOUT (0x1 << 1)
1041 #define WDOG_WRSR_SFTW (0x1 << 0)
1042
1043 /* Keypad */
1044 #define KPP_KPCR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x0))
1045 #define KPP_KPSR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x2))
1046 #define KPP_KDDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x4))
1047 #define KPP_KPDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x6))
1048
1049 /* KPP_KPSR bits */
1050 #define KPP_KPSR_KRIE (1 << 9)
1051 #define KPP_KPSR_KDIE (1 << 8)
1052 #define KPP_KPSR_KRSS (1 << 3)
1053 #define KPP_KPSR_KDSC (1 << 2)
1054 #define KPP_KPSR_KPKR (1 << 1)
1055 #define KPP_KPSR_KPKD (1 << 0)
1056
1057 /* SDHC */
1058 #define SDHC1_CLOCK_CONTROL (*(REG32_PTR_T)(MMC_SDHC1_BASE_ADDR+0x00))
1059 #define SDHC2_CLOCK_CONTROL (*(REG32_PTR_T)(MMC_SDHC2_BASE_ADDR+0x00))
1060
1061 /* SDHC bits */
1062 #define STOP_CLK (1 << 0)
1063
1064 /* ROMPATCH and AVIC */
1065 #define ROMPATCH_BASE_ADDR 0x60000000
1066
1067 /* Since AVIC vector registers are NOT used, we reserve some for various
1068 * purposes. Copied from Linux source code. */
1069 #define CHIP_REV_1_0 0x10
1070 #define CHIP_REV_2_0 0x20
1071 #define SYSTEM_REV_ID_REG (AVIC_BASE_ADDR + AVIC_VEC_1)
1072 #define SYSTEM_REV_ID_MAG 0xF00C
1073
1074 /*
1075 * NAND, SDRAM, WEIM, M3IF, EMI controllers
1076 */
1077 #define EXT_MEM_CTRL_BASE 0xB8000000
1078 #define NFC_BASE EXT_MEM_CTRL_BASE
1079 #define ESDCTL_BASE 0xB8001000
1080 #define WEIM_BASE_ADDR 0xB8002000
1081 #define WEIM_CTRL_CS0 (WEIM_BASE_ADDR+0x00)
1082 #define WEIM_CTRL_CS1 (WEIM_BASE_ADDR+0x10)
1083 #define WEIM_CTRL_CS2 (WEIM_BASE_ADDR+0x20)
1084 #define WEIM_CTRL_CS3 (WEIM_BASE_ADDR+0x30)
1085 #define WEIM_CTRL_CS4 (WEIM_BASE_ADDR+0x40)
1086 #define M3IF_BASE 0xB8003000
1087 #define PCMCIA_CTL_BASE 0xB8004000
1088
1089 /*
1090 * Memory regions and CS
1091 */
1092 #define IPU_MEM_BASE_ADDR 0x70000000
1093 #define CSD0_BASE_ADDR 0x80000000
1094 #define CSD1_BASE_ADDR 0x90000000
1095 #define CS0_BASE_ADDR 0xA0000000
1096 #define CS1_BASE_ADDR 0xA8000000
1097 #define CS2_BASE_ADDR 0xB0000000
1098 #define CS3_BASE_ADDR 0xB2000000
1099 #define CS4_BASE_ADDR 0xB4000000
1100 #define CS4_BASE_PSRAM 0xB5000000
1101 #define CS5_BASE_ADDR 0xB6000000
1102 #define PCMCIA_MEM_BASE_ADDR 0xC0000000
1103
1104 #define INTERNAL_ROM_VA 0xF0000000
1105
1106 /*
1107 * SDRAM
1108 */
1109 #define RAM_BANK0_BASE SDRAM_BASE_ADDR
1110
1111 /*
1112 * IRQ Controller Register Definitions.
1113 */
1114 #define AVIC_BASE_ADDR 0x68000000
1115 #define AVIC_INTCNTL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00))
1116 #define AVIC_NIMASK (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04))
1117 #define AVIC_INTENNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08))
1118 #define AVIC_INTDISNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C))
1119 #define AVIC_INTENABLEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10))
1120 #define AVIC_INTENABLEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14))
1121 #define AVIC_INTTYPEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18))
1122 #define AVIC_INTTYPEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C))
1123 #define AVIC_NIPRIORITY(n) (((REG32_PTR_T)(AVIC_BASE_ADDR+0x20))[n])
1124 #define AVIC_NIPRIORITY7 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20))
1125 #define AVIC_NIPRIORITY6 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24))
1126 #define AVIC_NIPRIORITY5 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28))
1127 #define AVIC_NIPRIORITY4 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C))
1128 #define AVIC_NIPRIORITY3 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30))
1129 #define AVIC_NIPRIORITY2 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34))
1130 #define AVIC_NIPRIORITY1 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38))
1131 #define AVIC_NIPRIORITY0 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C))
1132 #define AVIC_NIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40))
1133 #define AVIC_FIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44))
1134 #define AVIC_INTSRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48))
1135 #define AVIC_INTSRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C))
1136 #define AVIC_INTFRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50))
1137 #define AVIC_INTFRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54))
1138 #define AVIC_NIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58))
1139 #define AVIC_NIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C))
1140 #define AVIC_FIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60))
1141 #define AVIC_FIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64))
1142 #define AVIC_VECTOR_BASE_ADDR (AVIC_BASE_ADDR+0x100)
1143 #define AVIC_VECTOR(n) (((REG32_PTR_T)VECTOR_BASE_ADDR)[n])
1144
1145 /* The vectors go all the way up to 63. 4 bytes for each */
1146 #define AVIC_INTCNTL_ABFLAG (1 << 25)
1147 #define AVIC_INTCNTL_ABFEN (1 << 24)
1148 #define AVIC_INTCNTL_NIDIS (1 << 22)
1149 #define AVIC_INTCNTL_FIDIS (1 << 21)
1150 #define AVIC_INTCNTL_NIAD (1 << 20)
1151 #define AVIC_INTCNTL_FIAD (1 << 19)
1152 #define AVIC_INTCNTL_NM (1 << 18)
1153
1154 /* L210 */
1155 #define L2CC_BASE_ADDR 0x30000000
1156 #define L2_CACHE_LINE_SIZE 32
1157 #define L2_CACHE_CTL_REG 0x100
1158 #define L2_CACHE_AUX_CTL_REG 0x104
1159 #define L2_CACHE_SYNC_REG 0x730
1160 #define L2_CACHE_INV_LINE_REG 0x770
1161 #define L2_CACHE_INV_WAY_REG 0x77C
1162 #define L2_CACHE_CLEAN_LINE_REG 0x7B0
1163 #define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
1164
1165 #define L2CC_CACHE_SYNC (*(REG32_PTR_T)(L2CC_BASE_ADDR+L2_CACHE_SYNC_REG))
1166
1167 /* CCM */
1168 #define CCM_CCMR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00))
1169 #define CCM_PDR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04))
1170 #define CCM_PDR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08))
1171 #define CCM_RCSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C))
1172 #define CCM_MPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10))
1173 #define CCM_UPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14))
1174 #define CCM_SPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18))
1175 #define CCM_COSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C))
1176 #define CCM_CGR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20))
1177 #define CCM_CGR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24))
1178 #define CCM_CGR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28))
1179 #define CCM_WIMR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C))
1180 #define CCM_LDC (*(REG32_PTR_T)(CCM_BASE_ADDR+0x30))
1181 #define CCM_DCVR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x34))
1182 #define CCM_DCVR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x38))
1183 #define CCM_DCVR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x3C))
1184 #define CCM_DCVR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x40))
1185 #define CCM_LTR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x44))
1186 #define CCM_LTR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x48))
1187 #define CCM_LTR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x4C))
1188 #define CCM_LTR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x50))
1189 #define CCM_LTBR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x54))
1190 #define CCM_LTBR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x58))
1191 #define CCM_PMCR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C))
1192 #define CCM_PMCR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60))
1193 #define CCM_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64))
1194
1195 /* CCMR */
1196 #define CCM_CCMR_L2PG (0x1 << 29)
1197 #define CCM_CCMR_VSTBY (0x1 << 28)
1198 #define CCM_CCMR_WBEN (0x1 << 27)
1199 #define CCM_CCMR_FPMF (0x1 << 26)
1200 #define CCM_CCMR_CSCS (0x1 << 25)
1201 #define CCM_CCMR_PERCS (0x1 << 24)
1202
1203 #define CCM_CCMR_SSI2S (0x3 << 21)
1204 #define CCM_CCMR_SSI2S_MCU_CLK (0x0 << 21)
1205 #define CCM_CCMR_SSI2S_USB_CLK (0x1 << 21)
1206 #define CCM_CCMR_SSI2S_SERIAL_CLK (0x2 << 21) /* default */
1207
1208 #define CCM_CCMR_SSI1S (0x3 << 18)
1209 #define CCM_CCMR_SSI1S_MCU_CLK (0x0 << 18)
1210 #define CCM_CCMR_SSI1S_USB_CLK (0x1 << 18)
1211 #define CCM_CCMR_SSI1S_SERIAL_CLK (0x2 << 18) /* default */
1212
1213 #define CCM_CCMR_RAMW (0x3 << 16)
1214 #define CCM_CCMR_RAMW_0ARM_0ALTMS (0x0 << 16)
1215 #define CCM_CCMR_RAMW_0ARM_1ALTMS (0x1 << 16) /* Not recommended */
1216 #define CCM_CCMR_RAMW_1ARM_0ALTMS (0x2 << 16) /* Not recommended */
1217 #define CCM_CCMR_RAMW_1ARM_1ALTMS (0x3 << 16)
1218
1219 #define CCM_CCMR_LPM (0x3 << 14)
1220 #define CCM_CCMR_LPM_WAIT_MODE (0x0 << 14)
1221 #define CCM_CCMR_LPM_DOZE_MODE (0x1 << 14)
1222 #define CCM_CCMR_LPM_SRM (0x2 << 14) /* State retention mode */
1223 #define CCM_CCMR_LPM_DSM (0x3 << 14) /* Deep sleep mode */
1224
1225 #define CCM_CCMR_FIRS (0x3 << 11)
1226 #define CCM_CCMR_FIRS_MCU_CLK (0x0 << 11)
1227 #define CCM_CCMR_FIRS_USB_CLK (0x1 << 11)
1228 #define CCM_CCMR_FIRS_SERIAL_CLK (0x2 << 11)
1229
1230 #define CCM_CCMR_WAMO (0x1 << 10)
1231 #define CCM_CCMR_UPE (0x1 << 9)
1232 #define CCM_CCMR_SPE (0x1 << 8)
1233 #define CCM_CCMR_MDS (0x1 << 7)
1234
1235 #define CCM_CCMR_ROMW (0x3 << 5)
1236 #define CCM_CCMR_ROMW_0ARM_0ALTMS (0x0 << 5)
1237 #define CCM_CCMR_ROMW_0ARM_1ALTMS (0x1 << 5) /* Not recommended */
1238 #define CCM_CCMR_ROMW_1ARM_0ALTMS (0x2 << 5) /* Not recommended */
1239 #define CCM_CCMR_ROMW_1ARM_1ALTMS (0x3 << 5)
1240
1241 #define CCM_CCMR_SBYCS (0x1 << 4)
1242 #define CCM_CCMR_MPE (0x1 << 3)
1243
1244 #define CCM_CCMR_PRCS (0x3 << 1)
1245 #define CCM_CCMR_PRCS_FPM (0x1 << 1)
1246 #define CCM_CCMR_PRCS_CKIH (0x2 << 1)
1247
1248 #define CCM_CCMR_FPME (0x1 << 0)
1249
1250 /* PDR0 */
1251 #define CCM_PDR0_CSI_PODF (0x1ff << 23)
1252 #define CCM_PDR0_CSI_PODF_POS (23)
1253
1254 #define CCM_PDR0_PER_PODF (0x1f << 16)
1255 #define CCM_PDR0_PER_PODF_POS (16)
1256
1257 #define CCM_PDR0_HSP_PODF (0x7 << 11)
1258 #define CCM_PDR0_HSP_PODF_POS (11)
1259
1260 #define CCM_PDR0_NFC_PODF (0x7 << 8)
1261 #define CCM_PDR0_NFC_PODF_POS (8)
1262
1263 #define CCM_PDR0_IPG_PODF (0x3 << 6)
1264 #define CCM_PDR0_IPG_PODF_POS (6)
1265
1266 #define CCM_PDR0_MAX_PODF (0x7 << 3)
1267 #define CCM_PDR0_MAX_PODF_POS (3)
1268
1269 #define CCM_PDR0_MCU_PODF (0x7 << 0)
1270 #define CCM_PDR0_MCU_PODF_POS (0)
1271
1272 /* PDR1 */
1273 #define CCM_PDR1_USB_PRDF (0x3 << 30)
1274 #define CCM_PDR1_USB_PRDF_POS (30)
1275
1276 #define CCM_PDR1_USB_PODF (0x7 << 27)
1277 #define CCM_PDR1_USB_PODF_POS (27)
1278
1279 #define CCM_PDR1_FIRI_PRE_PODF (0x7 << 24)
1280 #define CCM_PDR1_FIRI_PRE_PODF_POS (24)
1281
1282 #define CCM_PDR1_FIRI_PODF (0x3f << 18)
1283 #define CCM_PDR1_FIRI_PODF_POS (18)
1284
1285 #define CCM_PDR1_SSI2_PRE_PODF (0x7 << 15)
1286 #define CCM_PDR1_SSI2_PRE_PODF_POS (15)
1287
1288 #define CCM_PDR1_SSI2_PODF (0x3f << 9)
1289 #define CCM_PDR1_SSI2_PODF_POS (9)
1290
1291 #define CCM_PDR1_SSI1_PRE_PODF (0x7 << 6)
1292 #define CCM_PDR1_SSI1_PRE_PODF_POS (6)
1293
1294 #define CCM_PDR1_SSI1_PODF (0x3f << 0)
1295 #define CCM_PDR1_SSI1_PODF_POS (0)
1296
1297 /* RCSR */
1298 #define CCM_RCSR_NF16B (1 << 31)
1299
1300 #define CCM_RCSR_NFMS (1 << 30)
1301
1302 #define CCM_RCSR_BTP4 (1 << 27)
1303 #define CCM_RCSR_BTP3 (1 << 26)
1304 #define CCM_RCSR_BTP2 (1 << 25)
1305 #define CCM_RCSR_BTP1 (1 << 24)
1306 #define CCM_RCSR_BTP0 (1 << 23)
1307
1308 #define CCM_RCSR_OSCNT (0x7f << 16)
1309 #define CCM_RCSR_OSCNT_POS (16)
1310
1311 #define CCM_RCSR_PERES (1 << 15)
1312
1313 #define CCM_RCSR_SDM (0x3 << 12)
1314 #define CCM_RCSR_SDM_POS (12)
1315
1316 #define CCM_RCSR_GPF (0x7 << 5)
1317 #define CCM_RCSR_GPF_POS (5)
1318
1319 #define CCM_RCSR_WFIS (1 << 4)
1320
1321 #define CCM_RCSR_REST (0x7 << 0)
1322 #define CCM_RCSR_REST_POS (0)
1323 #define CCM_RCSR_REST_POR_EXT (0x0)
1324 #define CCM_RCSR_REST_QUALIFIED_EXT (0x1)
1325 #define CCM_RCSR_REST_WATCHDOG_TMO (0x2)
1326 /* 0x3 - 0x5: reserved */
1327 #define CCM_RCSR_REST_JTAG (0x6)
1328 #define CCM_RCSR_REST_ARM11P_GATING (0x7)
1329
1330 /* MPCTL */
1331 #define CCM_MPCTL_BRM (1 << 31)
1332 #define CCM_MPCTL_PD (0xf << 26)
1333 #define CCM_MPCTL_PD_POS (26)
1334 #define CCM_MPCTL_MFD (0x3ff << 16)
1335 #define CCM_MPCTL_MFD_POS (16)
1336 #define CCM_MPCTL_MFI (0xf << 10)
1337 #define CCM_MPCTL_MFI_POS (10)
1338 #define CCM_MPCTL_MFN (0x3ff << 0)
1339 #define CCM_MPCTL_MFN_POS (0)
1340
1341 /* UPCTL */
1342 #define CCM_UPCTL_BRM (1 << 31)
1343 #define CCM_UPCTL_PD (0xf << 26)
1344 #define CCM_UPCTL_PD_POS (26)
1345 #define CCM_UPCTL_MFD (0x3ff << 16)
1346 #define CCM_UPCTL_MFD_POS (16)
1347 #define CCM_UPCTL_MFI (0xf << 10)
1348 #define CCM_UPCTL_MFI_POS (10)
1349 #define CCM_UPCTL_MFN (0x3ff << 0)
1350 #define CCM_UPCTL_MFN_POS (0)
1351
1352 /* SPCTL */
1353 #define CCM_SPCTL_BRM (1 << 31)
1354 #define CCM_SPCTL_PD (0xf << 26)
1355 #define CCM_SPCTL_PD_POS (26)
1356 #define CCM_SPCTL_MFD (0x3ff << 16)
1357 #define CCM_SPCTL_MFD_POS (16)
1358 #define CCM_SPCTL_MFI (0xf << 10)
1359 #define CCM_SPCTL_MFI_POS (10)
1360 #define CCM_SPCTL_MFN (0x3ff << 0)
1361 #define CCM_SPCTL_MFN_POS (0)
1362
1363 /* COSR */
1364 #define CCM_COSR_CLKOEN (1 << 9)
1365 #define CCM_COSR_CLKOUTDIV (0x7 << 6)
1366 #define CCM_COSR_CLKOUTDIV_POS (6)
1367 #define CCM_COSR_CLKOSEL (0xf << 0)
1368 #define CCM_COSR_CLKOSEL_POS (0)
1369 #define CCM_COSR_CLKOSEL_MPL_DPDGCK_CLK (0x0)
1370 #define CCM_COSR_CLKOSEL_IPG_CLK_CCM (0x1)
1371 #define CCM_COSR_CLKOSEL_UPL_DPDGCK_CLK (0x2)
1372 #define CCM_COSR_CLKOSEL_PLL_REF_CLK (0x3)
1373 #define CCM_COSR_CLKOSEL_FPM_CKIL512_CLK (0x4)
1374 #define CCM_COSR_CLKOSEL_IPG_CLK_AHB_ARM (0x5)
1375 #define CCM_COSR_CLKOSEL_IPG_CLK_ARM (0x6)
1376 #define CCM_COSR_CLKOSEL_SPL_DPDGCK_CLK (0x7)
1377 #define CCM_COSR_CLKOSEL_CKIH (0x8)
1378 #define CCM_COSR_CLKOSEL_IPG_CLK_AHB_EMI_CLK (0x9)
1379 #define CCM_COSR_CLKOSEL_IPG_CLK_IPU_HSP (0x9)
1380 #define CCM_COSR_CLKOSEL_IPG_CLK_NFC_20M (0xa)
1381 #define CCM_COSR_CLKOSEL_IPG_CLK_PERCLK_UART1 (0xb)
1382 #define CCM_COSR_CLKOSEL_IPG_REF_CIR1 (0xc) /* ref_cir_gateload */
1383 #define CCM_COSR_CLKOSEL_IPG_REF_CIR2 (0xc) /* ref_cir_intrcload */
1384 #define CCM_COSR_CLKOSEL_IPG_REF_CIR3 (0xc) /* ref_cir_path */
1385
1386 /* CGR0 */
1387 /* CGR1 */
1388 /* CGR2 */
1389 /* Handled in ccm-imx31.h and ccm-imx31.c */
1390
1391
1392 #define CCM_WIMR0_GPIO3 (1 << 0)
1393 #define CCM_WIMR0_GPIO2 (1 << 1)
1394 #define CCM_WIMR0_GPIO1 (1 << 2)
1395 #define CCM_WIMR0_PCMCIA (1 << 3)
1396 #define CCM_WIMR0_WDT (1 << 4)
1397 #define CCM_WIMR0_USB_OTG (1 << 5)
1398 #define CCM_WIMR0_IPI_INT_UH2 (1 << 6)
1399 #define CCM_WIMR0_IPI_INT_UH1 (1 << 7)
1400 #define CCM_WIMR0_IPI_INT_UART5_ANDED (1 << 8)
1401 #define CCM_WIMR0_IPI_INT_UART4_ANDED (1 << 9)
1402 #define CCM_WIMR0_IPI_INT_UART3_ANDED (1 << 10)
1403 #define CCM_WIMR0_IPI_INT_UART2_ANDED (1 << 11)
1404 #define CCM_WIMR0_IPI_INT_UART1_ANDED (1 << 12)
1405 #define CCM_WIMR0_IPI_INT_SIM_DATA_IRQ (1 << 13)
1406 #define CCM_WIMR0_IPI_INT_SDHC2 (1 << 14)
1407 #define CCM_WIMR0_IPI_INT_SDHC1 (1 << 15)
1408 #define CCM_WIMR0_IPI_INT_RTC (1 << 16)
1409 #define CCM_WIMR0_IPI_INT_PWM (1 << 17)
1410 #define CCM_WIMR0_IPI_INT_KPP (1 << 18)
1411 #define CCM_WIMR0_IPI_INT_IIM (1 << 19)
1412 #define CCM_WIMR0_IPI_INT_GPT (1 << 20)
1413 #define CCM_WIMR0_IPI_INT_FIR (1 << 21)
1414 #define CCM_WIMR0_IPI_INT_EPIT2 (1 << 22)
1415 #define CCM_WIMR0_IPI_INT_EPIT1 (1 << 23)
1416 #define CCM_WIMR0_IPI_INT_CSPI2 (1 << 24)
1417 #define CCM_WIMR0_IPI_INT_CSPI1 (1 << 25)
1418 #define CCM_WIMR0_IPI_INT_POWER_FAIL (1 << 26)
1419 #define CCM_WIMR0_IPI_INT_CSPI3 (1 << 27)
1420 #define CCM_WIMR0_RESERVED28 (1 << 28)
1421 #define CCM_WIMR0_RESERVED29 (1 << 29)
1422 #define CCM_WIMR0_RESERVED30 (1 << 30)
1423 #define CCM_WIMR0_RESERVED31 (1 << 31)
1424
1425 /* LDC */
1426 /* 32 bits specify value */
1427
1428 /* DCVR0-DCVR3 */
1429 #define CCM_DCVR_ULV (0x3ff << 22) /* Upper limit */
1430 #define CCM_DCVR_ULV_POS (22)
1431 #define CCM_DCVR_LLV (0x3ff << 12) /* Lower limit */
1432 #define CCM_DCVR_LLV_POS (12)
1433 #define CCM_DCVR_ELV (0x3ff << 2) /* Emergency limit */
1434 #define CCM_DCVR_ELV_POS (2)
1435
1436
1437 /* LTR0 */
1438 #define CCM_LTR0_UPTHR (0x3f << 22)
1439 #define CCM_LTR0_UPTHR_POS (22)
1440 #define CCM_LTR0_DNTHR (0x3f << 16)
1441 #define CCM_LTR0_DNTHR_POS (16)
1442 /* for div_3_clk */
1443 #define CCM_LTR0_DIV3CK (0x3 << 1)
1444 #define CCM_LTR0_DIV3CK_POS (1)
1445 #define CCM_LTR0_DIV3CK_2048 (0x0 << 1) /* 1/2048 ARM clock */
1446 #define CCM_LTR0_DIV3CK_8192 (0x1 << 1) /* 1/8192 ARM clock */
1447 #define CCM_LTR0_DIV3CK_32768 (0x2 << 1) /* 1/32768 ARM clock */
1448 #define CCM_LTR0_DIV3CK_131072 (0x3 << 1) /* 1/131072 ARM clock */
1449
1450 /* LTR1 */
1451 #define CCM_LTR1_LTBRSH (1 << 23)
1452 #define CCM_LTR1_LTBRSR (1 << 22)
1453 #define CCM_LTR1_DNCNT (0xff << 14)
1454 #define CCM_LTR1_DNCNT_POS (14)
1455 #define CCM_LTR1_UPCNT (0xff << 6)
1456 #define CCM_LTR1_UPCNT_POS (6)
1457 #define CCM_LTR1_PNCTHR (0x3f << 0)
1458 #define CCM_LTR1_PNCTHR_POS (0)
1459
1460 /* LTR2 */
1461 #define CCM_LTR2_EMAC (0x1ff)
1462 #define CCM_LTR2_EMAC_POS (0)
1463
1464 /* PMCR0 */
1465 #define CCM_PMCR0_DFSUP_MCUPLL (1 << 31)
1466 #define CCM_PMCR0_DFSUP_MCUPLL_POS (31)
1467 #define CCM_PMCR0_DFSUP_POST_DIVIDERS (1 << 30)
1468 #define CCM_PMCR0_DVSUP (0x3 << 28)
1469 #define CCM_PMCR0_DVSUP_POS (28)
1470 #define CCM_PMCR0_UDSC (1 << 27)
1471 #define CCM_PMCR0_VSCNT (0x7 << 24)
1472 #define CCM_PMCR0_VSCNT_POS (24)
1473 #define CCM_PMCR0_DVFEV (1 << 23)
1474 #define CCM_PMCR0_DVFIS (1 << 22)
1475 #define CCM_PMCR0_LBMI (1 << 21)
1476 #define CCM_PMCR0_LBFL (1 << 20)
1477 #define CCM_PMCR0_LBCF (0x3 << 18)
1478 #define CCM_PMCR0_LBCF_4 (0x0 << 18)
1479 #define CCM_PMCR0_LBCF_8 (0x1 << 18)
1480 #define CCM_PMCR0_LBCF_12 (0x2 << 18)
1481 #define CCM_PMCR0_LBCF_16 (0x3 << 18)
1482 #define CCM_PMCR0_PTVIS (1 << 17)
1483 #define CCM_PMCR0_UPDTEN (1 << 16)
1484 #define CCM_PMCR0_FSVAIM (1 << 15)
1485 #define CCM_PMCR0_FSVAI (0x3 << 13)
1486 #define CCM_PMCR0_FSVAI_NO_INT (0x0 << 13)
1487 #define CCM_PMCR0_FSVAI_INCREASE (0x1 << 13)
1488 #define CCM_PMCR0_FSVAI_DECREASE (0x2 << 13)
1489 #define CCM_PMCR0_FSVAI_INCREASE_NOW (0x3 << 13)
1490 #define CCM_PMCR0_FSVAI_POS (13)
1491 #define CCM_PMCR0_DPVCR (1 << 12)
1492 #define CCM_PMCR0_DPVV (1 << 11)
1493 #define CCM_PMCR0_WFIM (1 << 10)
1494 #define CCM_PMCR0_DRCE3 (1 << 9)
1495 #define CCM_PMCR0_DRCE2 (1 << 8)
1496 #define CCM_PMCR0_DRCE1 (1 << 7)
1497 #define CCM_PMCR0_DRCE0 (1 << 6)
1498 #define CCM_PMCR0_DCR (1 << 5) /* 512 vs 256 count */
1499 #define CCM_PMCR0_DVFEN (1 << 4)
1500 #define CCM_PMCR0_PTVAIM (1 << 3)
1501 #define CCM_PMCR0_PTVAI (0x3 << 1)
1502 #define CCM_PMCR0_PTVAI_NO_INT (0x0 << 1)
1503 #define CCM_PMCR0_PTVAI_DECREASE (0x1 << 1)
1504 #define CCM_PMCR0_PTVAI_INCREASE (0x2 << 1)
1505 #define CCM_PMCR0_PTVAI_INCREASE_NOW (0x3 << 1)
1506 #define CCM_PMCR0_DPTEN (1 << 0)
1507
1508
1509 /* PMCR1 */
1510 #define CCM_PMCR1_DVGP_POS (0)
1511 #define CCM_PMCR1_DVGP_MASK (0xf << 0)
1512
1513 /* IC revision 2.0 or greater ONLY! */
1514 #define CCM_PMCR1_EMIRQ_EN (1 << 8)
1515 #define CCM_PMCR1_PLLRDIS (1 << 7) /* No PLL reset on switch */
1516
1517
1518 /* WEIM - CS0 */
1519 #define CSCRU 0x00
1520 #define CSCRL 0x04
1521 #define CSCRA 0x08
1522
1523 /* ESDCTL */
1524 #define ESDCTL_ESDCTL0 0x00
1525 #define ESDCTL_ESDCFG0 0x04
1526 #define ESDCTL_ESDCTL1 0x08
1527 #define ESDCTL_ESDCFG1 0x0C
1528 #define ESDCTL_ESDMISC 0x10
1529
1530 /* More UART 1 Register defines */
1531 #define URXD1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x00))
1532 #define UTXD1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x40))
1533 #define UCR1_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x80))
1534 #define UCR2_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x84))
1535 #define UCR3_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x88))
1536 #define UCR4_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x8C))
1537 #define UFCR1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x90))
1538 #define USR1_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x94))
1539 #define USR2_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x98))
1540 #define UTS1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0xB4))
1541
1542 #define UCR1_2 (*(REG32_PTR_T)(UART2_BASE_ADDR+0x80))
1543 #define UCR1_3 (*(REG32_PTR_T)(UART3_BASE_ADDR+0x80))
1544 #define UCR1_4 (*(REG32_PTR_T)(UART4_BASE_ADDR+0x80))
1545 #define UCR1_5 (*(REG32_PTR_T)(UART5_BASE_ADDR+0x80))
1546
1547 /*
1548 * UART Control Register 0 Bit Fields.
1549 */
1550 #define EUARTUCR1_ADEN (1 << 15) // Auto detect interrupt
1551 #define EUARTUCR1_ADBR (1 << 14) // Auto detect baud rate
1552 #define EUARTUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
1553 #define EUARTUCR1_IDEN (1 << 12) // Idle condition interrupt
1554 #define EUARTUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
1555 #define EUARTUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
1556 #define EUARTUCR1_IREN (1 << 7) // Infrared interface enable
1557 #define EUARTUCR1_TXMPTYEN (1 << 6) // Transimitter empt interrupt enable
1558 #define EUARTUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
1559 #define EUARTUCR1_SNDBRK (1 << 4) // Send break
1560 #define EUARTUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
1561 #define EUARTUCR1_DOZE (1 << 1) // Doze
1562 #define EUARTUCR1_UARTEN (1 << 0) // UART enabled
1563 #define EUARTUCR2_ESCI (1 << 15) // Escape seq interrupt enable
1564 #define EUARTUCR2_IRTS (1 << 14) // Ignore RTS pin
1565 #define EUARTUCR2_CTSC (1 << 13) // CTS pin control
1566 #define EUARTUCR2_CTS (1 << 12) // Clear to send
1567 #define EUARTUCR2_ESCEN (1 << 11) // Escape enable
1568 #define EUARTUCR2_PREN (1 << 8) // Parity enable
1569 #define EUARTUCR2_PROE (1 << 7) // Parity odd/even
1570 #define EUARTUCR2_STPB (1 << 6) // Stop
1571 #define EUARTUCR2_WS (1 << 5) // Word size
1572 #define EUARTUCR2_RTSEN (1 << 4) // Request to send interrupt enable
1573 #define EUARTUCR2_ATEN (1 << 3) // Aging timer enable
1574 #define EUARTUCR2_TXEN (1 << 2) // Transmitter enabled
1575 #define EUARTUCR2_RXEN (1 << 1) // Receiver enabled
1576 #define EUARTUCR2_SRST_ (1 << 0) // SW reset
1577 #define EUARTUCR3_PARERREN (1 << 12) // Parity enable
1578 #define EUARTUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
1579 #define EUARTUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
1580 #define EUARTUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
1581 #define EUARTUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
1582 #define EUARTUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
1583 #define EUARTUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
1584 #define EUARTUCR3_INVT (1 << 1) // Inverted Infrared transmission
1585 #define EUARTUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
1586 #define EUARTUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
1587 #define EUARTUCR4_INVR (1 << 9) // Inverted infrared reception
1588 #define EUARTUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
1589 #define EUARTUCR4_WKEN (1 << 7) // Wake interrupt enable
1590 #define EUARTUCR4_IRSC (1 << 5) // IR special case
1591 #define EUARTUCR4_LPBYP (1 << 4) // Low power bypass
1592 #define EUARTUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
1593 #define EUARTUCR4_BKEN (1 << 2) // Break condition interrupt enable
1594 #define EUARTUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
1595 #define EUARTUCR4_DREN (1 << 0) // Recv data ready interrupt enable
1596 #define EUARTUFCR_RXTL_SHF 0 // Receiver trigger level shift
1597 #define EUARTUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div> 1)
1598 #define EUARTUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div> 2)
1599 #define EUARTUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
1600 #define EUARTUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
1601 #define EUARTUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
1602 #define EUARTUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
1603 #define EUARTUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
1604 #define EUARTUFCR_TXTL_SHF 10 // Transmitter trigger level shift
1605 #define EUARTUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
1606 #define EUARTUSR1_RTSS (1 << 14) // RTS pin status
1607 #define EUARTUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
1608 #define EUARTUSR1_RTSD (1 << 12) // RTS delta
1609 #define EUARTUSR1_ESCF (1 << 11) // Escape seq interrupt flag
1610 #define EUARTUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
1611 #define EUARTUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
1612 #define EUARTUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
1613 #define EUARTUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
1614 #define EUARTUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
1615 #define EUARTUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
1616 #define EUARTUSR2_ADET (1 << 15) // Auto baud rate detect complete
1617 #define EUARTUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
1618 #define EUARTUSR2_IDLE (1 << 12) // Idle condition
1619 #define EUARTUSR2_ACST (1 << 11) // Autobaud counter stopped
1620 #define EUARTUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
1621 #define EUARTUSR2_WAKE (1 << 7) // Wake
1622 #define EUARTUSR2_RTSF (1 << 4) // RTS edge interrupt flag
1623 #define EUARTUSR2_TXDC (1 << 3) // Transmitter complete
1624 #define EUARTUSR2_BRCD (1 << 2) // Break condition
1625 #define EUARTUSR2_ORE (1 << 1) // Overrun error
1626 #define EUARTUSR2_RDR (1 << 0) // Recv data ready
1627 #define EUARTUTS_FRCPERR (1 << 13) // Force parity error
1628 #define EUARTUTS_LOOP (1 << 12) // Loop tx and rx
1629 #define EUARTUTS_TXEMPTY (1 << 6) // TxFIFO empty
1630 #define EUARTUTS_RXEMPTY (1 << 5) // RxFIFO empty
1631 #define EUARTUTS_TXFULL (1 << 4) // TxFIFO full
1632 #define EUARTUTS_RXFULL (1 << 3) // RxFIFO full
1633 #define EUARTUTS_SOFTRST (1 << 0) // Software reset
1634
1635 /* SDMA */
1636 #define SDMA_MC0PTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x000))
1637 #define SDMA_INTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x004))
1638 #define SDMA_STOP_STAT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x008))
1639 #define SDMA_HSTART (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x00C))
1640 #define SDMA_EVTOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x010))
1641 #define SDMA_DSPOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x014))
1642 #define SDMA_HOSTOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x018))
1643 #define SDMA_EVTPEND (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x01C))
1644 #define SDMA_DSPENBL (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x020))
1645 #define SDMA_RESET (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x024))
1646 #define SDMA_EVTERR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x028))
1647 #define SDMA_INTRMSK (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x02C))
1648 #define SDMA_PSW (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x030))
1649 #define SDMA_EVTERRDBG (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x034))
1650 #define SDMA_CONFIG (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x038))
1651 #define SDMA_ONCE_ENB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x040))
1652 #define SDMA_ONCE_DATA (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x044))
1653 #define SDMA_ONCE_INSTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x048))
1654 #define SDMA_ONCE_STAT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x04C))
1655 #define SDMA_ONCE_CMD (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x050))
1656 #define SDMA_EVT_MIRROR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x054))
1657 #define SDMA_ILLINSTADDR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x058))
1658 #define SDMA_CHN0ADDR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x05C))
1659 #define SDMA_ONCE_RTB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x060))
1660 #define SDMA_XTRIG_CONF1 (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x070))
1661 #define SDMA_XTRIG_CONF2 (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x074))
1662
1663 /* SDMA_CHNENBL: 0x080 - 0x0FC */
1664 #define SDMA_CHNENBL(n) (((REG32_PTR_T)(SDMA_BASE_ADDR + 0x080))[n]) /* 0..31 */
1665
1666 /* SDMA_CHNPRI: 0x100 - 0x17C */
1667 #define SDMA_CHNPRI(n) (((REG32_PTR_T)(SDMA_BASE_ADDR + 0x100))[n]) /* 0..31 */
1668
1669 #define SDMA_ONCE_COUNT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x200))
1670 #define SDMA_ONCE_ECTL (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x204))
1671 #define SDMA_ONCE_EAA (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x208))
1672 #define SDMA_ONCE_EAB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x20C))
1673 #define SDMA_ONCE_EAM (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x210))
1674 #define SDMA_ONCE_ED (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x214))
1675 #define SDMA_ONCE_EDM (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x218))
1676 #define SDMA_ONCE_PCMATCH (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x21C))
1677
1678 /* SDMA_RESET */
1679 #define SDMA_RESET_RESCHED (0x1 << 1)
1680 #define SDMA_RESET_RESET (0x1 << 0)
1681
1682 /* SDMA_PSW */
1683 #define SDMA_PSW_NCP (0x7 << 13)
1684 #define SDMA_PSW_NCR (0x1f << 8)
1685 #define SDMA_PSW_CCP (0x7 << 5)
1686 #define SDMA_PSW_CCR (0x1f << 0)
1687
1688 /* SDMA_CONFIG */
1689 #define SDMA_CONFIG_DSPDMA (0x1 << 12)
1690 #define SDMA_CONFIG_RTDOBS (0x1 << 11)
1691 #define SDMA_CONFIG_ACR (0x1 << 4)
1692 #define SDMA_CONFIG_CSM (0x3 << 0)
1693 #define SDMA_CONFIG_CSM_STATIC (0x0 << 0)
1694 #define SDMA_CONFIG_CSM_DYNAMIC_LOW_POWER (0x1 << 0)
1695 #define SDMA_CONFIG_CSM_DYNAMIC_NO_LOOP (0x2 << 0)
1696 #define SDMA_CONFIG_CSM_DYNAMIC (0x3 << 0)
1697
1698 /* SDMA_ONCE_ENB */
1699 #define SDMA_ONCE_ENB_ENB (0x1 << 0)
1700
1701 /* SDMA_ONCE_STAT */
1702 #define SDMA_ONCE_STAT_PST (0xf << 12)
1703 #define SDMA_ONCE_STAT_PST_PROGRAM (0x0 << 12)
1704 #define SDMA_ONCE_STAT_PST_DATA (0x1 << 12)
1705 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW (0x2 << 12)
1706 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_LOOP (0x3 << 12)
1707 #define SDMA_ONCE_STAT_PST_DEBUG (0x4 << 12)
1708 #define SDMA_ONCE_STAT_PST_FUNCTIONAL_UNIT (0x5 << 12)
1709 #define SDMA_ONCE_STAT_PST_SLEEP (0x6 << 12)
1710 #define SDMA_ONCE_STAT_PST_SAVE (0x7 << 12)
1711 #define SDMA_ONCE_STAT_PST_PROGRAM_IN_SLEEP (0x8 << 12)
1712 #define SDMA_ONCE_STAT_PST_DATA_IN_SLEEP (0x9 << 12)
1713 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_SLEEP (0xa << 12)
1714 #define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_LOOP_IN_SLEEP (0xb << 12)
1715 #define SDMA_ONCE_STAT_PST_DEBUG_IN_SLEEP (0xc << 12)
1716 #define SDMA_ONCE_STAT_PST_FUNCTIONAL_UNIT_IN_SLEEP (0xd << 12)
1717 #define SDMA_ONCE_STAT_PST_SLEEP_AFTER_RESET (0xe << 12)
1718 #define SDMA_ONCE_STAT_PST_RESTORE (0xf << 12)
1719 #define SDMA_ONCE_STAT_RCV (0x1 << 11)
1720 #define SDMA_ONCE_STAT_EDR (0x1 << 10)
1721 #define SDMA_ONCE_STAT_ODR (0x1 << 9)
1722 #define SDMA_ONCE_STAT_SWB (0x1 << 8)
1723 #define SDMA_ONCE_STAT_MST (0x1 << 7)
1724 #define SDMA_ONCE_STAT_ECDR (0x7 << 0)
1725 #define SDMA_ONCE_STAT_ECDR_MATCHED_ADDRA_COND (0x1 << 0)
1726 #define SDMA_ONCE_STAT_ECDR_MATCHED_ADDRB_COND (0x1 << 1)
1727 #define SDMA_ONCE_STAT_ECDR_MATCHED_DATA_COND (0x1 << 2)
1728
1729 /* SDMA_ONCE_CMD */
1730 #define SDMA_ONCE_CMD_RSTATUS 0x0
1731 #define SDMA_ONCE_CMD_DMOV 0x1
1732 #define SDMA_ONCE_CMD_EXEC_ONCE 0x2
1733 #define SDMA_ONCE_CMD_RUN_CORE 0x3
1734 #define SDMA_ONCE_CMD_EXEC_CORE 0x4
1735 #define SDMA_ONCE_CMD_DEBUG_RQST 0x5
1736 #define SDMA_ONCE_CMD_RBUFFER 0x6
1737 /* 7-15 reserved */
1738
1739 /* SDMA_CHN0ADDR */
1740 #define SDMA_CHN0ADDR_SMSZ (0x1 << 14)
1741 /* 13:0 = 0x0050 by default (std. boot code) */
1742
1743 /* SDMA_EVT_MIRROR */
1744 #define SDMA_EVT_MIRROR_EVENTS(n) (0x1 << (n))
1745
1746 /* SDMA_XTRIG_CONF1 */
1747 #define SDMA_XTRIG_CONF1_CNF3 (0x1 << 30)
1748 #define SDMA_XTRIG_CONF1_NUM3 (0x1f << 24)
1749 #define SDMA_XTRIG_CONF1_CNF2 (0x1 << 22)
1750 #define SDMA_XTRIG_CONF1_NUM2 (0x1f << 16)
1751 #define SDMA_XTRIG_CONF1_CNF1 (0x1 << 14)
1752 #define SDMA_XTRIG_CONF1_NUM1 (0x1f << 8)
1753 #define SDMA_XTRIG_CONF1_CNF0 (0x1 << 6)
1754 #define SDMA_XTRIG_CONF1_NUM0 (0x1f << 0)
1755
1756 /* SDMA_XTRIG_CONF2 */
1757 #define SDMA_XTRIG_CONF2_CNF7 (0x1 << 30)
1758 #define SDMA_XTRIG_CONF2_NUM7 (0x1f << 24)
1759 #define SDMA_XTRIG_CONF2_CNF6 (0x1 << 22)
1760 #define SDMA_XTRIG_CONF2_NUM6 (0x1f << 16)
1761 #define SDMA_XTRIG_CONF2_CNF5 (0x1 << 14)
1762 #define SDMA_XTRIG_CONF2_NUM5 (0x1f << 8)
1763 #define SDMA_XTRIG_CONF2_CNF4 (0x1 << 6)
1764 #define SDMA_XTRIG_CONF2_NUM4 (0x1f << 0)
1765
1766 /* SDMA_CHNENBL(n) */
1767 #define SDMA_CHNENBL_ENBL(n) (0x1 << (n))
1768
1769
1770 #define L2CC_ENABLED
1771
1772 /* Assuming 26MHz input clock */
1773 /* PD MFD MFI MFN */
1774 #define MPCTL_PARAM_208 ((1 << 26) + (0 << 16) + (8 << 10) + (0 << 0))
1775 #define MPCTL_PARAM_399 ((0 << 26) + (51 << 16) + (7 << 10) + (35 << 0))
1776 #define MPCTL_PARAM_532 ((0 << 26) + (51 << 16) + (10 << 10) + (12 << 0))
1777
1778 /* UPCTL PD MFD MFI MFN */
1779 #define UPCTL_PARAM_288 (((1-1) << 26) + ((13-1) << 16) + (5 << 10) + (7 << 0))
1780 #define UPCTL_PARAM_240 (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
1781
1782 /* PDR0 */
1783 #define PDR0_208_104_52 0xFF870D48 /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */
1784 #define PDR0_399_66_66 0xFF872B28 /* ARM=399MHz, HCLK=IPG=66.5MHz */
1785 #define PDR0_399_133_66 0xFF871650 /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */
1786 #define PDR0_532_133_66 0xFF871E58 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
1787 #define PDR0_665_83_66 0xFF873D78 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
1788 #define PDR0_665_133_66 0xFF872660 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
1789
1790 #define PBC_BASE CS4_BASE_ADDR /* Peripheral Bus Controller */
1791
1792 #define PBC_BSTAT2 0x2
1793 #define PBC_BCTRL1 0x4
1794 #define PBC_BCTRL1_CLR 0x6
1795 #define PBC_BCTRL2 0x8
1796 #define PBC_BCTRL2_CLR 0xA
1797 #define PBC_BCTRL3 0xC
1798 #define PBC_BCTRL3_CLR 0xE
1799 #define PBC_BCTRL4 0x10
1800 #define PBC_BCTRL4_CLR 0x12
1801 #define PBC_BSTAT1 0x14
1802 #define MX31EVB_CS_LAN_BASE (CS4_BASE_ADDR + 0x00020000 + 0x300)
1803 #define MX31EVB_CS_UART_BASE (CS4_BASE_ADDR + 0x00010000)
1804
1805 #define REDBOOT_IMAGE_SIZE 0x40000
1806
1807 #define SDRAM_WORKAROUND_FULL_PAGE
1808
1809 #define ARMHIPG_208_52_52 /* ARM: 208MHz, HCLK=IPG=52MHz*/
1810 #define ARMHIPG_52_52_52 /* ARM: 52MHz, HCLK=IPG=52MHz*/
1811 #define ARMHIPG_399_66_66
1812 #define ARMHIPG_399_133_66
1813
1814 /* MX31 EVB SDRAM is from 0x80000000, 64M */
1815 #define SDRAM_BASE_ADDR CSD0_BASE_ADDR
1816 #define SDRAM_SIZE 0x04000000
1817
1818 #define UART_WIDTH_32 /* internal UART is 32bit access only */
1819 #define EXT_UART_x16
1820
1821 #define UART_WIDTH_32 /* internal UART is 32bit access only */
1822
1823 #define FLASH_BURST_MODE_ENABLE 1
1824 #define SDRAM_COMPARE_CONST1 0x55555555
1825 #define SDRAM_COMPARE_CONST2 0xAAAAAAAA
1826 #define UART_FIFO_CTRL 0x881
1827 #define TIMEOUT 1000
1828
1829 /* Timer frequency */
1830 /* timer is based on ipg_clk */
1831 #define TIMER_FREQ (66000000)
1832
1833 #endif /* __IMX31L_H__ */
thomasjfox's rockbox modifications (mameo port)