firmware/export/imx233.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2011 by Amaury Pouly
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef __IMX233_H__
  22 #define __IMX233_H__
  23
  24 /*
  25  * Chip Memory Map:
  26  *   0x00000000 - 0x00007fff: on chip ram
  27  *   0x40000000 - 0x5fffffff: dram (512Mb max)
  28  *   0x80000000 - 0x80100000: memory mapped registers
  29  * We use the following map:
  30  *   0x60000000 - 0x7fffffff: dram (cached)
  31  *   0x90000000 - 0xafffffff: dram (buffered)
  32  *   everything else        : identity mapped (uncached)
  33  *
  34  * As a side note it's important to notice that uncached dram is identity mapped
  35  */
  36
  37 #define IRAM_ORIG           0
  38 #define IRAM_SIZE           0x8000
  39 #define DRAM_ORIG           0x40000000
  40 #define DRAM_SIZE           (MEMORYSIZE * 0x100000)
  41
  42 #define UNCACHED_DRAM_ADDR  0x40000000
  43 #define CACHED_DRAM_ADDR    0x60000000
  44 #define BUFFERED_DRAM_ADDR  0x90000000
  45 #define CACHEALIGN_SIZE     32
  46
  47 #define NOCACHE_BASE        (UNCACHED_DRAM_ADDR - CACHED_DRAM_ADDR)
  48
  49 #define PHYSICAL_ADDR(a) \
  50     ((typeof(a))((uintptr_t)(a) >= BUFFERED_DRAM_ADDR ? \
  51         ((uintptr_t)(a) - BUFFERED_DRAM_ADDR + UNCACHED_DRAM_ADDR) \
  52         :(uintptr_t)(a) >= CACHED_DRAM_ADDR ? \
  53         ((uintptr_t)(a) - CACHED_DRAM_ADDR + UNCACHED_DRAM_ADDR) \
  54         :(uintptr_t)(a)))
  55 #define UNCACHED_ADDR(a) PHYSICAL_ADDR(a)
  56
  57 #define TTB_BASE_ADDR   (DRAM_ORIG + DRAM_SIZE - TTB_SIZE)
  58 #define TTB_SIZE        0x4000
  59 #define TTB_BASE        ((unsigned long *)TTB_BASE_ADDR)
  60 #define FRAME_SIZE      (LCD_WIDTH * LCD_HEIGHT * LCD_DEPTH / 8)
  61 #define FRAME_PHYS_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE - FRAME_SIZE)
  62 #define FRAME           ((void *)(FRAME_PHYS_ADDR - UNCACHED_DRAM_ADDR + BUFFERED_DRAM_ADDR))
  63
  64 /* Timer runs at 32KHz, derived from clk32k@32KHz */
  65 #define TIMER_FREQ      32000
  66
  67 /* USBOTG */
  68 #define USB_QHARRAY_ATTR    __attribute__((section(".qharray"),nocommon,aligned(2048)))
  69 #define USB_NUM_ENDPOINTS   5
  70 #define USB_DEVBSS_ATTR     NOCACHEBSS_ATTR
  71 #define USB_BASE            0x80080000
  72 /*
  73 #define QHARRAY_SIZE        ((64*USB_NUM_ENDPOINTS*2 + 2047) & (0xffffffff - 2047))
  74 #define QHARRAY_PHYS_ADDR   ((FRAME_PHYS_ADDR - QHARRAY_SIZE) & (0xffffffff - 2047))
  75 */
  76
  77 #define __REG_SET(reg)  (*((volatile uint32_t *)(&reg + 1)))
  78 #define __REG_CLR(reg)  (*((volatile uint32_t *)(&reg + 2)))
  79 #define __REG_TOG(reg)  (*((volatile uint32_t *)(&reg + 3)))
  80 #define __REG_SET_CLR(reg, set) \
  81     (*((volatile uint32_t *)(&reg + (set ? 1 : 2))))
  82
  83 #define __BLOCK_SFTRST  (1 << 31)
  84 #define __BLOCK_CLKGATE (1 << 30)
  85
  86 /* 32 bytes per cache line */
  87 #define CACHEALIGN_BITS     5
  88
  89 #define ___ENSURE_ZERO(line, x) static uint8_t __ensure_zero_##line[-(x)] __attribute__((unused));
  90 #define __ENSURE_ZERO(x) ___ENSURE_ZERO(__LINE__, x)
  91 #define __ENSURE_MULTIPLE(x, y) __ENSURE_ZERO((x) % (y))
  92 #define __ENSURE_CACHELINE_MULTIPLE(x) __ENSURE_MULTIPLE(x, 1 << CACHEALIGN_BITS)
  93 #define __ENSURE_STRUCT_CACHE_FRIENDLY(name) __ENSURE_CACHELINE_MULTIPLE(sizeof(name))
  94
  95 #define __XTRACT(reg, field)    ((reg & reg##__##field##_BM) >> reg##__##field##_BP)
  96 #define __XTRACT_EX(val, field)    (((val) & field##_BM) >> field##_BP)
  97 #define __FIELD_SET(reg, field, val) reg = (reg & ~reg##__##field##_BM) | (val << reg##__##field##_BP)
  98 #define __FIELD_SET_CLR(reg, field, set) __REG_SET_CLR(reg, set) = reg##__##field
  99
 100 #endif /* __IMX233_H__ */