Initial maemo platform support
[maemo-rb.git] / firmware / export / tlv320.h
blob66f4d5ca929aa9a505af9ecfffef4209f2c6f606
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
10 * Copyright (C) 2005 by Christian Gmeiner
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
22 #ifndef _TLV320_H_
23 #define _TLV320_H_
25 #define VOLUME_MIN -730
26 #define VOLUME_MAX 60
28 extern int tenthdb2master(int db);
30 /*** definitions ***/
31 extern void audiohw_set_headphone_vol(int vol_l, int vol_r);
33 #define HEADPHONE_MUTE 0x30 /* 0110000 = -73db */
35 /* ToDo: samplerates */
37 /* registers */
38 /* REG_LLIV: Left line input channel volume control */
39 #define REG_LLIV 0x0
40 #define LLIV_LRS (1 << 8) /* simultaneous volume/mute update */
41 #define LLIV_LIM (1 << 7) /* Left line input mute */
42 #define LLIV_LIV(x) ((x) & 0x1f)/* Left line input volume control */
44 /* REG_RLIV: Right line input channel volume control */
45 #define REG_RLIV 0x1
46 #define RLIV_RLS (1 << 8) /* simultaneous volume/mute update */
47 #define RLIV_RIM (1 << 7) /* Right line input mute */
48 #define RLIV_RIV(x) ((x) & 0x1f)/* Right line input volume control */
50 /* REG_LHV: Left Channel Headphone Volume Control */
51 #define REG_LHV 0x2
52 #define LHV_LRS (1 << 8) /* simultaneous volume/mute update */
53 #define LHV_LZC (1 << 7) /* Left-channel zero-cross detect */
54 #define LHV_LHV(x) ((x) & 0x7f)/* Left headphone volume control */
56 /* REG_RHV: Right Channel Headphone Volume Control */
57 #define REG_RHV 0x3
58 #define RHV_LRS (1 << 8) /* simultaneous volume/mute update */
59 #define RHV_RZC (1 << 7) /* Right-channel zero-cross detect */
60 #define RHV_RHV(x) ((x) & 0x7f)/* Right headphone volume control */
62 /* REG_AAP: Analog Audio Path Control */
63 #define REG_AAP 0x4
64 #define AAP_DAC (1 << 4) /* DAC select */
65 #define AAP_BYPASS (1 << 3) /* bypass */
66 #define AAP_INSEL (1 << 2) /* Input select for ADC */
67 #define AAP_MICM (1 << 1) /* Microphone mute */
68 #define AAP_MICB (1 << 0) /* Microphone boost */
70 /* REG_DAP: Digital Audio Path Control */
71 #define REG_DAP 0x5
72 #define DAP_DACM (1 << 3) /* DAC soft mute */
73 #define DAP_DEEMP_32 (1 << 1) /* De-emphasis control: 32 kHz */
74 #define DAP_DEEMP_44 (2 << 1) /* De-emphasis control: 44.1 kHz */
75 #define DAP_DEEMP_48 (3 << 1) /* De-emphasis control: 48 kHz */
76 #define DAP_ADCHP (1 << 0) /* ADC high-pass filter */
78 /* REG_PC: Power Down Control */
79 #define REG_PC 0x6
80 #define PC_OFF (1 << 7) /* Device power */
81 #define PC_CLK (1 << 6) /* Clock */
82 #define PC_OSC (1 << 5) /* Oscillator */
83 #define PC_OUT (1 << 4) /* Outputs */
84 #define PC_DAC (1 << 3) /* DAC */
85 #define PC_ADC (1 << 2) /* ADC */
86 #define PC_MIC (1 << 1) /* Microphone input */
87 #define PC_LINE (1 << 0) /* Line input */
89 /* REG_DAIF: Digital Audio Interface Format */
90 #define REG_DAIF 0x7
91 #define DAIF_MS (1 << 6) /* Master/slave mode */
92 #define DAIF_LRSWAP (1 << 5) /* DAC left/right swap */
93 #define DAIF_LRP (1 << 4) /* DAC left/right phase */
94 #define DAIF_IWL_16 (0 << 2) /* Input bit length: 16 bit */
95 #define DAIF_IWL_20 (1 << 2) /* Input bit length: 20 bit */
96 #define DAIF_IWL_24 (2 << 2) /* Input bit length: 24 bit */
97 #define DAIF_IWL_32 (3 << 2) /* Input bit length: 32 bit */
98 #define DAIF_FOR_DSP (3 << 0) /* Data format: DSP */
99 #define DAIF_FOR_I2S (2 << 0) /* Data format: I2S */
100 #define DAIF_FOR_MSBL (1 << 0) /* Data format: MSB first, left aligned */
101 #define DAIF_FOR_MSBR (0 << 0) /* Data format: MSB first, right aligned */
103 /* REG_SRC: Sample Rate Control */
104 #define REG_SRC 0x8
105 #define SRC_CLKIN (1 << 6) /* Clock input divider */
106 #define SRC_CLKOUT (1 << 7) /* Clock output divider */
107 /*#define SRC_SR ()*/
108 #define SRC_BOSR (1 << 1) /* Base oversampling rate, depends on SRC_USB */
109 #define SRC_USB (1 << 0) /* Clock mode select */
111 /* REG_DIA: Digital Interface Activation */
112 #define REG_DIA 0x9
113 #define DIA_ACT (1 << 0) /* Activate interface */
115 /* REG_RR: Reset Register */
116 #define REG_RR 0xf
117 #define RR_RESET 0 /* Reset */
119 #endif /*_TLV320_H_*/