firmware/export/isp1583.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2008 by Maurus Cuelenaere
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef ISP1583_H
  22 #define ISP1583_H
  23
  24 #include "dm320.h"
  25
  26 /* General purpose memory region #2 */
  27 #define ISP1583_IOBASE              0x60FFC000
  28
  29 #define ISP1583_INIT_ADDRESS        (*((volatile unsigned char*)(ISP1583_IOBASE+0x0))) //char
  30 #define ISP1583_INIT_MODE           (*((volatile unsigned short*)(ISP1583_IOBASE+0xC*2)))
  31 #define ISP1583_INIT_INTCONF        (*((volatile unsigned char*)(ISP1583_IOBASE+0x10*2))) //char
  32 #define ISP1583_INIT_OTG            (*((volatile unsigned char*)(ISP1583_IOBASE+0x12*2))) //char
  33 #define ISP1583_INIT_INTEN_A        (*((volatile unsigned short*)(ISP1583_IOBASE+0x14*2)))
  34 #define ISP1583_INIT_INTEN_B        (*((volatile unsigned short*)(ISP1583_IOBASE+0x14*2+4)))
  35 #define ISP1583_INIT_INTEN_READ     (unsigned long)( (ISP1583_INIT_INTEN_A & 0xFFFF) | ((ISP1583_INIT_INTEN_B & 0xFFFF) << 16) )
  36 /* Data flow registers */
  37 #define ISP1583_DFLOW_EPINDEX       (*((volatile unsigned char*)(ISP1583_IOBASE+0xC2*2))) //char
  38 #define ISP1583_DFLOW_CTRLFUN       (*((volatile unsigned char*)(ISP1583_IOBASE+0x28*2))) //char
  39 #define ISP1583_DFLOW_DATA          (*((volatile unsigned short*)(ISP1583_IOBASE+0x20*2)))
  40 #define ISP1583_DFLOW_BUFLEN        (*((volatile unsigned short*)(ISP1583_IOBASE+0x1C*2)))
  41 #define ISP1583_DFLOW_BUFSTAT       (*((volatile unsigned char*)(ISP1583_IOBASE+0x1E*2))) //char
  42 #define ISP1583_DFLOW_MAXPKSZ       (*((volatile unsigned short*)(ISP1583_IOBASE+0x04*2)))
  43 #define ISP1583_DFLOW_EPTYPE        (*((volatile unsigned short*)(ISP1583_IOBASE+0x08*2)))
  44 /* DMA registers */
  45 #define ISP1583_DMA_ENDPOINT        (*((volatile unsigned char*)(ISP1583_IOBASE+0x58*2)))
  46 /* General registers */
  47 #define ISP1583_GEN_INT_A           (*((volatile unsigned short*)(ISP1583_IOBASE+0x18*2)))
  48 #define ISP1583_GEN_INT_B           (*((volatile unsigned short*)(ISP1583_IOBASE+0x18*2+4)))
  49 #define ISP1583_GEN_INT_READ        (unsigned long)( (ISP1583_GEN_INT_A & 0xFFFF) | ((ISP1583_GEN_INT_B & 0xFFFF) << 16))
  50 #define ISP1583_GEN_CHIPID_A        (*((volatile unsigned short*)(ISP1583_IOBASE+0x70*2)))
  51 #define ISP1583_GEN_CHIPID_B        (*((volatile unsigned char*)(ISP1583_IOBASE+0x70*2+4))) //char
  52 #define ISP1583_GEN_CHIPID          (unsigned long)( (ISP1583_GEN_CHIPID_A & 0xFFFF) | ((ISP1583_GEN_CHIPID_B & 0xFFFF) << 16) )
  53 #define ISP1583_GEN_FRAMEN0         (*((volatile unsigned short*)(ISP1583_IOBASE+0x74*2)))
  54 #define ISP1583_GEN_SCRATCH         (*((volatile unsigned short*)(ISP1583_IOBASE+0x78*2)))
  55 #define ISP1583_GEN_UNLCKDEV        (*((volatile unsigned short*)(ISP1583_IOBASE+0x7C*2)))
  56 #define ISP1583_GEN_TSTMOD          (*((volatile unsigned char*)(ISP1583_IOBASE+0x84*2))) //char
  57
  58 #define EN_INT_CPU_TARGET           IO_INTC_EINT1 |= INTR_EINT1_EXT7
  59 #define DIS_INT_CPU_TARGET          IO_INTC_EINT1 &= ~INTR_EINT1_EXT7
  60 #define INT_CONF_TARGET             0
  61 //#define INT_CONF_TARGET             2
  62 #define set_int_value(a,b,value)    a = value & 0xFFFF; \
  63                                     b = value >> 16;
  64 #define ISP1583_UNLOCK_CODE         ((unsigned short)0xAA37)
  65
  66 /* Initialization registers' bits */
  67
  68 /* Initialization OTG register bits */
  69 #define INIT_OTG_BSESS_VALID        (1 << 4)
  70
  71 /* Initialization Mode register bits */
  72 #define INIT_MODE_TEST2             (1 << 15)
  73 #define INIT_MODE_TEST1             (1 << 14)
  74 #define INIT_MODE_TEST0             (1 << 13)
  75 #define INIT_MODE_DMA_CLKON         (1 << 9)
  76 #define INIT_MODE_VBUSSTAT          (1 << 8)
  77 #define INIT_MODE_CLKAON            (1 << 7)
  78 #define INIT_MODE_SNDRSU            (1 << 6)
  79 #define INIT_MODE_GOSUSP            (1 << 5)
  80 #define INIT_MODE_SFRESET           (1 << 4)
  81 #define INIT_MODE_GLINTENA          (1 << 3)
  82 #define INIT_MODE_WKUPCS            (1 << 2)
  83 #define INIT_MODE_PWRON             (1 << 1)
  84 #define INIT_MODE_SOFTCT            (1 << 0)
  85
  86 /* Initialization Interrupt Enable register bits */
  87 #define INIT_INTEN_IEP7TX           (1 << 25)
  88 #define INIT_INTEN_IEP7RX           (1 << 24)
  89 #define INIT_INTEN_IEP6TX           (1 << 23)
  90 #define INIT_INTEN_IEP6RX           (1 << 22)
  91 #define INIT_INTEN_IEP5TX           (1 << 21)
  92 #define INIT_INTEN_IEP5RX           (1 << 20)
  93 #define INIT_INTEN_IEP4TX           (1 << 19)
  94 #define INIT_INTEN_IEP4RX           (1 << 18)
  95 #define INIT_INTEN_IEP3TX           (1 << 17)
  96 #define INIT_INTEN_IEP3RX           (1 << 16)
  97 #define INIT_INTEN_IEP2TX           (1 << 15)
  98 #define INIT_INTEN_IEP2RX           (1 << 14)
  99 #define INIT_INTEN_IEP1TX           (1 << 13)
 100 #define INIT_INTEN_IEP1RX           (1 << 12)
 101 #define INIT_INTEN_IEP0TX           (1 << 11)
 102 #define INIT_INTEN_IEP0RX           (1 << 10)
 103 #define INIT_INTEN_IEP0SETUP        (1 << 8)
 104 #define INIT_INTEN_IEVBUS           (1 << 7)
 105 #define INIT_INTEN_IEDMA            (1 << 6)
 106 #define INIT_INTEN_IEHS_STA         (1 << 5)
 107 #define INIT_INTEN_IERESM           (1 << 4)
 108 #define INIT_INTEN_IESUSP           (1 << 3)
 109 #define INIT_INTEN_IEPSOF           (1 << 2)
 110 #define INIT_INTEN_IESOF            (1 << 1)
 111 #define INIT_INTEN_IEBRST           (1 << 0)
 112
 113 /* Initialization Interrupt Configuration register bits */
 114 #define INIT_INTCONF_INTLVL         (1 << 1)
 115 #define INIT_INTCONF_INTPOL         (1 << 0)
 116
 117 /* Initialization Address register bits */
 118 #define INIT_ADDRESS_DEVEN          (1 << 7)
 119
 120 /* Data Flow registers' bits */
 121
 122 /* Data Flow Endpoint Index register bits */
 123 #define DFLOW_EPINDEX_EP0SETUP      (1 << 5)
 124
 125 /* Data Flow Control Function register bits */
 126 #define DFLOW_CTRLFUN_CLBUF         (1 << 4)
 127 #define DFLOW_CTRLFUN_VENDP         (1 << 3)
 128 #define DFLOW_CTRLFUN_DSEN          (1 << 2)
 129 #define DFLOW_CTRLFUN_STATUS        (1 << 1)
 130 #define DFLOW_CTRLFUN_STALL         (1 << 0)
 131
 132 /* Data Flow Endpoint Type register bits */
 133 #define DFLOW_EPTYPE_NOEMPKT        (1 << 4)
 134 #define DFLOW_EPTYPE_ENABLE         (1 << 3)
 135 #define DFLOW_EPTYPE_DBLBUF         (1 << 2)
 136
 137 /* General registers' bits */
 138
 139 /* General Test Mode register bits */
 140 #define GEN_TSTMOD_FORCEHS          (1 << 7)
 141 #define GEN_TSTMOD_FORCEFS          (1 << 4)
 142 #define GEN_TSTMOD_PRBS             (1 << 3)
 143 #define GEN_TSTMOD_KSTATE           (1 << 2)
 144 #define GEN_TSTMOD_JSTATE           (1 << 1)
 145 #define GEN_TSTMOD_SE0_NAK          (1 << 0)
 146
 147 /* Interrupts */
 148 #define INT_IEP7TX                  (1 << 25)
 149 #define INT_IEP7RX                  (1 << 24)
 150 #define INT_IEP6TX                  (1 << 23)
 151 #define INT_IEP6RX                  (1 << 22)
 152 #define INT_IEP5TX                  (1 << 21)
 153 #define INT_IEP5RX                  (1 << 20)
 154 #define INT_IEP4TX                  (1 << 19)
 155 #define INT_IEP4RX                  (1 << 18)
 156 #define INT_IEP3TX                  (1 << 17)
 157 #define INT_IEP3RX                  (1 << 16)
 158 #define INT_IEP2TX                  (1 << 15)
 159 #define INT_IEP2RX                  (1 << 14)
 160 #define INT_IEP1TX                  (1 << 13)
 161 #define INT_IEP1RX                  (1 << 12)
 162 #define INT_IEP0TX                  (1 << 11)
 163 #define INT_IEP0RX                  (1 << 10)
 164 #define INT_IEP0SETUP               (1 << 8)
 165 #define INT_IEVBUS                  (1 << 7)
 166 #define INT_IEDMA                   (1 << 6)
 167 #define INT_IEHS_STA                (1 << 5)
 168 #define INT_IERESM                  (1 << 4)
 169 #define INT_IESUSP                  (1 << 3)
 170 #define INT_IEPSOF                  (1 << 2)
 171 #define INT_IESOF                   (1 << 1)
 172 #define INT_IEBRST                  (1 << 0)
 173
 174 #define INT_EP_MASK                 ( INT_IEP0RX | INT_IEP0TX | INT_IEP1RX | INT_IEP1TX | INT_IEP2RX | INT_IEP2TX | INT_IEP3RX | INT_IEP3TX | INT_IEP4RX | INT_IEP4TX | INT_IEP5RX | INT_IEP5TX | INT_IEP6RX | INT_IEP6TX | INT_IEP7RX | INT_IEP7TX )
 175
 176 #define STANDARD_INTEN              ( INIT_INTEN_IEBRST | INIT_INTEN_IEHS_STA | INT_IESUSP | INT_IERESM | INIT_INTEN_IEVBUS | INIT_INTEN_IEP0SETUP | INIT_INTEN_IEP0RX | INIT_INTEN_IEP0TX )
 177 #define STANDARD_INIT_MODE          ( INIT_MODE_CLKAON | INIT_MODE_GLINTENA )
 178
 179 #define IRAM_ATTR __attribute__ ((section(".icode")))
 180
 181 #include "usb_drv.h"
 182
 183 #endif