firmware/target/arm/imx233/rtc-imx233.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2011 by Amaury Pouly
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef RTC_IMX233_H
  22 #define RTC_IMX233_H
  23
  24 #include "config.h"
  25 #include "system.h"
  26 #include "cpu.h"
  27
  28 #define HW_RTC_BASE     0x8005c000
  29
  30 #define HW_RTC_CTRL         (*(volatile uint32_t *)(HW_RTC_BASE + 0x0))
  31 #define HW_RTC_CTRL__ALARM_IRQ_EN   (1 << 0)
  32 #define HW_RTC_CTRL__ONEMSEC_IRQ_EN (1 << 1)
  33 #define HW_RTC_CTRL__ALARM_IRQ      (1 << 2)
  34 #define HW_RTC_CTRL__ONEMSEC_IRQ    (1 << 3)
  35 #define HW_RTC_CTRL__WATCHDOGEN     (1 << 4)
  36 #define HW_RTC_CTRL__FORCE_UPDATE   (1 << 5)
  37 #define HW_RTC_CTRL__SUPPRESS_COPY2ANALOG   (1 << 6)
  38
  39 #define HW_RTC_STAT         (*(volatile uint32_t *)(HW_RTC_BASE + 0x10))
  40 #define HW_RTC_STAT__NEW_REGS_BP    8
  41 #define HW_RTC_STAT__NEW_REGS_BM    0xff00
  42 #define HW_RTC_STAT__STALE_REGS_BP  16
  43 #define HW_RTC_STAT__STALE_REGS_BM  0xff0000
  44 #define HW_RTC_STAT__XTAL32768_PRESENT  (1 << 27)
  45 #define HW_RTC_STAT__XTAL32000_PRESENT  (1 << 28)
  46 #define HW_RTC_STAT__WATCHDOG_PRESENT   (1 << 29)
  47 #define HW_RTC_STAT__ALARM_PRESENT      (1 << 30)
  48 #define HW_RTC_STAT__RTC_PRESENT        (1 << 31)
  49
  50 #define HW_RTC_MILLISECONDS (*(volatile uint32_t *)(HW_RTC_BASE + 0x20))
  51
  52 #define HW_RTC_SECONDS      (*(volatile uint32_t *)(HW_RTC_BASE + 0x30))
  53
  54 #define HW_RTC_ALARM        (*(volatile uint32_t *)(HW_RTC_BASE + 0x40))
  55
  56 #define HW_RTC_WATCHDOG     (*(volatile uint32_t *)(HW_RTC_BASE + 0x50))
  57
  58 #define HW_RTC_PERSISTENTx(x)   (*(volatile uint32_t *)(HW_RTC_BASE + 0x60 + (x) * 0x10))
  59
  60 #define HW_RTC_PERSISTENT0  (*(volatile uint32_t *)(HW_RTC_BASE + 0x60))
  61 #define HW_RTC_PERSISTENT0__CLOCKSOURCE (1 << 0)
  62 #define HW_RTC_PERSISTENT0__ALARM_WAKE_EN   (1 << 1)
  63 #define HW_RTC_PERSISTENT0__ALARM_EN    (1 << 2)
  64 #define HW_RTC_PERSISTENT0__XTAL24MHZ_PWRUP (1 << 4)
  65 #define HW_RTC_PERSISTENT0__XTAL32KHZ_PWRUP (1 << 5)
  66 #define HW_RTC_PERSISTENT0__XTAL32_FREQ (1 << 6)
  67 #define HW_RTC_PERSISTENT0__ALARM_WAKE  (1 << 7)
  68 #define HW_RTC_PERSISTENT0__AUTO_RESTART    (1 << 17)
  69 #define HW_RTC_PERSISTENT0__SPARE_BP    18
  70 #define HW_RTC_PERSISTENT0__SPARE_BM    (0x3fff << 18)
  71 #define HW_RTC_PERSISTENT0__SPARE__RELEASE_GND  (1 << 19)
  72
  73 #define HW_RTC_PERSISTENT1  (*(volatile uint32_t *)(HW_RTC_BASE + 0x70))
  74
  75 #define HW_RTC_PERSISTENT2  (*(volatile uint32_t *)(HW_RTC_BASE + 0x80))
  76
  77 #define HW_RTC_PERSISTENT3  (*(volatile uint32_t *)(HW_RTC_BASE + 0x90))
  78
  79 #define HW_RTC_PERSISTENT4  (*(volatile uint32_t *)(HW_RTC_BASE + 0xa0))
  80
  81 #define HW_RTC_PERSISTENT5  (*(volatile uint32_t *)(HW_RTC_BASE + 0xb0))
  82
  83 struct imx233_rtc_info_t
  84 {
  85     uint32_t seconds;
  86     uint32_t persistent[6];
  87 };
  88
  89 static inline void imx233_rtc_init(void)
  90 {
  91     __REG_CLR(HW_RTC_CTRL) = __BLOCK_CLKGATE;
  92 }
  93
  94 static inline uint32_t imx233_rtc_read_seconds(void)
  95 {
  96     return HW_RTC_SECONDS;
  97 }
  98
  99 static inline uint32_t imx233_rtc_read_persistent(int idx)
 100 {
 101     return HW_RTC_PERSISTENTx(idx);
 102 }
 103
 104 static inline void imx233_rtc_clear_msec_irq(void)
 105 {
 106     __REG_CLR(HW_RTC_CTRL) = HW_RTC_CTRL__ONEMSEC_IRQ;
 107 }
 108
 109 static inline void imx233_rtc_enable_msec_irq(bool enable)
 110 {
 111     imx233_rtc_clear_msec_irq();
 112     if(enable)
 113         __REG_SET(HW_RTC_CTRL) = HW_RTC_CTRL__ONEMSEC_IRQ_EN;
 114     else
 115         __REG_CLR(HW_RTC_CTRL) = HW_RTC_CTRL__ONEMSEC_IRQ_EN;
 116 }
 117
 118 void imx233_rtc_write_seconds(uint32_t seconds);
 119 void imx233_rtc_write_persistent(int idx, uint32_t val);
 120
 121 struct imx233_rtc_info_t imx233_rtc_get_info(void);
 122
 123 #endif /* RTC_IMX233_H */