firmware/rolo.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 Randy D. Wood
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "config.h"
  23 #include "lcd.h"
  24 #include "lcd-remote.h"
  25 #include "thread.h"
  26 #include "kernel.h"
  27 #include "button.h"
  28 #include "file.h"
  29 #include "audio.h"
  30 #include "system.h"
  31 #include "i2c.h"
  32 #include "adc.h"
  33 #include "string.h"
  34 #include "core_alloc.h"
  35 #include "storage.h"
  36 #include "rolo.h"
  37
  38 #ifdef MI4_FORMAT
  39 #include "crc32-mi4.h"
  40 #undef FIRMWARE_OFFSET_FILE_CRC
  41 #undef FIRMWARE_OFFSET_FILE_DATA
  42 #define FIRMWARE_OFFSET_FILE_CRC     0xC
  43 #define FIRMWARE_OFFSET_FILE_DATA    0x200
  44 #endif
  45
  46 #if !defined(IRIVER_IFP7XX_SERIES)
  47 /* FIX: this doesn't work on iFP */
  48
  49 #define IRQ0_EDGE_TRIGGER 0x80
  50
  51 static int rolo_handle;
  52 #ifdef CPU_PP
  53 /* Handle the COP properly - it needs to jump to a function outside SDRAM while
  54  * the new firmware is being loaded, and then jump to the start of SDRAM
  55  * TODO: Use the mailboxes built into the PP processor for this
  56  */
  57
  58 #if NUM_CORES > 1
  59 volatile unsigned char IDATA_ATTR cpu_message = 0;
  60 volatile unsigned char IDATA_ATTR cpu_reply = 0;
  61 extern int cop_idlestackbegin[];
  62
  63 void rolo_restart_cop(void) ICODE_ATTR;
  64 void rolo_restart_cop(void)
  65 {
  66     if (CURRENT_CORE == CPU)
  67     {
  68         /* There should be free thread slots aplenty */
  69         create_thread(rolo_restart_cop, cop_idlestackbegin, IDLE_STACK_SIZE,
  70                       0, "rolo COP" IF_PRIO(, PRIORITY_REALTIME)
  71                       IF_COP(, COP));
  72         return;
  73     }
  74
  75     COP_INT_DIS = -1;
  76
  77     /* Invalidate cache */
  78     cpucache_invalidate();
  79
  80     /* Disable cache */
  81     CACHE_CTL = CACHE_CTL_DISABLE;
  82
  83     /* Tell the main core that we're ready to reload */
  84     cpu_reply = 1;
  85
  86     /* Wait while RoLo loads the image into SDRAM */
  87     /* TODO: Accept checksum failure gracefully */
  88     while(cpu_message != 1);
  89
  90     /* Acknowledge the CPU and then reload */
  91     cpu_reply = 2;
  92
  93     asm volatile(
  94         "bx    %0   \n"
  95         : : "r"(DRAM_START)
  96     );
  97 }
  98 #endif /* NUM_CORES > 1 */
  99 #endif /* CPU_PP */
 100
 101 static void rolo_error(const char *text)
 102 {
 103     rolo_handle = core_free(rolo_handle);
 104     lcd_clear_display();
 105     lcd_puts(0, 0, "ROLO error:");
 106     lcd_puts_scroll(0, 1, text);
 107     lcd_update();
 108     button_get(true);
 109     button_get(true);
 110     button_get(true);
 111     lcd_stop_scroll();
 112 }
 113
 114 #if CONFIG_CPU == SH7034 || CONFIG_CPU == IMX31L
 115 /* these are in assembler file "descramble.S" for SH7034 */
 116 extern unsigned short descramble(const unsigned char* source,
 117                                  unsigned char* dest, int length);
 118 /* this is in firmware/target/arm/imx31/rolo_restart.c for IMX31 */
 119 extern void rolo_restart(const unsigned char* source, unsigned char* dest,
 120                          int length);
 121 #else
 122
 123 /* explicitly put this code in iram, ICODE_ATTR is defined to be null for some
 124    targets that are low on iram, like the gigabeat F/X */
 125 void rolo_restart(const unsigned char* source, unsigned char* dest,
 126                   long length) __attribute__ ((section(".icode")));
 127 void rolo_restart(const unsigned char* source, unsigned char* dest,
 128                   long length)
 129 {
 130     long i;
 131     unsigned char* localdest = dest;
 132
 133     /* This is the equivalent of a call to memcpy() but this must be done from
 134        iram to avoid overwriting itself and we don't want to depend on memcpy()
 135        always being in iram */
 136     for(i = 0;i < length;i++)
 137         *localdest++ = *source++;
 138
 139 #if defined(CPU_COLDFIRE)
 140     asm (
 141         "movec.l %0,%%vbr    \n"
 142         "move.l  (%0)+,%%sp  \n"
 143         "move.l  (%0),%0     \n"
 144         "jmp     (%0)        \n"
 145         : : "a"(dest)
 146     );
 147 #elif defined(CPU_PP)
 148     CPU_INT_DIS = -1;
 149
 150     /* Flush cache */
 151     cpucache_flush();
 152
 153     /* Disable cache */
 154     CACHE_CTL = CACHE_CTL_DISABLE;
 155
 156     /* Reset the memory mapping registers to zero */
 157     {
 158         volatile unsigned long *mmap_reg;
 159         for (mmap_reg = &MMAP_FIRST; mmap_reg <= &MMAP_LAST; mmap_reg++)
 160             *mmap_reg = 0;
 161     }
 162
 163 #if NUM_CORES > 1
 164     /* Tell the COP it's safe to continue rebooting */
 165     cpu_message = 1;
 166
 167     /* Wait for the COP to tell us it is rebooting */
 168     while(cpu_reply != 2);
 169 #endif
 170
 171     asm volatile(
 172         "bx    %0   \n"
 173         : : "r"(DRAM_START)
 174     );
 175
 176 #elif defined(CPU_ARM)
 177 #ifdef HAVE_CPUCACHE_INVALIDATE
 178     /* Flush and invalidate caches */
 179     cpucache_invalidate();
 180 #endif
 181     asm volatile(
 182         "bx    %0   \n"
 183         : : "r"(dest)
 184     );
 185 #elif defined(CPU_MIPS)
 186     __dcache_writeback_all();
 187     asm volatile(
 188         "jr     %0               \n"
 189         : : "r"(dest)
 190     );
 191 #endif
 192 }
 193 #endif
 194
 195 /* This is assigned in the linker control file */
 196 extern unsigned long loadaddress;
 197
 198 /***************************************************************************
 199  *
 200  * Name: rolo_load_app(char *filename,int scrambled)
 201  * Filename must be a fully defined filename including the path and extension
 202  *
 203  ***************************************************************************/
 204 int rolo_load(const char* filename)
 205 {
 206     int fd;
 207     long length;
 208 #if defined(CPU_COLDFIRE) || defined(CPU_ARM) || defined(CPU_MIPS)
 209 #if !defined(MI4_FORMAT)
 210     int i;
 211 #endif
 212     unsigned long checksum,file_checksum;
 213 #else
 214     long file_length;
 215     unsigned short checksum,file_checksum;
 216 #endif
 217     unsigned char* ramstart = (void*)&loadaddress;
 218     unsigned char* filebuf;
 219     size_t filebuf_size;
 220
 221     lcd_clear_display();
 222     lcd_puts(0, 0, "ROLO...");
 223     lcd_puts(0, 1, "Loading");
 224     lcd_update();
 225 #ifdef HAVE_REMOTE_LCD
 226     lcd_remote_clear_display();
 227     lcd_remote_puts(0, 0, "ROLO...");
 228     lcd_remote_puts(0, 1, "Loading");
 229     lcd_remote_update();
 230 #endif
 231
 232     audio_stop();
 233
 234     fd = open(filename, O_RDONLY);
 235     if(-1 == fd) {
 236         rolo_error("File not found");
 237         return -1;
 238     }
 239
 240     length = filesize(fd) - FIRMWARE_OFFSET_FILE_DATA;
 241
 242     /* get the system buffer. release only in case of error, otherwise
 243      * we don't return anyway */
 244     rolo_handle = core_alloc_maximum("rolo", &filebuf_size, NULL);
 245     filebuf = core_get_data(rolo_handle);
 246
 247 #if CONFIG_CPU != SH7034
 248     /* Read and save checksum */
 249     lseek(fd, FIRMWARE_OFFSET_FILE_CRC, SEEK_SET);
 250     if (read(fd, &file_checksum, 4) != 4) {
 251         rolo_error("Error Reading checksum");
 252         return -1;
 253     }
 254
 255 #if !defined(MI4_FORMAT)
 256     /* Rockbox checksums are big-endian */
 257     file_checksum = betoh32(file_checksum);
 258 #endif
 259
 260 #if defined(CPU_PP) && NUM_CORES > 1
 261     lcd_puts(0, 2, "Waiting for coprocessor...");
 262     lcd_update();
 263     rolo_restart_cop();
 264     /* Wait for COP to be in safe code */
 265     while(cpu_reply != 1);
 266     lcd_puts(0, 2, "                          ");
 267     lcd_update();
 268 #endif
 269
 270     lseek(fd, FIRMWARE_OFFSET_FILE_DATA, SEEK_SET);
 271
 272     /* this shouldn't happen, but well */
 273     if ((long)filebuf_size < length)
 274     {
 275         rolo_error("File too big");
 276         return -1;
 277     }
 278
 279     if (read(fd, filebuf, length) != length) {
 280         rolo_error("Error Reading File");
 281         return -1;
 282     }
 283
 284 #ifdef MI4_FORMAT
 285     /* Check CRC32 to see if we have a valid file */
 286     chksum_crc32gentab();
 287     checksum = chksum_crc32 (filebuf, length);
 288 #else
 289     checksum = MODEL_NUMBER;
 290
 291     for(i = 0;i < length;i++) {
 292         checksum += filebuf[i];
 293     }
 294 #endif
 295
 296     /* Verify checksum against file header */
 297     if (checksum != file_checksum) {
 298         rolo_error("Checksum Error");
 299         return -1;
 300     }
 301
 302 #ifdef HAVE_STORAGE_FLUSH
 303     lcd_puts(0, 1, "Flushing storage buffers");
 304     lcd_update();
 305     storage_flush();
 306 #endif
 307
 308     lcd_puts(0, 1, "Executing");
 309     lcd_update();
 310 #ifdef HAVE_REMOTE_LCD
 311     lcd_remote_puts(0, 1, "Executing");
 312     lcd_remote_update();
 313 #endif
 314     adc_close();
 315
 316 #if CONFIG_CPU != IMX31L /* We're not finished yet */
 317 #ifdef CPU_ARM
 318     /* Should do these together since some ARM version should never have
 319      * FIQ disabled and not IRQ (imx31 errata). */
 320     disable_interrupt(IRQ_FIQ_STATUS);
 321 #else
 322     /* Some targets have a higher disable level than HIGEST_IRQ_LEVEL */
 323     set_irq_level(DISABLE_INTERRUPTS);
 324 #endif
 325 #endif /* CONFIG_CPU == IMX31L */
 326
 327 #else /* CONFIG_CPU == SH7034 */
 328     /* Read file length from header and compare to real file length */
 329     lseek(fd, FIRMWARE_OFFSET_FILE_LENGTH, SEEK_SET);
 330     if(read(fd, &file_length, 4) != 4) {
 331         rolo_error("Error Reading File Length");
 332         return -1;
 333     }
 334     if (length != file_length) {
 335         rolo_error("File length mismatch");
 336         return -1;
 337     }
 338
 339     /* Read and save checksum */
 340     lseek(fd, FIRMWARE_OFFSET_FILE_CRC, SEEK_SET);
 341     if (read(fd, &file_checksum, 2) != 2) {
 342         rolo_error("Error Reading checksum");
 343         return -1;
 344     }
 345     lseek(fd, FIRMWARE_OFFSET_FILE_DATA, SEEK_SET);
 346
 347     /* verify that file can be read and descrambled */
 348     if ((size_t)((2*length)+4) >= filebuf_size) {
 349         rolo_error("Not enough room to load file");
 350         return -1;
 351     }
 352
 353     if (read(fd, &filebuf[length], length) != (int)length) {
 354         rolo_error("Error Reading File");
 355         return -1;
 356     }
 357
 358     lcd_puts(0, 1, "Descramble");
 359     lcd_update();
 360
 361     checksum = descramble(filebuf + length, filebuf, length);
 362
 363     /* Verify checksum against file header */
 364     if (checksum != file_checksum) {
 365         rolo_error("Checksum Error");
 366         return -1;
 367     }
 368
 369 #ifdef HAVE_STORAGE_FLUSH
 370     lcd_puts(0, 1, "Flushing      ");
 371     lcd_update();
 372     storage_flush();
 373 #endif
 374
 375     lcd_puts(0, 1, "Executing     ");
 376     lcd_update();
 377
 378     set_irq_level(HIGHEST_IRQ_LEVEL);
 379
 380     /* Calling these 2 initialization routines was necessary to get the
 381        the origional Archos version of the firmware to load and execute. */
 382     system_init();           /* Initialize system for restart */
 383     i2c_init();              /* Init i2c bus - it seems like a good idea */
 384     ICR = IRQ0_EDGE_TRIGGER; /* Make IRQ0 edge triggered */
 385     TSTR = 0xE0;             /* disable all timers */
 386     /* model-specific de-init, needed when flashed */
 387     /* Especially the Archos software is picky about this */
 388 #if defined(ARCHOS_RECORDER) || defined(ARCHOS_RECORDERV2) || \
 389     defined(ARCHOS_FMRECORDER)
 390     PAIOR = 0x0FA0;
 391 #endif
 392 #endif
 393     rolo_restart(filebuf, ramstart, length);
 394
 395     return 0; /* this is never reached */
 396     (void)checksum; (void)file_checksum;
 397 }
 398 #else  /* !defined(IRIVER_IFP7XX_SERIES) */
 399 int rolo_load(const char* filename)
 400 {
 401     /* dummy */
 402     (void)filename;
 403     return 0;
 404 }
 405
 406 #endif /* !defined(IRIVER_IFP7XX_SERIES) */