firmware/export/pp5020.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2004 by Thom Johansen
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef __PP5020_H__
  22 #define __PP5020_H__
  23
  24 /* All info gleaned and/or copied from the iPodLinux project. */
  25
  26 #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
  27
  28 /* PCM addresses for obtaining buffers will be what DMA is using (physical) */
  29 #define HAVE_PCM_DMA_ADDRESS
  30
  31 /* USBOTG */
  32 #define USB_NUM_ENDPOINTS  3
  33 /* This needs to be 2048 byte aligned, but USB_QHARRAY_ATTR should take care
  34  * of that */
  35 #define USB_QHARRAY_ATTR   __attribute__((section(".qharray"),nocommon,aligned(4)))
  36 #define USB_DEVBSS_ATTR    IBSS_ATTR
  37
  38 /* DRAM starts at 0x10000000, but in Rockbox we remap it to 0x00000000 */
  39 #define DRAM_START       0x10000000
  40
  41 /* Processor ID */
  42 #define PROCESSOR_ID     (*(volatile unsigned long *)(0x60000000))
  43
  44 #define PROC_ID_CPU      0x55
  45 #define PROC_ID_COP      0xaa
  46
  47 /* Mailboxes */
  48 #define MBX_BASE            (0x60001000)
  49 /* Read bits in the mailbox */
  50 #define MBX_MSG_STAT        (*(volatile unsigned long *)(0x60001000))
  51 /* Set bits in the mailbox */
  52 #define MBX_MSG_SET         (*(volatile unsigned long *)(0x60001004))
  53 /* Clear bits in the mailbox */
  54 #define MBX_MSG_CLR         (*(volatile unsigned long *)(0x60001008))
  55 /* Doesn't seem to be COP_REPLY at all :) */
  56 #define MBX_UNKNOWN1        (*(volatile unsigned long *)(0x6000100c))
  57 /* COP can set bit 29 - only CPU read clears it */
  58 #define CPU_QUEUE           (*(volatile unsigned long *)(0x60001010))
  59 /* CPU can set bit 29 - only COP read clears it */
  60 #define COP_QUEUE           (*(volatile unsigned long *)(0x60001020))
  61
  62 #define PROC_QUEUE(core)    ((&CPU_QUEUE)[(core)*4])
  63
  64 /* Interrupts */
  65 #define CPU_INT_STAT        (*(volatile unsigned long*)(0x60004000))
  66 #define COP_INT_STAT        (*(volatile unsigned long*)(0x60004004))
  67 #define CPU_FIQ_STAT        (*(volatile unsigned long*)(0x60004008))
  68 #define COP_FIQ_STAT        (*(volatile unsigned long*)(0x6000400c))
  69
  70 #define INT_STAT            (*(volatile unsigned long*)(0x60004010))
  71 #define INT_FORCED_STAT     (*(volatile unsigned long*)(0x60004014))
  72 #define INT_FORCED_SET      (*(volatile unsigned long*)(0x60004018))
  73 #define INT_FORCED_CLR      (*(volatile unsigned long*)(0x6000401c))
  74
  75 #define CPU_INT_EN_STAT     (*(volatile unsigned long*)(0x60004020))
  76 #define CPU_INT_EN          (*(volatile unsigned long*)(0x60004024))
  77 #define CPU_INT_DIS         (*(volatile unsigned long*)(0x60004028))
  78 #define CPU_INT_PRIORITY    (*(volatile unsigned long*)(0x6000402c))
  79
  80 #define COP_INT_EN_STAT     (*(volatile unsigned long*)(0x60004030))
  81 #define COP_INT_EN          (*(volatile unsigned long*)(0x60004034))
  82 #define COP_INT_DIS         (*(volatile unsigned long*)(0x60004038))
  83 #define COP_INT_PRIORITY    (*(volatile unsigned long*)(0x6000403c))
  84
  85 #define CPU_HI_INT_STAT     (*(volatile unsigned long*)(0x60004100))
  86 #define COP_HI_INT_STAT     (*(volatile unsigned long*)(0x60004104))
  87 #define CPU_HI_FIQ_STAT     (*(volatile unsigned long*)(0x60004108))
  88 #define COP_HI_FIQ_STAT     (*(volatile unsigned long*)(0x6000410c))
  89
  90 #define HI_INT_STAT         (*(volatile unsigned long*)(0x60004110))
  91 #define HI_INT_FORCED_STAT  (*(volatile unsigned long*)(0x60004114))
  92 #define HI_INT_FORCED_SET   (*(volatile unsigned long*)(0x60004118))
  93 #define HI_INT_FORCED_CLR   (*(volatile unsigned long*)(0x6000411c))
  94
  95 #define CPU_HI_INT_EN_STAT  (*(volatile unsigned long*)(0x60004120))
  96 #define CPU_HI_INT_EN       (*(volatile unsigned long*)(0x60004124))
  97 #define CPU_HI_INT_DIS      (*(volatile unsigned long*)(0x60004128))
  98 #define CPU_HI_INT_PRIORITY (*(volatile unsigned long*)(0x6000412c))
  99
 100 #define COP_HI_INT_EN_STAT  (*(volatile unsigned long*)(0x60004130))
 101 #define COP_HI_INT_EN       (*(volatile unsigned long*)(0x60004134))
 102 #define COP_HI_INT_DIS      (*(volatile unsigned long*)(0x60004138))
 103 #define COP_HI_INT_PRIORITY (*(volatile unsigned long*)(0x6000413c))
 104
 105 #define TIMER1_IRQ   0
 106 #define TIMER2_IRQ   1
 107 #define MAILBOX_IRQ  4
 108 #define IIS_IRQ      10
 109 #define USB_IRQ      20
 110 #define IDE_IRQ      23
 111 #define FIREWIRE_IRQ 25
 112 #define DMA_IRQ      26
 113 #define HI_IRQ       30
 114 #define GPIO0_IRQ    (32+0) /* Ports A..D */
 115 #define GPIO1_IRQ    (32+1) /* Ports E..H */
 116 #define GPIO2_IRQ    (32+2) /* Ports I..L */
 117 #define SER0_IRQ     (32+4)
 118 #define SER1_IRQ     (32+5)
 119 #define I2C_IRQ      (32+8)
 120
 121 #define TIMER1_MASK   (1 << TIMER1_IRQ)
 122 #define TIMER2_MASK   (1 << TIMER2_IRQ)
 123 #define MAILBOX_MASK  (1 << MAILBOX_IRQ)
 124 #define IIS_MASK      (1 << IIS_IRQ)
 125 #define IDE_MASK      (1 << IDE_IRQ)
 126 #define USB_MASK      (1 << USB_IRQ)
 127 #define FIREWIRE_MASK (1 << FIREWIRE_IRQ)
 128 #define DMA_MASK      (1 << DMA_IRQ)
 129 #define HI_MASK       (1 << HI_IRQ)
 130 #define GPIO0_MASK    (1 << (GPIO0_IRQ-32))
 131 #define GPIO1_MASK    (1 << (GPIO1_IRQ-32))
 132 #define GPIO2_MASK    (1 << (GPIO2_IRQ-32))
 133 #define SER0_MASK     (1 << (SER0_IRQ-32))
 134 #define SER1_MASK     (1 << (SER1_IRQ-32))
 135 #define I2C_MASK      (1 << (I2C_IRQ-32))
 136
 137 /* Timers */
 138 #define TIMER1_CFG   (*(volatile unsigned long *)(0x60005000))
 139 #define TIMER1_VAL   (*(volatile unsigned long *)(0x60005004))
 140 #define TIMER2_CFG   (*(volatile unsigned long *)(0x60005008))
 141 #define TIMER2_VAL   (*(volatile unsigned long *)(0x6000500c))
 142 #define USEC_TIMER   (*(volatile unsigned long *)(0x60005010))
 143 #define RTC          (*(volatile unsigned long *)(0x60005014))
 144
 145 /* Device Controller */
 146 #define DEV_RS       (*(volatile unsigned long *)(0x60006004))
 147 #define DEV_RS2      (*(volatile unsigned long *)(0x60006008))
 148 #define DEV_EN       (*(volatile unsigned long *)(0x6000600c))
 149 #define DEV_EN2      (*(volatile unsigned long *)(0x60006010))
 150
 151 #define DEV_EXTCLOCKS   0x00000002
 152 #define DEV_SYSTEM      0x00000004
 153 #define DEV_USB0        0x00000008
 154 #define DEV_SER0        0x00000040
 155 #define DEV_SER1        0x00000080
 156 #define DEV_I2S         0x00000800
 157 #define DEV_I2C         0x00001000
 158 #define DEV_ATA         0x00004000
 159 #define DEV_OPTO        0x00010000
 160 #define DEV_PIEZO       0x00010000
 161 #define DEV_PWM         0x00020000
 162 #define DEV_USB1        0x00400000
 163 #define DEV_FIREWIRE    0x00800000
 164 #define DEV_IDE0        0x02000000
 165 #define DEV_LCD         0x04000000
 166
 167 /* clock control */
 168 #define CLOCK_SOURCE    (*(volatile unsigned long *)(0x60006020))
 169 #define MLCD_SCLK_DIV   (*(volatile unsigned long *)(0x6000602c))
 170         /* bits 0..1: Mono LCD bridge serial clock divider: 1 / (n+1) */
 171 #define PLL_CONTROL     (*(volatile unsigned long *)(0x60006034))
 172 #define PLL_STATUS      (*(volatile unsigned long *)(0x6000603c))
 173 #define ADC_CLOCK_SRC   (*(volatile unsigned long *)(0x60006094))
 174 #define CLCD_CLOCK_SRC  (*(volatile unsigned long *)(0x600060a0))
 175
 176 /* Processors Control */
 177 #define CPU_CTL          (*(volatile unsigned long *)(0x60007000))
 178 #define COP_CTL          (*(volatile unsigned long *)(0x60007004))
 179 #define PROC_CTL(core)   ((&CPU_CTL)[core])
 180
 181 /* Control flags, can be ORed together */
 182 #define PROC_SLEEP     0x80000000  /* Sleep until an interrupt occurs */
 183 #define PROC_WAIT_CNT  0x40000000  /* Sleep until end of countdown */
 184 #define PROC_WAKE_INT  0x20000000  /* Fire interrupt on wake-up. Auto-clears. */
 185
 186 /* Counter source, select one */
 187 #define PROC_CNT_CLKS  0x08000000  /* Clock cycles */
 188 #define PROC_CNT_USEC  0x02000000  /* Microseconds */
 189 #define PROC_CNT_MSEC  0x01000000  /* Milliseconds */
 190 #define PROC_CNT_SEC   0x00800000  /* Seconds. Works on PP5022+ only! */
 191
 192 #define PROC_WAKE      0x00000000
 193
 194 /**
 195  * [22:8] - Semaphore flags for core communication? No execution effect observed
 196  *          [11:8] seem to often be set to the core's own ID
 197  *                 nybble when sleeping - 0x5 or 0xa.
 198  *  [7:0] - W: number of cycles to skip on next instruction
 199  *          R: cycles remaining
 200  * Executing on CPU
 201  *   CPU_CTL = 0x68000080
 202  *   nop
 203  * stalls the nop for 128 cycles
 204  * Reading CPU_CTL after the nop will return 0x48000000
 205  */
 206
 207
 208 /* Cache Control */
 209 #define CACHE_PRIORITY   (*(volatile unsigned long *)(0x60006044))
 210 #define CACHE_CTL        (*(volatile unsigned long *)(0x6000c000))
 211 #define CACHE_MASK       (*(volatile unsigned long *)(0xf000f040))
 212 #define CACHE_OPERATION  (*(volatile unsigned long *)(0xf000f044))
 213 #define CACHE_FLUSH_MASK (*(volatile unsigned long *)(0xf000f048))
 214
 215 /* CACHE_CTL bits */
 216 #define CACHE_CTL_DISABLE    0x0000
 217 #define CACHE_CTL_ENABLE     0x0001
 218 #define CACHE_CTL_RUN        0x0002
 219 #define CACHE_CTL_INIT       0x0004
 220 #define CACHE_CTL_VECT_REMAP 0x0010
 221 #define CACHE_CTL_READY      0x4000
 222 #define CACHE_CTL_BUSY       0x8000
 223 /* CACHE_OPERATION bits */
 224 #define CACHE_OP_FLUSH       0x0002
 225 #define CACHE_OP_INVALIDATE  0x0004
 226
 227 /* Local interrupt vector table (set CACHE_CTL_VECT_REMAP to enable) */
 228 #define INT_VECTOR_ENTRY(v) (*((volatile unsigned long *)(0x6000f100) + (v)))
 229
 230 /* GPIO Ports */
 231 #define GPIO_BASE_ADDR   0x6000d000
 232 #define GPIOA_ENABLE     (*(volatile unsigned long *)(0x6000d000))
 233 #define GPIOB_ENABLE     (*(volatile unsigned long *)(0x6000d004))
 234 #define GPIOC_ENABLE     (*(volatile unsigned long *)(0x6000d008))
 235 #define GPIOD_ENABLE     (*(volatile unsigned long *)(0x6000d00c))
 236 #define GPIOA_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d010))
 237 #define GPIOB_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d014))
 238 #define GPIOC_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d018))
 239 #define GPIOD_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d01c))
 240 #define GPIOA_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d020))
 241 #define GPIOB_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d024))
 242 #define GPIOC_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d028))
 243 #define GPIOD_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d02c))
 244 #define GPIOA_INPUT_VAL  (*(volatile unsigned long *)(0x6000d030))
 245 #define GPIOB_INPUT_VAL  (*(volatile unsigned long *)(0x6000d034))
 246 #define GPIOC_INPUT_VAL  (*(volatile unsigned long *)(0x6000d038))
 247 #define GPIOD_INPUT_VAL  (*(volatile unsigned long *)(0x6000d03c))
 248 #define GPIOA_INT_STAT   (*(volatile unsigned long *)(0x6000d040))
 249 #define GPIOB_INT_STAT   (*(volatile unsigned long *)(0x6000d044))
 250 #define GPIOC_INT_STAT   (*(volatile unsigned long *)(0x6000d048))
 251 #define GPIOD_INT_STAT   (*(volatile unsigned long *)(0x6000d04c))
 252 #define GPIOA_INT_EN     (*(volatile unsigned long *)(0x6000d050))
 253 #define GPIOB_INT_EN     (*(volatile unsigned long *)(0x6000d054))
 254 #define GPIOC_INT_EN     (*(volatile unsigned long *)(0x6000d058))
 255 #define GPIOD_INT_EN     (*(volatile unsigned long *)(0x6000d05c))
 256 #define GPIOA_INT_LEV    (*(volatile unsigned long *)(0x6000d060))
 257 #define GPIOB_INT_LEV    (*(volatile unsigned long *)(0x6000d064))
 258 #define GPIOC_INT_LEV    (*(volatile unsigned long *)(0x6000d068))
 259 #define GPIOD_INT_LEV    (*(volatile unsigned long *)(0x6000d06c))
 260 #define GPIOA_INT_CLR    (*(volatile unsigned long *)(0x6000d070))
 261 #define GPIOB_INT_CLR    (*(volatile unsigned long *)(0x6000d074))
 262 #define GPIOC_INT_CLR    (*(volatile unsigned long *)(0x6000d078))
 263 #define GPIOD_INT_CLR    (*(volatile unsigned long *)(0x6000d07c))
 264
 265 #define GPIOE_ENABLE     (*(volatile unsigned long *)(0x6000d080))
 266 #define GPIOF_ENABLE     (*(volatile unsigned long *)(0x6000d084))
 267 #define GPIOG_ENABLE     (*(volatile unsigned long *)(0x6000d088))
 268 #define GPIOH_ENABLE     (*(volatile unsigned long *)(0x6000d08c))
 269 #define GPIOE_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d090))
 270 #define GPIOF_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d094))
 271 #define GPIOG_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d098))
 272 #define GPIOH_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d09c))
 273 #define GPIOE_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0a0))
 274 #define GPIOF_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0a4))
 275 #define GPIOG_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0a8))
 276 #define GPIOH_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0ac))
 277 #define GPIOE_INPUT_VAL  (*(volatile unsigned long *)(0x6000d0b0))
 278 #define GPIOF_INPUT_VAL  (*(volatile unsigned long *)(0x6000d0b4))
 279 #define GPIOG_INPUT_VAL  (*(volatile unsigned long *)(0x6000d0b8))
 280 #define GPIOH_INPUT_VAL  (*(volatile unsigned long *)(0x6000d0bc))
 281 #define GPIOE_INT_STAT   (*(volatile unsigned long *)(0x6000d0c0))
 282 #define GPIOF_INT_STAT   (*(volatile unsigned long *)(0x6000d0c4))
 283 #define GPIOG_INT_STAT   (*(volatile unsigned long *)(0x6000d0c8))
 284 #define GPIOH_INT_STAT   (*(volatile unsigned long *)(0x6000d0cc))
 285 #define GPIOE_INT_EN     (*(volatile unsigned long *)(0x6000d0d0))
 286 #define GPIOF_INT_EN     (*(volatile unsigned long *)(0x6000d0d4))
 287 #define GPIOG_INT_EN     (*(volatile unsigned long *)(0x6000d0d8))
 288 #define GPIOH_INT_EN     (*(volatile unsigned long *)(0x6000d0dc))
 289 #define GPIOE_INT_LEV    (*(volatile unsigned long *)(0x6000d0e0))
 290 #define GPIOF_INT_LEV    (*(volatile unsigned long *)(0x6000d0e4))
 291 #define GPIOG_INT_LEV    (*(volatile unsigned long *)(0x6000d0e8))
 292 #define GPIOH_INT_LEV    (*(volatile unsigned long *)(0x6000d0ec))
 293 #define GPIOE_INT_CLR    (*(volatile unsigned long *)(0x6000d0f0))
 294 #define GPIOF_INT_CLR    (*(volatile unsigned long *)(0x6000d0f4))
 295 #define GPIOG_INT_CLR    (*(volatile unsigned long *)(0x6000d0f8))
 296 #define GPIOH_INT_CLR    (*(volatile unsigned long *)(0x6000d0fc))
 297
 298 #define GPIOI_ENABLE     (*(volatile unsigned long *)(0x6000d100))
 299 #define GPIOJ_ENABLE     (*(volatile unsigned long *)(0x6000d104))
 300 #define GPIOK_ENABLE     (*(volatile unsigned long *)(0x6000d108))
 301 #define GPIOL_ENABLE     (*(volatile unsigned long *)(0x6000d10c))
 302 #define GPIOI_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d110))
 303 #define GPIOJ_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d114))
 304 #define GPIOK_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d118))
 305 #define GPIOL_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d11c))
 306 #define GPIOI_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d120))
 307 #define GPIOJ_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d124))
 308 #define GPIOK_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d128))
 309 #define GPIOL_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d12c))
 310 #define GPIOI_INPUT_VAL  (*(volatile unsigned long *)(0x6000d130))
 311 #define GPIOJ_INPUT_VAL  (*(volatile unsigned long *)(0x6000d134))
 312 #define GPIOK_INPUT_VAL  (*(volatile unsigned long *)(0x6000d138))
 313 #define GPIOL_INPUT_VAL  (*(volatile unsigned long *)(0x6000d13c))
 314 #define GPIOI_INT_STAT   (*(volatile unsigned long *)(0x6000d140))
 315 #define GPIOJ_INT_STAT   (*(volatile unsigned long *)(0x6000d144))
 316 #define GPIOK_INT_STAT   (*(volatile unsigned long *)(0x6000d148))
 317 #define GPIOL_INT_STAT   (*(volatile unsigned long *)(0x6000d14c))
 318 #define GPIOI_INT_EN     (*(volatile unsigned long *)(0x6000d150))
 319 #define GPIOJ_INT_EN     (*(volatile unsigned long *)(0x6000d154))
 320 #define GPIOK_INT_EN     (*(volatile unsigned long *)(0x6000d158))
 321 #define GPIOL_INT_EN     (*(volatile unsigned long *)(0x6000d15c))
 322 #define GPIOI_INT_LEV    (*(volatile unsigned long *)(0x6000d160))
 323 #define GPIOJ_INT_LEV    (*(volatile unsigned long *)(0x6000d164))
 324 #define GPIOK_INT_LEV    (*(volatile unsigned long *)(0x6000d168))
 325 #define GPIOL_INT_LEV    (*(volatile unsigned long *)(0x6000d16c))
 326 #define GPIOI_INT_CLR    (*(volatile unsigned long *)(0x6000d170))
 327 #define GPIOJ_INT_CLR    (*(volatile unsigned long *)(0x6000d174))
 328 #define GPIOK_INT_CLR    (*(volatile unsigned long *)(0x6000d178))
 329 #define GPIOL_INT_CLR    (*(volatile unsigned long *)(0x6000d17c))
 330
 331 /* Standard GPIO addresses + 0x800 allow atomic port manipulation on PP502x.
 332  * Bits 8..15 of the written word define which bits are changed, bits 0..7
 333  * define the value of those bits. */
 334
 335 #define GPIO_SET_BITWISE(port, mask) \
 336         do { *(&(port) + (0x800/sizeof(long))) = ((mask) << 8) | (mask); } while(0)
 337
 338 #define GPIO_CLEAR_BITWISE(port, mask) \
 339         do { *(&(port) + (0x800/sizeof(long))) = (mask) << 8; } while(0)
 340
 341 #define GPIO_WRITE_BITWISE(port, val, mask) \
 342         do { *(&(port) + (0x800/sizeof(long))) = ((mask) << 8) | (val); } while(0)
 343
 344 /* GPIO Module 0 */
 345 #define GPIOA  0
 346 #define GPIOB  1
 347 #define GPIOC  2
 348 #define GPIOD  3
 349 /* GPIO Module 1 */
 350 #define GPIOE  4
 351 #define GPIOF  5
 352 #define GPIOG  6
 353 #define GPIOH  7
 354 /* GPIO Module 2 */
 355 #define GPIOI  8
 356 #define GPIOJ  9
 357 #define GPIOK 10
 358 #define GPIOL 11
 359
 360 #define GPIO_MODULE_NUM(gpio)   ((gpio)>>2)
 361 #define GPIO_MAP_ADDR(gpio)     (GPIO_BASE_ADDR+(GPIO_MODULE_NUM(gpio)<<7)+(((gpio)&3)<<2))
 362 #define GPIO_ENABLE(gpio)       (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x00))
 363 #define GPIO_OUTPUT_EN(gpio)    (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x10))
 364 #define GPIO_OUTPUT_VAL(gpio)   (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x20))
 365 #define GPIO_INPUT_VAL(gpio)    (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x30))
 366 #define GPIO_INT_STAT(gpio)     (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x40))
 367 #define GPIO_INT_EN(gpio)       (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x50))
 368 #define GPIO_INT_LEV(gpio)      (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x60))
 369 #define GPIO_INT_CLR(gpio)      (*(volatile unsigned long *)(GPIO_MAP_ADDR(gpio)+0x70))
 370 #define GPIO_HI_INT_MASK(gpio)  (1ul << GPIO_MODULE_NUM(gpio))
 371
 372 /* Device initialization */
 373 #define PP_VER1          (*(volatile unsigned long *)(0x70000000))
 374 #define PP_VER2          (*(volatile unsigned long *)(0x70000004))
 375 #define STRAP_OPT_A      (*(volatile unsigned long *)(0x70000008))
 376 #define STRAP_OPT_B      (*(volatile unsigned long *)(0x7000000c))
 377 #define BUS_WIDTH_MASK   0x00000010
 378 #define RAM_TYPE_MASK    0x000000c0
 379 #define ROM_TYPE_MASK    0x00000008
 380
 381 #define DEV_INIT1        (*(volatile unsigned long *)(0x70000010))
 382 #define DEV_INIT2        (*(volatile unsigned long *)(0x70000020))
 383 /* some timing that needs to be handled during clock setup */
 384 #define DEV_TIMING1      (*(volatile unsigned long *)(0x70000034))
 385 #define XMB_NOR_CFG      (*(volatile unsigned long *)(0x70000038))
 386 #define XMB_RAM_CFG      (*(volatile unsigned long *)(0x7000003c))
 387
 388 #define INIT_BUTTONS     0x00040000
 389 #define INIT_PLL         0x40000000
 390 #define INIT_USB         0x80000000
 391
 392 /* 32 bit GPO port */
 393 #define GPO32_VAL        (*(volatile unsigned long *)(0x70000080))
 394 #define GPO32_ENABLE     (*(volatile unsigned long *)(0x70000084))
 395
 396 /* IIS */
 397 #define IISDIV              (*(volatile unsigned long*)(0x60006080))
 398 #define IISCONFIG           (*(volatile unsigned long*)(0x70002800))
 399 #define IISCLK              (*(volatile unsigned long*)(0x70002808))
 400 #define IISFIFO_CFG         (*(volatile unsigned long*)(0x7000280c))
 401 #define IISFIFO_WR          (*(volatile unsigned long*)(0x70002840))
 402 #define IISFIFO_WRH         (*(volatile unsigned short*)(0x70002840))
 403 #define IISFIFO_RD          (*(volatile unsigned long*)(0x70002880))
 404 #define IISFIFO_RDH         (*(volatile unsigned short*)(0x70002880))
 405
 406 /**
 407  * IISCONFIG bits:
 408  * |   31   |   30   |   29   |   28   |   27   |   26   |   25   |   24   |
 409  * | RESET  |        |TXFIFOEN|RXFIFOEN|        |  ????  |   MS   |  ????  |
 410  * |   23   |   22   |   21   |   20   |   19   |   18   |   17   |   16   |
 411  * |        |        |        |        |        |        |        |        |
 412  * |   15   |   14   |   13   |   12   |   11   |   10   |    9   |    8   |
 413  * |        |        |        |        | Bus Format[1:0] |     Size[1:0]   |
 414  * |    7   |    6   |    5   |    4   |    3   |    2   |    1   |    0   |
 415  * |        |     Size Format[2:0]     |  ????  |  ????  | IRQTX  | IRQRX  |
 416  */
 417
 418 /* All IIS formats send MSB first */
 419 #define IIS_RESET    (1 << 31)
 420 #define IIS_TXFIFOEN (1 << 29)
 421 #define IIS_RXFIFOEN (1 << 28)
 422 #define IIS_MASTER   (1 << 25)
 423 #define IIS_IRQTX    (1 << 1)
 424 #define IIS_IRQRX    (1 << 0)
 425
 426 #define IIS_IRQTX_REG  IISCONFIG
 427 #define IIS_IRQRX_REG  IISCONFIG
 428
 429 /* Data format on the IIS bus */
 430 #define IIS_FORMAT_MASK  (0x3 << 10)
 431 #define IIS_FORMAT_IIS   (0x0 << 10) /* Standard IIS - leading dummy bit */
 432 #define IIS_FORMAT_1     (0x1 << 10)
 433 #define IIS_FORMAT_LJUST (0x2 << 10) /* Left justified - no dummy bit */
 434 #define IIS_FORMAT_3     (0x3 << 10)
 435 /* Other formats not yet known  */
 436
 437 /* Data size on IIS bus */
 438 #define IIS_SIZE_MASK   (0x3 << 8)
 439 #define IIS_SIZE_16BIT  (0x0 << 8)
 440 /* Other sizes not yet known */
 441
 442 /* Data size/format on IIS FIFO */
 443 #define IIS_FIFO_FORMAT_MASK        (0x7 << 4)
 444 #define IIS_FIFO_FORMAT_LE_HALFWORD (0x0 << 4)
 445 /* Big-endian formats - data sent to the FIFO must be big endian.
 446  * I forgot which is which size but did test them. */
 447 #define IIS_FIFO_FORMAT_1           (0x1 << 4)
 448 #define IIS_FIFO_FORMAT_2           (0x2 << 4)
 449 /* 32bit-MSB-little endian */
 450 #define IIS_FIFO_FORMAT_LE32        (0x3 << 4)
 451 /* 16bit-MSB-little endian */
 452 #define IIS_FIFO_FORMAT_LE16        (0x4 << 4)
 453 #define IIS_FIFO_FORMAT_5           (0x5 << 4)
 454 #define IIS_FIFO_FORMAT_6           (0x6 << 4)
 455 /* A second one like IIS_FIFO_FORMAT_LE16? PP5020 only? */
 456 #define IIS_FIFO_FORMAT_LE16_2      (0x7 << 4)
 457
 458 /* FIFO formats 0x5 and above seem equivalent to 0x4 ?? */
 459
 460 /**
 461  * IISFIFO_CFG bits:
 462  * |   31   |   30   |   29   |   28   |   27   |   26   |   25   |   24   |
 463  * |        |        |                      RXFull[5:0]                    |
 464  * |   23   |   22   |   21   |   20   |   19   |   18   |   17   |   16   |
 465  * |        |        |                      TXFree[5:0]                    |
 466  * |   15   |   14   |   13   |   12   |   11   |   10   |    9   |    8   |
 467  * |        |        |        | RXCLR  |        |        |        | TXCLR  |
 468  * |    7   |    6   |    5   |    4   |    3   |    2   |    1   |    0   |
 469  * |        |        |   RX_FULL_LVL   |        |        |  TX_EMPTY_LVL   |
 470  */
 471
 472 /* handy macros to extract the FIFO counts */
 473 #define IIS_RX_FULL_MASK (0x3f << 24)
 474 #define IIS_RX_FULL_COUNT \
 475     ((IISFIFO_CFG & IIS_RX_FULL_MASK) >> 24)
 476
 477 #define IIS_TX_FREE_MASK (0x3f << 16)
 478 #define IIS_TX_FREE_COUNT \
 479     ((IISFIFO_CFG & IIS_TX_FREE_MASK) >> 16)
 480
 481 #define IIS_TX_IS_EMPTY \
 482     ((IISFIFO_CFG & IIS_TX_FREE_MASK) >= (16 << 16))
 483
 484 #define IIS_RXCLR (1 << 12)
 485 #define IIS_TXCLR (1 << 8)
 486 /* Number of slots */
 487 #define IIS_RX_FULL_LVL_4  (0x1 << 4)
 488 #define IIS_RX_FULL_LVL_8  (0x2 << 4)
 489 #define IIS_RX_FULL_LVL_12 (0x3 << 4)
 490
 491 #define IIS_TX_EMPTY_LVL_4  (0x1 << 0)
 492 #define IIS_TX_EMPTY_LVL_8  (0x2 << 0)
 493 #define IIS_TX_EMPTY_LVL_12 (0x3 << 0)
 494
 495 /* Note: didn't bother to see of levels 0 and 16 actually work */
 496
 497 /* First ("mono") LCD bridge */
 498 #define LCD1_BASE           0x70003000
 499
 500 #define LCD1_CONTROL        (*(volatile unsigned long *)(0x70003000))
 501 #define LCD1_CMD            (*(volatile unsigned long *)(0x70003008))
 502 #define LCD1_DATA           (*(volatile unsigned long *)(0x70003010))
 503
 504 #define LCD1_BUSY_MASK      0x8000
 505
 506 /* Serial Controller */
 507 #define SER0_BASE           (*(volatile unsigned long*)(0x70006000))
 508
 509 #define SER0_RBR            (*(volatile unsigned long*)(0x70006000))
 510 #define SER0_THR            (*(volatile unsigned long*)(0x70006000))
 511 #define SER0_IER            (*(volatile unsigned long*)(0x70006004))
 512 #define SER0_FCR            (*(volatile unsigned long*)(0x70006008))
 513 #define SER0_IIR            (*(volatile unsigned long*)(0x70006008))
 514 #define SER0_LCR            (*(volatile unsigned long*)(0x7000600c))
 515 #define SER0_MCR            (*(volatile unsigned long*)(0x70006010))
 516 #define SER0_LSR            (*(volatile unsigned long*)(0x70006014))
 517 #define SER0_MSR            (*(volatile unsigned long*)(0x70006018))
 518 #define SER0_SPR            (*(volatile unsigned long*)(0x7000601c))
 519
 520 #define SER0_DLL            (*(volatile unsigned long*)(0x70006000))
 521 #define SER0_DLM            (*(volatile unsigned long*)(0x70006004))
 522
 523 #define SER1_BASE           (*(volatile unsigned long*)(0x70006040))
 524
 525 #define SER1_RBR            (*(volatile unsigned long*)(0x70006040))
 526 #define SER1_THR            (*(volatile unsigned long*)(0x70006040))
 527 #define SER1_IER            (*(volatile unsigned long*)(0x70006044))
 528 #define SER1_FCR            (*(volatile unsigned long*)(0x70006048))
 529 #define SER1_IIR            (*(volatile unsigned long*)(0x70006048))
 530 #define SER1_LCR            (*(volatile unsigned long*)(0x7000604c))
 531 #define SER1_MCR            (*(volatile unsigned long*)(0x70006050))
 532 #define SER1_LSR            (*(volatile unsigned long*)(0x70006054))
 533 #define SER1_MSR            (*(volatile unsigned long*)(0x70006058))
 534 #define SER1_SPR            (*(volatile unsigned long*)(0x7000605c))
 535
 536 #define SER1_DLL            (*(volatile unsigned long*)(0x70006040))
 537 #define SER1_DLM            (*(volatile unsigned long*)(0x70006044))
 538
 539 /* Second ("color") LCD bridge */
 540 #define LCD2_BASE           0x70008a00
 541
 542 #define LCD2_PORT           (*(volatile unsigned long*)(0x70008a0c))
 543 #define LCD2_BLOCK_CTRL     (*(volatile unsigned long*)(0x70008a20))
 544 #define LCD2_BLOCK_CONFIG   (*(volatile unsigned long*)(0x70008a24))
 545 #define LCD2_BLOCK_DATA     (*(volatile unsigned long*)(0x70008b00))
 546
 547 #define LCD2_BUSY_MASK      0x80000000
 548 #define LCD2_CMD_MASK       0x80000000
 549 #define LCD2_DATA_MASK      0x81000000
 550
 551 #define LCD2_BLOCK_READY    0x04000000
 552 #define LCD2_BLOCK_TXOK     0x01000000
 553
 554 /* I2C */
 555 #define I2C_BASE            0x7000c000
 556
 557 /* EIDE Controller */
 558 #define IDE_BASE            0xc3000000
 559
 560 #define IDE0_PRI_TIMING0    (*(volatile unsigned long*)(0xc3000000))
 561 #define IDE0_PRI_TIMING1    (*(volatile unsigned long*)(0xc3000004))
 562 #define IDE0_SEC_TIMING0    (*(volatile unsigned long*)(0xc3000008))
 563 #define IDE0_SEC_TIMING1    (*(volatile unsigned long*)(0xc300000c))
 564
 565 #define IDE1_PRI_TIMING0    (*(volatile unsigned long*)(0xc3000010))
 566 #define IDE1_PRI_TIMING1    (*(volatile unsigned long*)(0xc3000014))
 567 #define IDE1_SEC_TIMING0    (*(volatile unsigned long*)(0xc3000018))
 568 #define IDE1_SEC_TIMING1    (*(volatile unsigned long*)(0xc300001c))
 569
 570 #define IDE0_CFG            (*(volatile unsigned long*)(0xc3000028))
 571 #define IDE1_CFG            (*(volatile unsigned long*)(0xc300002c))
 572
 573 #define IDE0_CNTRLR_STAT    (*(volatile unsigned long*)(0xc30001e0))
 574
 575 /* USB controller */
 576 #define USB_BASE            0xc5000000
 577
 578 /* Firewire Controller */
 579 #define FIREWIRE_BASE       0xc6000000
 580
 581 /* Memory controller */
 582 #define CACHE_BASE              (*(volatile unsigned long*)(0xf0000000))
 583 /* 0xf0000000-0xf0001fff */
 584 #define CACHE_DATA_BASE         (*(volatile unsigned long*)(0xf0000000))
 585 /* 0xf0002000-0xf0003fff */
 586 #define CACHE_DATA_MIRROR_BASE  (*(volatile unsigned long*)(0xf0002000))
 587 /* 0xf0004000-0xf0007fff */
 588 #define CACHE_STATUS_BASE       (*(volatile unsigned long*)(0xf0004000))
 589 #define CACHE_FLUSH_BASE        (*(volatile unsigned long*)(0xf0008000))
 590 #define CACHE_INVALID_BASE      (*(volatile unsigned long*)(0xf000c000))
 591 #define MMAP_PHYS_READ_MASK     0x0100
 592 #define MMAP_PHYS_WRITE_MASK    0x0200
 593 #define MMAP_PHYS_DATA_MASK     0x0400
 594 #define MMAP_PHYS_CODE_MASK     0x0800
 595 #define MMAP_FIRST              (*(volatile unsigned long*)(0xf000f000))
 596 #define MMAP_LAST               (*(volatile unsigned long*)(0xf000f03c))
 597 #define MMAP0_LOGICAL           (*(volatile unsigned long*)(0xf000f000))
 598 #define MMAP0_PHYSICAL          (*(volatile unsigned long*)(0xf000f004))
 599 #define MMAP1_LOGICAL           (*(volatile unsigned long*)(0xf000f008))
 600 #define MMAP1_PHYSICAL          (*(volatile unsigned long*)(0xf000f00c))
 601 #define MMAP2_LOGICAL           (*(volatile unsigned long*)(0xf000f010))
 602 #define MMAP2_PHYSICAL          (*(volatile unsigned long*)(0xf000f014))
 603 #define MMAP3_LOGICAL           (*(volatile unsigned long*)(0xf000f018))
 604 #define MMAP3_PHYSICAL          (*(volatile unsigned long*)(0xf000f01c))
 605 #define MMAP4_LOGICAL           (*(volatile unsigned long*)(0xf000f020))
 606 #define MMAP4_PHYSICAL          (*(volatile unsigned long*)(0xf000f024))
 607 #define MMAP5_LOGICAL           (*(volatile unsigned long*)(0xf000f028))
 608 #define MMAP5_PHYSICAL          (*(volatile unsigned long*)(0xf000f02c))
 609 #define MMAP6_LOGICAL           (*(volatile unsigned long*)(0xf000f030))
 610 #define MMAP6_PHYSICAL          (*(volatile unsigned long*)(0xf000f034))
 611 #define MMAP7_LOGICAL           (*(volatile unsigned long*)(0xf000f038))
 612 #define MMAP7_PHYSICAL          (*(volatile unsigned long*)(0xf000f03c))
 613
 614 /** DMA engine **/
 615 #define DMA0_BASE_ADDR          0x6000b000
 616 #define DMA1_BASE_ADDR          0x6000b020
 617 #define DMA2_BASE_ADDR          0x6000b040
 618 #define DMA3_BASE_ADDR          0x6000b060
 619
 620 /* DMA request IDs */
 621 #define DMA_REQ_IIS             2
 622 #define DMA_REQ_SDHC            13
 623
 624 #define DMA_MASTER_CONTROL      (*(volatile unsigned long*)(0x6000a000))
 625 #define DMA_MASTER_STATUS       (*(volatile unsigned long*)(0x6000a004))
 626     /* 1ul << DMA_REQ_xxx to set bit */
 627 #define DMA_REQ_STATUS          (*(volatile unsigned long*)(0x6000a008))
 628
 629 #define DMA_MASTER_CONTROL_EN   (1 << 31)
 630
 631 #define DMA_MASTER_STATUS_CH0   (0x1 << 24)
 632 #define DMA_MASTER_STATUS_CH1   (0x1 << 25)
 633 #define DMA_MASTER_STATUS_CH2   (0x1 << 26)
 634 #define DMA_MASTER_STATUS_CH3   (0x1 << 27)
 635
 636 #define DMA0_CMD                (*(volatile unsigned long*)(DMA0_BASE_ADDR+0x00))
 637 #define DMA0_STATUS             (*(volatile unsigned long*)(DMA0_BASE_ADDR+0x04))
 638 #define DMA0_RAM_ADDR           (*(volatile unsigned long*)(DMA0_BASE_ADDR+0x10))
 639 #define DMA0_FLAGS              (*(volatile unsigned long*)(DMA0_BASE_ADDR+0x14))
 640 #define DMA0_PER_ADDR           (*(volatile unsigned long*)(DMA0_BASE_ADDR+0x18))
 641 #define DMA0_INCR               (*(volatile unsigned long*)(DMA0_BASE_ADDR+0x1c))
 642
 643 #define DMA1_CMD                (*(volatile unsigned long*)(DMA1_BASE_ADDR+0x00))
 644 #define DMA1_STATUS             (*(volatile unsigned long*)(DMA1_BASE_ADDR+0x04))
 645 #define DMA1_RAM_ADDR           (*(volatile unsigned long*)(DMA1_BASE_ADDR+0x10))
 646 #define DMA1_FLAGS              (*(volatile unsigned long*)(DMA1_BASE_ADDR+0x14))
 647 #define DMA1_PER_ADDR           (*(volatile unsigned long*)(DMA1_BASE_ADDR+0x18))
 648 #define DMA1_INCR               (*(volatile unsigned long*)(DMA1_BASE_ADDR+0x1c))
 649
 650 #define DMA2_CMD                (*(volatile unsigned long*)(DMA2_BASE_ADDR+0x00))
 651 #define DMA2_STATUS             (*(volatile unsigned long*)(DMA2_BASE_ADDR+0x04))
 652 #define DMA2_RAM_ADDR           (*(volatile unsigned long*)(DMA2_BASE_ADDR+0x10))
 653 #define DMA2_FLAGS              (*(volatile unsigned long*)(DMA2_BASE_ADDR+0x14))
 654 #define DMA2_PER_ADDR           (*(volatile unsigned long*)(DMA2_BASE_ADDR+0x18))
 655 #define DMA2_INCR               (*(volatile unsigned long*)(DMA2_BASE_ADDR+0x1c))
 656
 657 #define DMA3_CMD                (*(volatile unsigned long*)(DMA3_BASE_ADDR+0x00))
 658 #define DMA3_STATUS             (*(volatile unsigned long*)(DMA3_BASE_ADDR+0x04))
 659 #define DMA3_RAM_ADDR           (*(volatile unsigned long*)(DMA3_BASE_ADDR+0x10))
 660 #define DMA3_FLAGS              (*(volatile unsigned long*)(DMA3_BASE_ADDR+0x14))
 661 #define DMA3_PER_ADDR           (*(volatile unsigned long*)(DMA3_BASE_ADDR+0x18))
 662 #define DMA3_INCR               (*(volatile unsigned long*)(DMA3_BASE_ADDR+0x1c))
 663
 664 #define DMA_CMD_SIZE            (0xffff)
 665 #define DMA_CMD_REQ_ID          (0xf << 16)
 666     #define DMA_CMD_REQ_ID_POS  16
 667 #define DMA_CMD_WAIT_REQ        (0x1 << 24)
 668 #define DMA_CMD_UNK25           (0x1 << 25)
 669 #define DMA_CMD_SINGLE          (0x1 << 26) /* stop on complete, no auto reload */
 670 #define DMA_CMD_RAM_TO_PER      (0x1 << 27) /* otherwise per to ram */
 671 #define DMA_CMD_SLEEP_WAIT      (0x1 << 28)
 672 #define DMA_CMD_INTR            (0x1 << 30)
 673 #define DMA_CMD_START           (0x1 << 31)
 674
 675 #define DMA_STATUS_SIZE_REMAIN  (0xffff)
 676 #define DMA_STATUS_INTR         (0x1 << 30)
 677 #define DMA_STATUS_BUSY         (0x1 << 31)
 678
 679 #define DMA_FLAGS_ALIGNED       (0x1 << 24)
 680 #define DMA_FLAGS_UNK26         (0x1 << 26)
 681
 682 #define DMA_INCR_RANGE          (0x7 << 16)
 683 #define DMA_INCR_RANGE_UNL      (0x0 << 16)
 684 #define DMA_INCR_RANGE_FIXED    (0x1 << 16)
 685 #define DMA_INCR_RANGE_ALTR     (0x2 << 16)
 686 #define DMA_INCR_RANGE_4        (0x3 << 16)
 687 #define DMA_INCR_RANGE_8        (0x4 << 16)
 688 #define DMA_INCR_RANGE_16       (0x5 << 16)
 689 #define DMA_INCR_RANGE_32       (0x6 << 16)
 690 #define DMA_INCR_RANGE_64       (0x7 << 16)
 691
 692 #define DMA_INCR_WIDTH          (0x7 << 28)
 693 #define DMA_INCR_WIDTH_8BIT     (0x0 << 28)
 694 #define DMA_INCR_WIDTH_16BIT    (0x1 << 28)
 695 #define DMA_INCR_WIDTH_32BIT    (0x2 << 28)
 696 /* All other values reserved? */
 697
 698 /* Timer frequency */
 699 /* Portalplayer chips use a microsecond timer. */
 700 #define TIMER_FREQ 1000000
 701
 702 #endif /* __PP5020_H__ */