firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2008 by Maurus Cuelenaere
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "config.h"
  23 #include "jz4740.h"
  24 #include "nand.h"
  25 #include "nand_id.h"
  26 #include "system.h"
  27 #include "panic.h"
  28 #include "kernel.h"
  29 #include "storage.h"
  30 #include "string.h"
  31 /*#define LOGF_ENABLE*/
  32 #include "logf.h"
  33
  34 //#define USE_DMA
  35 //#define USE_ECC
  36
  37 /*
  38  * Standard NAND flash commands
  39  */
  40 #define NAND_CMD_READ0         0
  41 #define NAND_CMD_READ1         1
  42 #define NAND_CMD_RNDOUT        5
  43 #define NAND_CMD_PAGEPROG      0x10
  44 #define NAND_CMD_READOOB       0x50
  45 #define NAND_CMD_ERASE1        0x60
  46 #define NAND_CMD_STATUS        0x70
  47 #define NAND_CMD_STATUS_MULTI  0x71
  48 #define NAND_CMD_SEQIN         0x80
  49 #define NAND_CMD_RNDIN         0x85
  50 #define NAND_CMD_READID        0x90
  51 #define NAND_CMD_ERASE2        0xd0
  52 #define NAND_CMD_RESET         0xff
  53
  54 /* Extended commands for large page devices */
  55 #define NAND_CMD_READSTART     0x30
  56 #define NAND_CMD_RNDOUTSTART   0xE0
  57 #define NAND_CMD_CACHEDPROG    0x15
  58
  59 /* Status bits */
  60 #define NAND_STATUS_FAIL       0x01
  61 #define NAND_STATUS_FAIL_N1    0x02
  62 #define NAND_STATUS_TRUE_READY 0x20
  63 #define NAND_STATUS_READY      0x40
  64 #define NAND_STATUS_WP         0x80
  65
  66 /*
  67  * NAND parameter struct
  68  */
  69 struct nand_param
  70 {
  71     unsigned int bus_width;        /* data bus width: 8-bit/16-bit */
  72     unsigned int row_cycle;        /* row address cycles: 2/3 */
  73     unsigned int page_size;        /* page size in bytes: 512/2048/4096 */
  74     unsigned int oob_size;         /* oob size in bytes: 16/64/128 */
  75     unsigned int page_per_block;   /* pages per block: 32/64/128 */
  76 };
  77
  78 /*
  79  * jz4740_nand.c
  80  *
  81  * NAND read routine for JZ4740
  82  *
  83  * Copyright (c) 2005-2008 Ingenic Semiconductor Inc.
  84  *
  85  */
  86
  87 static volatile unsigned long nand_address;
  88 #define NAND_DATAPORT      (nand_address)
  89 #define NAND_ADDRPORT      (nand_address+0x10000)
  90 #define NAND_COMMPORT      (nand_address+0x08000)
  91
  92 #define ECC_BLOCK          512
  93 #define ECC_POS            6
  94 #define PAR_SIZE           9
  95
  96 #define __nand_cmd(n)      (REG8(NAND_COMMPORT) = (n))
  97 #define __nand_addr(n)     (REG8(NAND_ADDRPORT) = (n))
  98 #define __nand_data8()     (REG8(NAND_DATAPORT))
  99 #define __nand_data16()    (REG16(NAND_DATAPORT))
 100
 101 #define __nand_ecc_rs_encoding() \
 102     (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_ENCODING)
 103 #define __nand_ecc_rs_decoding() \
 104     (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_DECODING)
 105 #define __nand_ecc_disable()     (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
 106 #define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
 107 #define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
 108
 109 /*--------------------------------------------------------------*/
 110
 111 static struct nand_info* chip_info = NULL;
 112 static struct nand_info* banks[4];
 113 static unsigned int nr_banks = 1;
 114 static unsigned long bank_size;
 115 static struct nand_param internal_param;
 116 static struct mutex nand_mtx;
 117 #ifdef USE_DMA
 118 static struct mutex nand_dma_mtx;
 119 static struct semaphore nand_dma_complete;
 120 #endif
 121 static unsigned char temp_page[4096]; /* Max page size */
 122
 123 static inline void jz_nand_wait_ready(void)
 124 {
 125     register unsigned int timeout = 1000;
 126     while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--);
 127     while (!(REG_GPIO_PXPIN(2) & 0x40000000));
 128 }
 129
 130 #ifndef USE_DMA
 131 static inline void jz_nand_read_buf16(void *buf, int count)
 132 {
 133     register int i;
 134     register unsigned short *p = (unsigned short *)buf;
 135
 136     for (i = 0; i < count; i += 2)
 137         *p++ = __nand_data16();
 138 }
 139
 140 static inline void jz_nand_read_buf8(void *buf, int count)
 141 {
 142     register int i;
 143     register unsigned char *p = (unsigned char *)buf;
 144
 145     for (i = 0; i < count; i++)
 146         *p++ = __nand_data8();
 147 }
 148 #else
 149 static void jz_nand_write_dma(void *source, unsigned int len, int bw)
 150 {
 151     mutex_lock(&nand_dma_mtx);
 152
 153     if(((unsigned int)source < 0xa0000000) && len)
 154          dma_cache_wback_inv((unsigned long)source, len);
 155
 156     dma_enable();
 157
 158     REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES;
 159     REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)source);
 160     REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT);
 161     REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 16;
 162     REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO;
 163     REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_16BYTE |
 164                                        (bw == 8 ? DMAC_DCMD_DWDH_8 : DMAC_DCMD_DWDH_16));
 165
 166     REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */
 167 #if 1
 168     while( REG_DMAC_DTCR(DMA_NAND_CHANNEL) )
 169         yield();
 170 #else
 171     REG_DMAC_DCMD(DMA_NAND_CHANNEL) |= DMAC_DCMD_TIE;  /* Enable DMA interrupt */
 172     semaphore_wait(&nand_dma_complete, TIMEOUT_BLOCK);
 173 #endif
 174
 175     REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */
 176
 177     dma_disable();
 178
 179     mutex_unlock(&nand_dma_mtx);
 180 }
 181
 182 static void jz_nand_read_dma(void *target, unsigned int len, int bw)
 183 {
 184     mutex_lock(&nand_dma_mtx);
 185
 186     if(((unsigned int)target < 0xa0000000) && len)
 187         dma_cache_wback_inv((unsigned long)target, len);
 188
 189     dma_enable();
 190
 191     REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES ;
 192     REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT);
 193     REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)target);
 194     REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 4;
 195     REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO;
 196     REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT |
 197                                        (bw == 8 ? DMAC_DCMD_SWDH_8 : DMAC_DCMD_SWDH_16));
 198     REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */
 199 #if 1
 200     while( REG_DMAC_DTCR(DMA_NAND_CHANNEL) )
 201         yield();
 202 #else
 203     REG_DMAC_DCMD(DMA_NAND_CHANNEL) |= DMAC_DCMD_TIE;  /* Enable DMA interrupt */
 204     semaphore_wait(&nand_dma_complete, TIMEOUT_BLOCK);
 205 #endif
 206
 207     //REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */
 208
 209     dma_disable();
 210
 211     mutex_unlock(&nand_dma_mtx);
 212 }
 213
 214 void DMA_CALLBACK(DMA_NAND_CHANNEL)(void)
 215 {
 216     if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_HLT)
 217         REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_HLT;
 218
 219     if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_AR)
 220         REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_AR;
 221
 222     if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_CT)
 223         REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_CT;
 224
 225     if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_TT)
 226         REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_TT;
 227
 228     semaphore_release(&nand_dma_complete);
 229 }
 230 #endif /* USE_DMA */
 231
 232 static inline void jz_nand_read_buf(void *buf, int count, int bw)
 233 {
 234 #ifdef USE_DMA
 235     if (bw == 8)
 236         jz_nand_read_dma(buf, count, 8);
 237     else
 238         jz_nand_read_dma(buf, count, 16);
 239 #else
 240     if (bw == 8)
 241         jz_nand_read_buf8(buf, count);
 242     else
 243         jz_nand_read_buf16(buf, count);
 244 #endif
 245 }
 246
 247 #ifdef USE_ECC
 248 /*
 249  * Correct 1~9-bit errors in 512-bytes data
 250  */
 251 static void jz_rs_correct(unsigned char *dat, int idx, int mask)
 252 {
 253     int i, j;
 254     unsigned short d, d1, dm;
 255
 256     i = (idx * 9) >> 3;
 257     j = (idx * 9) & 0x7;
 258
 259     i = (j == 0) ? (i - 1) : i;
 260     j = (j == 0) ? 7 : (j - 1);
 261
 262     if (i > 512)
 263         return;
 264
 265     if (i == 512)
 266         d = dat[i - 1];
 267     else
 268         d = (dat[i] << 8) | dat[i - 1];
 269
 270     d1 = (d >> j) & 0x1ff;
 271     d1 ^= mask;
 272
 273     dm = ~(0x1ff << j);
 274     d = (d & dm) | (d1 << j);
 275
 276     dat[i - 1] = d & 0xff;
 277     if (i < 512)
 278         dat[i] = (d >> 8) & 0xff;
 279 }
 280 #endif
 281
 282 /*
 283  * Read oob
 284  */
 285 static int jz_nand_read_oob(unsigned long page_addr, unsigned char *buf, int size)
 286 {
 287     struct nand_param *nandp = &internal_param;
 288     int page_size, row_cycle, bus_width;
 289     int col_addr;
 290
 291     page_size = nandp->page_size;
 292     row_cycle = nandp->row_cycle;
 293     bus_width = nandp->bus_width;
 294
 295     if (page_size >= 2048)
 296         col_addr = page_size;
 297     else
 298         col_addr = 0;
 299
 300     if (page_size >= 2048)
 301         /* Send READ0 command */
 302         __nand_cmd(NAND_CMD_READ0);
 303     else
 304         /* Send READOOB command */
 305         __nand_cmd(NAND_CMD_READOOB);
 306
 307     /* Send column address */
 308     __nand_addr(col_addr & 0xff);
 309     if (page_size >= 2048)
 310         __nand_addr((col_addr >> 8) & 0xff);
 311
 312     /* Send page address */
 313     __nand_addr(page_addr & 0xff);
 314     __nand_addr((page_addr >> 8) & 0xff);
 315     if (row_cycle == 3)
 316         __nand_addr((page_addr >> 16) & 0xff);
 317
 318     /* Send READSTART command for 2048 ps NAND */
 319     if (page_size >= 2048)
 320         __nand_cmd(NAND_CMD_READSTART);
 321
 322     /* Wait for device ready */
 323     jz_nand_wait_ready();
 324
 325     /* Read oob data */
 326     jz_nand_read_buf(buf, size, bus_width);
 327
 328     return 0;
 329 }
 330
 331
 332 /*
 333  * nand_read_page()
 334  *
 335  * Input:
 336  *
 337  *    block - block number: 0, 1, 2, ...
 338  *    page - page number within a block: 0, 1, 2, ...
 339  *    dst - pointer to target buffer
 340  */
 341 static int jz_nand_read_page(unsigned long page_addr, unsigned char *dst)
 342 {
 343     struct nand_param *nandp = &internal_param;
 344     int page_size, oob_size, page_per_block;
 345     int row_cycle, bus_width, ecc_count;
 346     int i;
 347 #ifdef USE_ECC
 348     int j;
 349 #endif
 350     unsigned char *data_buf;
 351     unsigned char oob_buf[nandp->oob_size];
 352
 353     if(nand_address == 0)
 354         return -1;
 355
 356     page_size = nandp->page_size;
 357     oob_size = nandp->oob_size;
 358     page_per_block = nandp->page_per_block;
 359     row_cycle = nandp->row_cycle;
 360     bus_width = nandp->bus_width;
 361
 362     /*
 363      * Read oob data
 364      */
 365     jz_nand_read_oob(page_addr, oob_buf, oob_size);
 366
 367     /*
 368      * Read page data
 369      */
 370
 371     /* Send READ0 command */
 372     __nand_cmd(NAND_CMD_READ0);
 373
 374     /* Send column address */
 375     __nand_addr(0);
 376     if (page_size >= 2048)
 377         __nand_addr(0);
 378
 379     /* Send page address */
 380     __nand_addr(page_addr & 0xff);
 381     __nand_addr((page_addr >> 8) & 0xff);
 382     if (row_cycle >= 3)
 383         __nand_addr((page_addr >> 16) & 0xff);
 384
 385     /* Send READSTART command for 2048 ps NAND */
 386     if (page_size >= 2048)
 387         __nand_cmd(NAND_CMD_READSTART);
 388
 389     /* Wait for device ready */
 390     jz_nand_wait_ready();
 391
 392     /* Read page data */
 393     data_buf = dst;
 394
 395     ecc_count = page_size / ECC_BLOCK;
 396
 397     for (i = 0; i < ecc_count; i++)
 398     {
 399 #ifdef USE_ECC
 400         volatile unsigned char *paraddr = (volatile unsigned char *)EMC_NFPAR0;
 401         unsigned int stat;
 402
 403         /* Enable RS decoding */
 404         REG_EMC_NFINTS = 0x0;
 405         __nand_ecc_rs_decoding();
 406 #endif
 407
 408         /* Read data */
 409         jz_nand_read_buf((void *)data_buf, ECC_BLOCK, bus_width);
 410
 411 #ifdef USE_ECC
 412         /* Set PAR values */
 413         for (j = 0; j < PAR_SIZE; j++)
 414             *paraddr++ = oob_buf[ECC_POS + i*PAR_SIZE + j];
 415
 416         /* Set PRDY */
 417         REG_EMC_NFECR |= EMC_NFECR_PRDY;
 418
 419         /* Wait for completion */
 420         __nand_ecc_decode_sync();
 421
 422         /* Disable decoding */
 423         __nand_ecc_disable();
 424
 425         /* Check result of decoding */
 426         stat = REG_EMC_NFINTS;
 427         if (stat & EMC_NFINTS_ERR)
 428         {
 429             /* Error occurred */
 430             if (stat & EMC_NFINTS_UNCOR)
 431             {
 432                 /* Uncorrectable error occurred */
 433                 logf("Uncorrectable ECC error at NAND page address 0x%lx", page_addr);
 434                 return -1;
 435             }
 436             else
 437             {
 438                 unsigned int errcnt, index, mask;
 439
 440                 errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
 441                 switch (errcnt)
 442                 {
 443                 case 4:
 444                     index = (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
 445                     mask = (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
 446                     jz_rs_correct(data_buf, index, mask);
 447                 case 3:
 448                     index = (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
 449                     mask = (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
 450                     jz_rs_correct(data_buf, index, mask);
 451                 case 2:
 452                     index = (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
 453                     mask = (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
 454                     jz_rs_correct(data_buf, index, mask);
 455                 case 1:
 456                     index = (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
 457                     mask = (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
 458                     jz_rs_correct(data_buf, index, mask);
 459                     break;
 460                 default:
 461                     break;
 462                 }
 463             }
 464         }
 465 #endif
 466
 467         data_buf += ECC_BLOCK;
 468     }
 469
 470     return 0;
 471 }
 472
 473 /*
 474  * Disable NAND controller
 475  */
 476 static void jz_nand_disable(void)
 477 {
 478     REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1 | EMC_NFCSR_NFCE2 |
 479                        EMC_NFCSR_NFCE3 | EMC_NFCSR_NFCE4 |
 480                        EMC_NFCSR_NFE1 | EMC_NFCSR_NFE2   |
 481                        EMC_NFCSR_NFE3 | EMC_NFCSR_NFE4   );
 482 }
 483
 484 /*
 485  * Enable NAND controller
 486  */
 487 static void jz_nand_enable(void)
 488 {
 489 #if 0
 490     /* OF RE */
 491     REG_GPIO_PXFUNS(1) = 0x1E018000; // __gpio_as_func0() start
 492     REG_GPIO_PXSELC(1) = 0x1E018000; // __gpio_as_func0() end
 493
 494     REG_GPIO_PXFUNS(2) = 0x3000<<16; // __gpio_as_func0() start
 495     REG_GPIO_PXSELC(2) = 0x3000<<16; // __gpio_as_func0() end
 496
 497     REG_GPIO_PXFUNC(2) = 0x4000<<16; // __gpio_port_as_input() start
 498     REG_GPIO_PXSELC(2) = 0x4000<<16;
 499     REG_GPIO_PXDIRC(2) = 0x4000<<16; // __gpio_port_as_input() end
 500     REG_GPIO_PXPES(2) = 0x4000<<16; // __gpio_disable_pull()
 501
 502     REG_GPIO_PXFUNS(1) = 0x40<<16; // __gpio_as_func0() start
 503     REG_GPIO_PXSELC(1) = 0x40<<16; // __gpio_as_func0() end
 504
 505     REG_EMC_SMCR1 = (REG_EMC_SMCR1 & 0xFF) | 0x4621200;
 506     REG_EMC_SMCR2 = (REG_EMC_SMCR2 & 0xFF) | 0x4621200;
 507     REG_EMC_SMCR3 = (REG_EMC_SMCR3 & 0xFF) | 0x4621200;
 508     REG_EMC_SMCR4 = (REG_EMC_SMCR4 & 0xFF) | 0x4621200;
 509
 510     REG_EMC_SMCR1 = REG_EMC_SMCR2 = REG_EMC_SMCR3 = REG_EMC_SMCR4 = 0x6621200;
 511 #else
 512     REG_EMC_SMCR1 = REG_EMC_SMCR2 = REG_EMC_SMCR3 = REG_EMC_SMCR4 = 0x04444400;
 513 #endif
 514 }
 515
 516 static void jz_nand_select(int bank)
 517 {
 518     REG_EMC_NFCSR |= (EMC_NFCSR_NFE(bank+1) | EMC_NFCSR_NFCE(bank+1));
 519
 520     switch(bank)
 521     {
 522         case 0:
 523             nand_address = 0xB8000000;
 524             break;
 525         case 1:
 526             nand_address = 0xB4000000;
 527             break;
 528         case 2:
 529             nand_address = 0xAC000000;
 530             break;
 531         case 3:
 532             nand_address = 0xA8000000;
 533             break;
 534     }
 535 }
 536
 537 static void jz_nand_deselect(int bank)
 538 {
 539     REG_EMC_NFCSR &= ~(EMC_NFCSR_NFE(bank+1) | EMC_NFCSR_NFCE(bank+1));
 540     nand_address = 0;
 541 }
 542
 543 static int jz_nand_init(void)
 544 {
 545     unsigned char cData[5];
 546     int i;
 547
 548     jz_nand_enable();
 549
 550     for(i=0; i<4; i++)
 551     {
 552         jz_nand_select(i);
 553
 554         __nand_cmd(NAND_CMD_READID);
 555         __nand_addr(NAND_CMD_READ0);
 556         cData[0] = __nand_data8();
 557         cData[1] = __nand_data8();
 558         cData[2] = __nand_data8();
 559         cData[3] = __nand_data8();
 560         cData[4] = __nand_data8();
 561
 562         jz_nand_deselect(i);
 563
 564         logf("NAND chip %d: 0x%x 0x%x 0x%x 0x%x 0x%x", i+1, cData[0], cData[1],
 565                                                   cData[2], cData[3], cData[4]);
 566
 567         banks[i] = nand_identify(cData);
 568
 569         if(banks[i] != NULL)
 570             nr_banks++;
 571
 572         if(i == 0 && banks[i] == NULL)
 573         {
 574             panicf("Unknown NAND flash chip: 0x%x 0x%x 0x%x 0x%x 0x%x", cData[0],
 575                                           cData[1], cData[2], cData[3], cData[4]);
 576             return -1; /* panicf() doesn't return though */
 577         }
 578     }
 579     chip_info = banks[0];
 580
 581     internal_param.bus_width = 8;
 582     internal_param.row_cycle = chip_info->row_cycles;
 583     internal_param.page_size = chip_info->page_size;
 584     internal_param.oob_size = chip_info->spare_size;
 585     internal_param.page_per_block = chip_info->pages_per_block;
 586
 587     bank_size = chip_info->page_size * chip_info->blocks_per_bank / 512 * chip_info->pages_per_block;
 588
 589     jz_nand_disable();
 590
 591     return 0;
 592 }
 593
 594 int nand_init(void)
 595 {
 596     int res = 0;
 597     static bool inited = false;
 598
 599     if(!inited)
 600     {
 601         res = jz_nand_init();
 602         mutex_init(&nand_mtx);
 603 #ifdef USE_DMA
 604         mutex_init(&nand_dma_mtx);
 605         semaphore_init(&nand_dma_complete, 1, 0);
 606         system_enable_irq(DMA_IRQ(DMA_NAND_CHANNEL));
 607 #endif
 608
 609         inited = true;
 610     }
 611
 612     return res;
 613 }
 614
 615 static inline int read_sector(unsigned long start, unsigned int count,
 616                                void* buf, unsigned int chip_size)
 617 {
 618     register int ret;
 619
 620     if(UNLIKELY(start % chip_size == 0 && count == chip_size))
 621         ret = jz_nand_read_page(start / chip_size, buf);
 622     else
 623     {
 624         ret = jz_nand_read_page(start / chip_size, temp_page);
 625         memcpy(buf, temp_page + (start % chip_size), count);
 626     }
 627
 628     return ret;
 629 }
 630
 631 int nand_read_sectors(IF_MV2(int drive,) unsigned long start, int count, void* buf)
 632 {
 633 #ifdef HAVE_MULTIVOLUME
 634     (void)drive;
 635 #endif
 636     int ret = 0;
 637     unsigned int i, _count, chip_size = chip_info->page_size;
 638     unsigned long _start;
 639
 640     logf("start");
 641     mutex_lock(&nand_mtx);
 642
 643     _start = start << 9;
 644     _count = count << 9;
 645
 646     if(_count <= chip_size)
 647     {
 648         jz_nand_select(start / bank_size);
 649         ret = read_sector(_start, _count, buf, chip_size);
 650         jz_nand_deselect(start / bank_size);
 651     }
 652     else
 653     {
 654         for(i=0; i<_count && ret==0; i+=chip_size)
 655         {
 656             jz_nand_select((start+(i>>9)) / bank_size);
 657
 658             ret = read_sector(_start+i, (_count-i < chip_size ?
 659                                          _count-i : chip_size),
 660                                buf+i, chip_size);
 661
 662             jz_nand_deselect((start+(i>>9)) / bank_size);
 663         }
 664     }
 665
 666     mutex_unlock(&nand_mtx);
 667
 668     logf("nand_read_sectors(%ld, %d, 0x%x): %d", start, count, (int)buf, ret);
 669
 670     return ret;
 671 }
 672
 673 /* TODO */
 674 int nand_write_sectors(IF_MV2(int drive,) unsigned long start, int count, const void* buf)
 675 {
 676     (void)start;
 677     (void)count;
 678     (void)buf;
 679 #ifdef HAVE_MULTIVOLUME
 680     (void)drive;
 681 #endif
 682
 683     return -1;
 684 }
 685
 686 #ifdef HAVE_STORAGE_FLUSH
 687 int nand_flush(void)
 688 {
 689     return 0;
 690 }
 691 #endif
 692
 693 void nand_spindown(int seconds)
 694 {
 695     /* null */
 696     (void)seconds;
 697 }
 698
 699 void nand_sleep(void)
 700 {
 701     /* null */
 702 }
 703
 704 void nand_spin(void)
 705 {
 706     /* null */
 707 }
 708
 709 void nand_enable(bool on)
 710 {
 711     /* null - flash controller is enabled/disabled as needed. */
 712     (void)on;
 713 }
 714
 715 /* TODO */
 716 long nand_last_disk_activity(void)
 717 {
 718     return 0;
 719 }
 720
 721 int nand_spinup_time(void)
 722 {
 723     return 0;
 724 }
 725
 726 void nand_sleepnow(void)
 727 {
 728 }
 729
 730 #ifdef STORAGE_GET_INFO
 731 void nand_get_info(IF_MV2(int drive,) struct storage_info *info)
 732 {
 733 #ifdef HAVE_MULTIVOLUME
 734     (void)drive;
 735 #endif
 736
 737     /* firmware version */
 738     info->revision="0.00";
 739
 740     info->vendor="Rockbox";
 741     info->product="NAND Storage";
 742
 743     /* blocks count */
 744     info->num_sectors = bank_size * nr_banks;
 745     info->sector_size = 512;
 746 }
 747 #endif
 748
 749 #ifdef CONFIG_STORAGE_MULTI
 750 int nand_num_drives(int first_drive)
 751 {
 752     /* We don't care which logical drive number(s) we have been assigned */
 753     (void)first_drive;
 754
 755     return 1;
 756 }
 757 #endif