fuze+: scramble bootloader file
[maemo-rb.git] / firmware / export / ak4537.h
blob1f272d41fc238d3d16373351cde18b5bfd5b69f1
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
10 * Copyright (C) 2009 by Mark Arigo
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
22 #ifndef _AK4537_H
23 #define _AK4537_H
25 /* Volume goes from -127.0 ... 0 dB in 0.5 dB increments */
26 #define VOLUME_MIN -1270
27 #define VOLUME_MAX 0
29 extern int tenthdb2master(int db);
31 extern void audiohw_set_master_vol(int vol_l, int vol_r);
33 #define AKC_NUM_REGS 0x11
35 /* Common register bits */
37 /* Power Management 1 */
38 #define AK4537_PM1 0x00
39 #define PMADL (1 << 0)
40 #define PMMICL (1 << 1)
41 #define PMIPGL (1 << 2)
42 #define PMMO (1 << 3)
43 #define PMLO (1 << 4)
44 #define PMBPM (1 << 5)
45 #define PMBPS (1 << 6)
46 #define PMVCM (1 << 7)
48 /* Power Management 2 */
49 #define AK4537_PM2 0x01
50 #define PMDAC (1 << 0)
51 #define PMHPR (1 << 1)
52 #define PMHPL (1 << 2)
53 #define PMSPK (1 << 3)
54 #define SPKG (1 << 4)
55 #define PMPLL (1 << 5)
56 #define PMXTL (1 << 6)
57 #define MCLKPD (1 << 7)
59 /* Signal Select 1 */
60 #define AK4537_SIGSEL1 0x02
61 #define MOUT2 (1 << 0)
62 #define ALCS (1 << 1)
63 #define BPMSP (1 << 2)
64 #define BPSSP (1 << 3)
65 #define MICM (1 << 4)
66 #define DAMO (1 << 5)
67 #define PSMO (1 << 6)
68 #define MOGN (1 << 7)
70 /* Signal Select 2 */
71 #define AK4537_SIGSEL2 0x03
72 #define HPR (1 << 0)
73 #define HPL (1 << 1)
74 #define BPMHP (1 << 2)
75 #define BPSHP (1 << 3)
76 #define MICL (1 << 4)
77 #define PSLO (1 << 6)
78 #define DAHS (1 << 7)
80 /* Mode Control 1 */
81 #define AK4537_MODE1 0x04
82 #define DIF_MASK (3 << 0)
83 #define BICK_MASK (1 << 2)
84 #define MCKO_EN (1 << 3)
85 #define MCKO_MASK (3 << 4)
86 #define MCKI_MASK (3 << 6)
88 /* Mode Control 2 */
89 #define AK4537_MODE2 0x05
90 #define SPPS (1 << 0)
91 #define LOOP (1 << 1)
92 #define HPM (1 << 2)
93 #define FS_MASK (7 << 5)
95 /* DAC Control */
96 #define AK4537_DAC 0x06
97 #define DEM_MASK (3 << 0)
98 #define BST_MASK (3 << 2)
99 #define DATTC (1 << 4)
100 #define SMUTE (1 << 5)
101 #define TM_MASK (3 << 6)
103 /* MIC Control */
104 #define AK4537_MIC 0x07
105 #define MGAIN (1 << 0)
106 #define MSEL (1 << 1)
107 #define MICAD (1 << 2)
108 #define MPWRI (1 << 3)
109 #define MPWRE (1 << 4)
110 #define IPGAC (1 << 5)
112 /* Timer Select */
113 #define AK4537_TIMER 0x08
114 #define LTM_MASK (3 << 0)
115 #define WTM_MASK (3 << 2)
116 #define ZTM_MASK (3 << 4)
117 #define ZTM1 (1 << 5)
118 #define ROTM (1 << 6)
120 /* ALC Mode Control 1 */
121 #define AK4537_ALC1 0x09
122 #define LMTH (1 << 0)
123 #define RATT (1 << 1)
124 #define LMAT_MASK (3 << 2)
125 #define ZELM (1 << 4)
126 #define ALC1 (1 << 5)
127 #define ALC2 (1 << 6)
129 /* ALC Mode Control 2 */
130 #define AK4537_ALC2 0x0a
132 /* Lch Input PGA Control */
133 #define AK4537_IPGAL 0x0b
135 /* Lch Digital ATT Control */
136 #define AK4537_ATTL 0x0c
138 /* Rch Digital ATT Control */
139 #define AK4537_ATTR 0x0d
141 /* Volume Control */
142 #define AK4537_VOLUME 0x0e
143 #define ATTS_MASK (7 << 4)
144 #define ATTRM (1 << 7)
146 /* Rch Input PGA Control */
147 #define AK4537_IPGAR 0x0f
149 /* Power Management 3 */
150 #define AK4537_PM3 0x10
151 #define PMADR (1 << 0)
152 #define PMMICR (1 << 1)
153 #define PMIPGR (1 << 2)
154 #define INR (1 << 3)
155 #define INL (1 << 4)
157 /* Sampling frequency (PLL mode) */
158 #define AKC_PLL_8000HZ (7 << 5)
159 #define AKC_PLL_11025HZ (2 << 5)
160 #define AKC_PLL_16000HZ (6 << 5)
161 #define AKC_PLL_22050HZ (1 << 5)
162 #define AKC_PLL_24000HZ (5 << 5)
163 #define AKC_PLL_32000HZ (4 << 5)
164 #define AKC_PLL_44100HZ (0 << 5)
165 #define AKC_PLL_48000HZ (3 << 5)
167 /* MCKI input frequency (PLL mode) */
168 #define MCKI_PLL_12288KHZ (0 << 6)
169 #define MCKI_PLL_11289KHZ (1 << 6)
170 #define MCKI_PLL_12000KHZ (2 << 6)
172 /* MCKO frequency (PLL mode, MCKO bit = 1) */
173 #define MCKO_PLL_256FS (0 << 4)
174 #define MCKO_PLL_128FS (1 << 4)
175 #define MCKO_PLL_64FS (2 << 4)
176 #define MCKO_PLL_32FS (3 << 4)
178 /* BICK frequency */
179 #define BICK_64FS (0 << 2)
180 #define BICK_32FS (1 << 2)
182 /* Audio interface format */
183 #define DIF_MSB_LSB (0 << 0)
184 #define DIF_MSB_MSB (1 << 0)
185 #define DIF_I2S (2 << 0)
187 /* Low frequency boost control */
188 #define BST_OFF (0 << 2)
189 #define BST_MIN (1 << 2)
190 #define BST_MID (2 << 2)
191 #define BST_MAX (3 << 2)
193 #endif /* _AK4537_H */