source/libs/gmp/gmp-src/mpn/arm/v7a/cora15/neon/aorsorrlshC_n.asm

   1 dnl  ARM mpn_addlshC_n, mpn_sublshC_n, mpn_rsblshC_n
   2
   3 dnl  Contributed to the GNU project by Torbjörn Granlund.
   4
   5 dnl  Copyright 2013 Free Software Foundation, Inc.
   6
   7 dnl  This file is part of the GNU MP Library.
   8 dnl
   9 dnl  The GNU MP Library is free software; you can redistribute it and/or modify
  10 dnl  it under the terms of either:
  11 dnl
  12 dnl    * the GNU Lesser General Public License as published by the Free
  13 dnl      Software Foundation; either version 3 of the License, or (at your
  14 dnl      option) any later version.
  15 dnl
  16 dnl  or
  17 dnl
  18 dnl    * the GNU General Public License as published by the Free Software
  19 dnl      Foundation; either version 2 of the License, or (at your option) any
  20 dnl      later version.
  21 dnl
  22 dnl  or both in parallel, as here.
  23 dnl
  24 dnl  The GNU MP Library is distributed in the hope that it will be useful, but
  25 dnl  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  26 dnl  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  27 dnl  for more details.
  28 dnl
  29 dnl  You should have received copies of the GNU General Public License and the
  30 dnl  GNU Lesser General Public License along with the GNU MP Library.  If not,
  31 dnl  see https://www.gnu.org/licenses/.
  32
  33
  34 C            cycles/limb
  35 C StrongARM      -
  36 C XScale         -
  37 C Cortex-A7      ?
  38 C Cortex-A8      ?
  39 C Cortex-A9      5.25
  40 C Cortex-A15     2.25
  41
  42 C TODO
  43 C  * Consider using 4-way feed-in code.
  44 C  * This is ad-hoc scheduled, perhaps unnecessarily so for A15, and perhaps
  45 C    insufficiently for A7 and A8.
  46
  47 define(`rp', `r0')
  48 define(`up', `r1')
  49 define(`vp', `r2')
  50 define(`n',  `r3')
  51
  52 ifdef(`DO_add', `
  53   define(`ADCSBCS',     `adcs   $1, $2, $3')
  54   define(`CLRCY',       `cmn    r13, #1')
  55   define(`RETVAL',      `adc    r0, $1, #0')
  56   define(`func',        mpn_addlsh`'LSH`'_n)')
  57 ifdef(`DO_sub', `
  58   define(`ADCSBCS',     `sbcs   $1, $2, $3')
  59   define(`CLRCY',       `cmp    r13, #0')
  60   define(`RETVAL',      `sbc    $2, $2, $2
  61                         cmn     $2, #1
  62                         adc      r0, $1, #0')
  63   define(`func',        mpn_sublsh`'LSH`'_n)')
  64 ifdef(`DO_rsb', `
  65   define(`ADCSBCS',     `sbcs   $1, $3, $2')
  66   define(`CLRCY',       `cmp    r13, #0')
  67   define(`RETVAL',      `sbc    r0, $1, #0')
  68   define(`func',        mpn_rsblsh`'LSH`'_n)')
  69
  70
  71 ASM_START()
  72 PROLOGUE(func)
  73         push     {r4-r10}
  74         vmov.i8  d0, #0                 C could feed carry through here
  75         CLRCY
  76         tst     n, #1
  77         beq     L(bb0)
  78
  79 L(bb1): vld1.32  {d3[0]}, [vp]!
  80         vsli.u32 d0, d3, #LSH
  81         ldr      r12, [up], #4
  82         vmov.32  r5, d0[0]
  83         vshr.u32 d0, d3, #32-LSH
  84         ADCSBCS( r12, r12, r5)
  85         str      r12, [rp], #4
  86         bics     n, n, #1
  87         beq      L(rtn)
  88
  89 L(bb0): tst     n, #2
  90         beq     L(b00)
  91
  92 L(b10): vld1.32  {d3}, [vp]!
  93         vsli.u64 d0, d3, #LSH
  94         ldmia    up!, {r10,r12}
  95         vmov     r4, r5, d0
  96         vshr.u64 d0, d3, #64-LSH
  97         ADCSBCS( r10, r10, r4)
  98         ADCSBCS( r12, r12, r5)
  99         stmia    rp!, {r10,r12}
 100         bics     n, n, #2
 101         beq      L(rtn)
 102
 103 L(b00): vld1.32  {d2}, [vp]!
 104         vsli.u64 d0, d2, #LSH
 105         vshr.u64 d1, d2, #64-LSH
 106         vld1.32  {d3}, [vp]!
 107         vsli.u64 d1, d3, #LSH
 108         vmov     r6, r7, d0
 109         vshr.u64 d0, d3, #64-LSH
 110         sub      n, n, #4
 111         tst      n, n
 112         beq      L(end)
 113
 114         ALIGN(16)
 115 L(top): ldmia    up!, {r8,r9,r10,r12}
 116         vld1.32  {d2}, [vp]!
 117         vsli.u64 d0, d2, #LSH
 118         vmov     r4, r5, d1
 119         vshr.u64 d1, d2, #64-LSH
 120         ADCSBCS( r8, r8, r6)
 121         ADCSBCS( r9, r9, r7)
 122         vld1.32  {d3}, [vp]!
 123         vsli.u64 d1, d3, #LSH
 124         vmov     r6, r7, d0
 125         vshr.u64 d0, d3, #64-LSH
 126         ADCSBCS( r10, r10, r4)
 127         ADCSBCS( r12, r12, r5)
 128         stmia    rp!, {r8,r9,r10,r12}
 129         sub      n, n, #4
 130         tst      n, n
 131         bne      L(top)
 132
 133 L(end): ldmia    up!, {r8,r9,r10,r12}
 134         vmov     r4, r5, d1
 135         ADCSBCS( r8, r8, r6)
 136         ADCSBCS( r9, r9, r7)
 137         ADCSBCS( r10, r10, r4)
 138         ADCSBCS( r12, r12, r5)
 139         stmia    rp!, {r8,r9,r10,r12}
 140 L(rtn): vmov.32  r0, d0[0]
 141         RETVAL(  r0, r1)
 142         pop      {r4-r10}
 143         bx       r14
 144 EPILOGUE()