2 ** IR assembler (SSA IR -> machine code).
3 ** Copyright (C) 2005-2012 Mike Pall. See Copyright Notice in luajit.h
22 #include "lj_ircall.h"
29 #include "lj_dispatch.h"
31 #include "lj_target.h"
33 /* -- Assembler state and common macros ----------------------------------- */
35 /* Assembler state. */
36 typedef struct ASMState
{
37 RegCost cost
[RID_MAX
]; /* Reference and blended allocation cost for regs. */
39 MCode
*mcp
; /* Current MCode pointer (grows down). */
40 MCode
*mclim
; /* Lower limit for MCode memory + red zone. */
42 IRIns
*ir
; /* Copy of pointer to IR instructions/constants. */
43 jit_State
*J
; /* JIT compiler state. */
45 #if LJ_TARGET_X86ORX64
46 x86ModRM mrm
; /* Fused x86 address operand. */
49 RegSet freeset
; /* Set of free registers. */
50 RegSet modset
; /* Set of registers modified inside the loop. */
51 RegSet weakset
; /* Set of weakly referenced registers. */
52 RegSet phiset
; /* Set of PHI registers. */
54 uint32_t flags
; /* Copy of JIT compiler flags. */
55 int loopinv
; /* Loop branch inversion (0:no, 1:yes, 2:yes+CC_P). */
57 int32_t evenspill
; /* Next even spill slot. */
58 int32_t oddspill
; /* Next odd spill slot (or 0). */
60 IRRef curins
; /* Reference of current instruction. */
61 IRRef stopins
; /* Stop assembly before hitting this instruction. */
62 IRRef orignins
; /* Original T->nins. */
64 IRRef snapref
; /* Current snapshot is active after this reference. */
65 IRRef snaprename
; /* Rename highwater mark for snapshot check. */
66 SnapNo snapno
; /* Current snapshot number. */
67 SnapNo loopsnapno
; /* Loop snapshot number. */
69 IRRef fuseref
; /* Fusion limit (loopref, 0 or FUSE_DISABLED). */
70 IRRef sectref
; /* Section base reference (loopref or 0). */
71 IRRef loopref
; /* Reference of LOOP instruction (or 0). */
73 BCReg topslot
; /* Number of slots for stack check (unless 0). */
74 int32_t gcsteps
; /* Accumulated number of GC steps (per section). */
76 GCtrace
*T
; /* Trace to assemble. */
77 GCtrace
*parent
; /* Parent trace (or NULL). */
79 MCode
*mcbot
; /* Bottom of reserved MCode. */
80 MCode
*mctop
; /* Top of generated MCode. */
81 MCode
*mcloop
; /* Pointer to loop MCode (or NULL). */
82 MCode
*invmcp
; /* Points to invertible loop branch (or NULL). */
83 MCode
*flagmcp
; /* Pending opportunity to merge flag setting ins. */
84 MCode
*realign
; /* Realign loop if not NULL. */
87 int32_t krefk
[RID_NUM_KREF
];
89 IRRef1 phireg
[RID_MAX
]; /* PHI register references. */
90 uint16_t parentmap
[LJ_MAX_JSLOTS
]; /* Parent instruction to RegSP map. */
93 #define IR(ref) (&as->ir[(ref)])
95 #define ASMREF_TMP1 REF_TRUE /* Temp. register. */
96 #define ASMREF_TMP2 REF_FALSE /* Temp. register. */
97 #define ASMREF_L REF_NIL /* Stores register for L. */
99 /* Check for variant to invariant references. */
100 #define iscrossref(as, ref) ((ref) < as->sectref)
102 /* Inhibit memory op fusion from variant to invariant references. */
103 #define FUSE_DISABLED (~(IRRef)0)
104 #define mayfuse(as, ref) ((ref) > as->fuseref)
105 #define neverfuse(as) (as->fuseref == FUSE_DISABLED)
106 #define canfuse(as, ir) (!neverfuse(as) && !irt_isphi((ir)->t))
107 #define opisfusableload(o) \
108 ((o) == IR_ALOAD || (o) == IR_HLOAD || (o) == IR_ULOAD || \
109 (o) == IR_FLOAD || (o) == IR_XLOAD || (o) == IR_SLOAD || (o) == IR_VLOAD)
111 /* Sparse limit checks using a red zone before the actual limit. */
112 #define MCLIM_REDZONE 64
113 #define checkmclim(as) \
114 if (LJ_UNLIKELY(as->mcp < as->mclim)) asm_mclimit(as)
116 static LJ_NORET LJ_NOINLINE
void asm_mclimit(ASMState
*as
)
118 lj_mcode_limiterr(as
->J
, (size_t)(as
->mctop
- as
->mcp
+ 4*MCLIM_REDZONE
));
122 #define ra_iskref(ref) ((ref) < RID_NUM_KREF)
123 #define ra_krefreg(ref) ((Reg)(RID_MIN_KREF + (Reg)(ref)))
124 #define ra_krefk(as, ref) (as->krefk[(ref)])
126 static LJ_AINLINE
void ra_setkref(ASMState
*as
, Reg r
, int32_t k
)
128 IRRef ref
= (IRRef
)(r
- RID_MIN_KREF
);
130 as
->cost
[r
] = REGCOST(ref
, ref
);
134 #define ra_iskref(ref) 0
135 #define ra_krefreg(ref) RID_MIN_GPR
136 #define ra_krefk(as, ref) 0
139 /* Arch-specific field offsets. */
140 static const uint8_t field_ofs
[IRFL__MAX
+1] = {
141 #define FLOFS(name, ofs) (uint8_t)(ofs),
147 /* -- Target-specific instruction emitter --------------------------------- */
149 #if LJ_TARGET_X86ORX64
150 #include "lj_emit_x86.h"
152 #include "lj_emit_arm.h"
154 #include "lj_emit_ppc.h"
156 #include "lj_emit_mips.h"
158 #error "Missing instruction emitter for target CPU"
161 /* -- Register allocator debugging ---------------------------------------- */
163 /* #define LUAJIT_DEBUG_RA */
165 #ifdef LUAJIT_DEBUG_RA
170 #define RIDNAME(name) #name,
171 static const char *const ra_regname
[] = {
179 static char ra_dbg_buf
[65536];
180 static char *ra_dbg_p
;
181 static char *ra_dbg_merge
;
182 static MCode
*ra_dbg_mcp
;
184 static void ra_dstart(void)
186 ra_dbg_p
= ra_dbg_buf
;
191 static void ra_dflush(void)
193 fwrite(ra_dbg_buf
, 1, (size_t)(ra_dbg_p
-ra_dbg_buf
), stdout
);
197 static void ra_dprintf(ASMState
*as
, const char *fmt
, ...)
202 p
= ra_dbg_mcp
== as
->mcp
? ra_dbg_merge
: ra_dbg_p
;
204 p
+= sprintf(p
, "%08x \e[36m%04d ", (uintptr_t)as
->mcp
, as
->curins
-REF_BIAS
);
206 const char *e
= strchr(fmt
, '$');
207 if (e
== NULL
) break;
208 memcpy(p
, fmt
, (size_t)(e
-fmt
));
211 Reg r
= va_arg(argp
, Reg
) & RID_MASK
;
214 for (q
= ra_regname
[r
]; *q
; q
++)
215 *p
++ = *q
>= 'A' && *q
<= 'Z' ? *q
+ 0x20 : *q
;
220 } else if (e
[1] == 'f' || e
[1] == 'i') {
223 ref
= va_arg(argp
, IRRef
);
225 ref
= va_arg(argp
, IRIns
*) - as
->ir
;
227 p
+= sprintf(p
, "%04d", ref
- REF_BIAS
);
229 p
+= sprintf(p
, "K%03d", REF_BIAS
- ref
);
230 } else if (e
[1] == 's') {
231 uint32_t slot
= va_arg(argp
, uint32_t);
232 p
+= sprintf(p
, "[sp+0x%x]", sps_scale(slot
));
233 } else if (e
[1] == 'x') {
234 p
+= sprintf(p
, "%08x", va_arg(argp
, int32_t));
243 *p
++ = '\e'; *p
++ = '['; *p
++ = 'm'; *p
++ = '\n';
244 if (p
> ra_dbg_buf
+sizeof(ra_dbg_buf
)-256) {
245 fwrite(ra_dbg_buf
, 1, (size_t)(p
-ra_dbg_buf
), stdout
);
251 #define RA_DBG_START() ra_dstart()
252 #define RA_DBG_FLUSH() ra_dflush()
253 #define RA_DBG_REF() \
254 do { char *_p = ra_dbg_p; ra_dprintf(as, ""); \
255 ra_dbg_merge = _p; ra_dbg_mcp = as->mcp; } while (0)
256 #define RA_DBGX(x) ra_dprintf x
259 #define RA_DBG_START() ((void)0)
260 #define RA_DBG_FLUSH() ((void)0)
261 #define RA_DBG_REF() ((void)0)
262 #define RA_DBGX(x) ((void)0)
265 /* -- Register allocator -------------------------------------------------- */
267 #define ra_free(as, r) rset_set(as->freeset, (r))
268 #define ra_modified(as, r) rset_set(as->modset, (r))
269 #define ra_weak(as, r) rset_set(as->weakset, (r))
270 #define ra_noweak(as, r) rset_clear(as->weakset, (r))
272 #define ra_used(ir) (ra_hasreg((ir)->r) || ra_hasspill((ir)->s))
274 /* Setup register allocator. */
275 static void ra_setup(ASMState
*as
)
278 /* Initially all regs (except the stack pointer) are free for use. */
279 as
->freeset
= RSET_INIT
;
280 as
->modset
= RSET_EMPTY
;
281 as
->weakset
= RSET_EMPTY
;
282 as
->phiset
= RSET_EMPTY
;
283 memset(as
->phireg
, 0, sizeof(as
->phireg
));
284 for (r
= RID_MIN_GPR
; r
< RID_MAX
; r
++)
285 as
->cost
[r
] = REGCOST(~0u, 0u);
288 /* Rematerialize constants. */
289 static Reg
ra_rematk(ASMState
*as
, IRRef ref
)
293 if (ra_iskref(ref
)) {
295 lua_assert(!rset_test(as
->freeset
, r
));
298 emit_loadi(as
, r
, ra_krefk(as
, ref
));
303 lua_assert(ra_hasreg(r
) && !ra_hasspill(ir
->s
));
306 ir
->r
= RID_INIT
; /* Do not keep any hint. */
307 RA_DBGX((as
, "remat $i $r", ir
, r
));
309 if (ir
->o
== IR_KNUM
) {
310 emit_loadn(as
, r
, ir_knum(ir
));
313 if (emit_canremat(REF_BASE
) && ir
->o
== IR_BASE
) {
314 ra_sethint(ir
->r
, RID_BASE
); /* Restore BASE register hint. */
315 emit_getgl(as
, r
, jit_base
);
316 } else if (emit_canremat(ASMREF_L
) && ir
->o
== IR_KPRI
) {
317 lua_assert(irt_isnil(ir
->t
)); /* REF_NIL stores ASMREF_L register. */
318 emit_getgl(as
, r
, jit_L
);
320 } else if (ir
->o
== IR_KINT64
) {
321 emit_loadu64(as
, r
, ir_kint64(ir
)->u64
);
324 lua_assert(ir
->o
== IR_KINT
|| ir
->o
== IR_KGC
||
325 ir
->o
== IR_KPTR
|| ir
->o
== IR_KKPTR
|| ir
->o
== IR_KNULL
);
326 emit_loadi(as
, r
, ir
->i
);
331 /* Force a spill. Allocate a new spill slot if needed. */
332 static int32_t ra_spill(ASMState
*as
, IRIns
*ir
)
334 int32_t slot
= ir
->s
;
335 if (!ra_hasspill(slot
)) {
336 if (irt_is64(ir
->t
)) {
337 slot
= as
->evenspill
;
339 } else if (as
->oddspill
) {
343 slot
= as
->evenspill
;
344 as
->oddspill
= slot
+1;
347 if (as
->evenspill
> 256)
348 lj_trace_err(as
->J
, LJ_TRERR_SPILLOV
);
349 ir
->s
= (uint8_t)slot
;
351 return sps_scale(slot
);
354 /* Release the temporarily allocated register in ASMREF_TMP1/ASMREF_TMP2. */
355 static Reg
ra_releasetmp(ASMState
*as
, IRRef ref
)
359 lua_assert(ra_hasreg(r
) && !ra_hasspill(ir
->s
));
366 /* Restore a register (marked as free). Rematerialize or force a spill. */
367 static Reg
ra_restore(ASMState
*as
, IRRef ref
)
369 if (emit_canremat(ref
)) {
370 return ra_rematk(as
, ref
);
373 int32_t ofs
= ra_spill(as
, ir
); /* Force a spill slot. */
375 lua_assert(ra_hasreg(r
));
376 ra_sethint(ir
->r
, r
); /* Keep hint. */
378 if (!rset_test(as
->weakset
, r
)) { /* Only restore non-weak references. */
380 RA_DBGX((as
, "restore $i $r", ir
, r
));
381 emit_spload(as
, ir
, r
, ofs
);
387 /* Save a register to a spill slot. */
388 static void ra_save(ASMState
*as
, IRIns
*ir
, Reg r
)
390 RA_DBGX((as
, "save $i $r", ir
, r
));
391 emit_spstore(as
, ir
, r
, sps_scale(ir
->s
));
394 #define MINCOST(name) \
395 if (rset_test(RSET_ALL, RID_##name) && \
396 LJ_LIKELY(allow&RID2RSET(RID_##name)) && as->cost[RID_##name] < cost) \
397 cost = as->cost[RID_##name];
399 /* Evict the register with the lowest cost, forcing a restore. */
400 static Reg
ra_evict(ASMState
*as
, RegSet allow
)
403 RegCost cost
= ~(RegCost
)0;
404 lua_assert(allow
!= RSET_EMPTY
);
405 if (RID_NUM_FPR
== 0 || allow
< RID2RSET(RID_MAX_GPR
)) {
410 ref
= regcost_ref(cost
);
411 lua_assert(ra_iskref(ref
) || (ref
>= as
->T
->nk
&& ref
< as
->T
->nins
));
412 /* Preferably pick any weak ref instead of a non-weak, non-const ref. */
413 if (!irref_isk(ref
) && (as
->weakset
& allow
)) {
415 if (!rset_test(as
->weakset
, ir
->r
))
416 ref
= regcost_ref(as
->cost
[rset_pickbot((as
->weakset
& allow
))]);
418 return ra_restore(as
, ref
);
421 /* Pick any register (marked as free). Evict on-demand. */
422 static Reg
ra_pick(ASMState
*as
, RegSet allow
)
424 RegSet pick
= as
->freeset
& allow
;
426 return ra_evict(as
, allow
);
428 return rset_picktop(pick
);
431 /* Get a scratch register (marked as free). */
432 static Reg
ra_scratch(ASMState
*as
, RegSet allow
)
434 Reg r
= ra_pick(as
, allow
);
436 RA_DBGX((as
, "scratch $r", r
));
440 /* Evict all registers from a set (if not free). */
441 static void ra_evictset(ASMState
*as
, RegSet drop
)
446 work
= (drop
& ~as
->freeset
) & RSET_FPR
;
448 Reg r
= rset_pickbot(work
);
449 ra_restore(as
, regcost_ref(as
->cost
[r
]));
454 work
= (drop
& ~as
->freeset
);
456 Reg r
= rset_pickbot(work
);
457 ra_restore(as
, regcost_ref(as
->cost
[r
]));
463 /* Evict (rematerialize) all registers allocated to constants. */
464 static void ra_evictk(ASMState
*as
)
468 work
= ~as
->freeset
& RSET_FPR
;
470 Reg r
= rset_pickbot(work
);
471 IRRef ref
= regcost_ref(as
->cost
[r
]);
472 if (emit_canremat(ref
) && irref_isk(ref
)) {
479 work
= ~as
->freeset
& RSET_GPR
;
481 Reg r
= rset_pickbot(work
);
482 IRRef ref
= regcost_ref(as
->cost
[r
]);
483 if (emit_canremat(ref
) && irref_isk(ref
)) {
492 /* Allocate a register for a constant. */
493 static Reg
ra_allock(ASMState
*as
, int32_t k
, RegSet allow
)
495 /* First try to find a register which already holds the same constant. */
496 RegSet pick
, work
= ~as
->freeset
& RSET_GPR
;
500 r
= rset_pickbot(work
);
501 ref
= regcost_ref(as
->cost
[r
]);
502 if (ref
< ASMREF_L
&&
503 k
== (ra_iskref(ref
) ? ra_krefk(as
, ref
) : IR(ref
)->i
))
507 pick
= as
->freeset
& allow
;
509 /* Constants should preferably get unmodified registers. */
510 if ((pick
& ~as
->modset
))
512 r
= rset_pickbot(pick
); /* Reduce conflicts with inverse allocation. */
514 r
= ra_evict(as
, allow
);
516 RA_DBGX((as
, "allock $x $r", k
, r
));
517 ra_setkref(as
, r
, k
);
518 rset_clear(as
->freeset
, r
);
523 /* Allocate a specific register for a constant. */
524 static void ra_allockreg(ASMState
*as
, int32_t k
, Reg r
)
526 Reg kr
= ra_allock(as
, k
, RID2RSET(r
));
529 irdummy
.t
.irt
= IRT_INT
;
530 ra_scratch(as
, RID2RSET(r
));
531 emit_movrr(as
, &irdummy
, r
, kr
);
535 #define ra_allockreg(as, k, r) emit_loadi(as, (r), (k))
538 /* Allocate a register for ref from the allowed set of registers.
539 ** Note: this function assumes the ref does NOT have a register yet!
540 ** Picks an optimal register, sets the cost and marks the register as non-free.
542 static Reg
ra_allocref(ASMState
*as
, IRRef ref
, RegSet allow
)
545 RegSet pick
= as
->freeset
& allow
;
547 lua_assert(ra_noreg(ir
->r
));
549 /* First check register hint from propagation or PHI. */
550 if (ra_hashint(ir
->r
)) {
551 r
= ra_gethint(ir
->r
);
552 if (rset_test(pick
, r
)) /* Use hint register if possible. */
554 /* Rematerialization is cheaper than missing a hint. */
555 if (rset_test(allow
, r
) && emit_canremat(regcost_ref(as
->cost
[r
]))) {
556 ra_rematk(as
, regcost_ref(as
->cost
[r
]));
559 RA_DBGX((as
, "hintmiss $f $r", ref
, r
));
561 /* Invariants should preferably get unmodified registers. */
562 if (ref
< as
->loopref
&& !irt_isphi(ir
->t
)) {
563 if ((pick
& ~as
->modset
))
565 r
= rset_pickbot(pick
); /* Reduce conflicts with inverse allocation. */
567 /* We've got plenty of regs, so get callee-save regs if possible. */
568 if (RID_NUM_GPR
> 8 && (pick
& ~RSET_SCRATCH
))
569 pick
&= ~RSET_SCRATCH
;
570 r
= rset_picktop(pick
);
573 r
= ra_evict(as
, allow
);
576 RA_DBGX((as
, "alloc $f $r", ref
, r
));
578 rset_clear(as
->freeset
, r
);
580 as
->cost
[r
] = REGCOST_REF_T(ref
, irt_t(ir
->t
));
584 /* Allocate a register on-demand. */
585 static Reg
ra_alloc1(ASMState
*as
, IRRef ref
, RegSet allow
)
588 /* Note: allow is ignored if the register is already allocated. */
589 if (ra_noreg(r
)) r
= ra_allocref(as
, ref
, allow
);
594 /* Rename register allocation and emit move. */
595 static void ra_rename(ASMState
*as
, Reg down
, Reg up
)
597 IRRef ren
, ref
= regcost_ref(as
->cost
[up
] = as
->cost
[down
]);
601 lua_assert((down
< RID_MAX_GPR
) == (up
< RID_MAX_GPR
));
602 lua_assert(!rset_test(as
->freeset
, down
) && rset_test(as
->freeset
, up
));
603 ra_free(as
, down
); /* 'down' is free ... */
604 ra_modified(as
, down
);
605 rset_clear(as
->freeset
, up
); /* ... and 'up' is now allocated. */
607 RA_DBGX((as
, "rename $f $r $r", regcost_ref(as
->cost
[up
]), down
, up
));
608 emit_movrr(as
, ir
, down
, up
); /* Backwards codegen needs inverse move. */
609 if (!ra_hasspill(IR(ref
)->s
)) { /* Add the rename to the IR. */
610 lj_ir_set(as
->J
, IRT(IR_RENAME
, IRT_NIL
), ref
, as
->snapno
);
611 ren
= tref_ref(lj_ir_emit(as
->J
));
612 as
->ir
= as
->T
->ir
; /* The IR may have been reallocated. */
613 IR(ren
)->r
= (uint8_t)down
;
614 IR(ren
)->s
= SPS_NONE
;
618 /* Pick a destination register (marked as free).
619 ** Caveat: allow is ignored if there's already a destination register.
620 ** Use ra_destreg() to get a specific register.
622 static Reg
ra_dest(ASMState
*as
, IRIns
*ir
, RegSet allow
)
625 if (ra_hasreg(dest
)) {
627 ra_modified(as
, dest
);
629 if (ra_hashint(dest
) && rset_test((as
->freeset
&allow
), ra_gethint(dest
))) {
630 dest
= ra_gethint(dest
);
631 ra_modified(as
, dest
);
632 RA_DBGX((as
, "dest $r", dest
));
634 dest
= ra_scratch(as
, allow
);
638 if (LJ_UNLIKELY(ra_hasspill(ir
->s
))) ra_save(as
, ir
, dest
);
642 /* Force a specific destination register (marked as free). */
643 static void ra_destreg(ASMState
*as
, IRIns
*ir
, Reg r
)
645 Reg dest
= ra_dest(as
, ir
, RID2RSET(r
));
647 lua_assert(rset_test(as
->freeset
, r
));
649 emit_movrr(as
, ir
, dest
, r
);
653 #if LJ_TARGET_X86ORX64
654 /* Propagate dest register to left reference. Emit moves as needed.
655 ** This is a required fixup step for all 2-operand machine instructions.
657 static void ra_left(ASMState
*as
, Reg dest
, IRRef lref
)
659 IRIns
*ir
= IR(lref
);
661 if (ra_noreg(left
)) {
662 if (irref_isk(lref
)) {
663 if (ir
->o
== IR_KNUM
) {
664 cTValue
*tv
= ir_knum(ir
);
665 /* FP remat needs a load except for +0. Still better than eviction. */
666 if (tvispzero(tv
) || !(as
->freeset
& RSET_FPR
)) {
667 emit_loadn(as
, dest
, tv
);
671 } else if (ir
->o
== IR_KINT64
) {
672 emit_loadu64(as
, dest
, ir_kint64(ir
)->u64
);
676 lua_assert(ir
->o
== IR_KINT
|| ir
->o
== IR_KGC
||
677 ir
->o
== IR_KPTR
|| ir
->o
== IR_KKPTR
|| ir
->o
== IR_KNULL
);
678 emit_loadi(as
, dest
, ir
->i
);
682 if (!ra_hashint(left
) && !iscrossref(as
, lref
))
683 ra_sethint(ir
->r
, dest
); /* Propagate register hint. */
684 left
= ra_allocref(as
, lref
, dest
< RID_MAX_GPR
? RSET_GPR
: RSET_FPR
);
687 /* Move needed for true 3-operand instruction: y=a+b ==> y=a; y+=b. */
689 /* Use register renaming if dest is the PHI reg. */
690 if (irt_isphi(ir
->t
) && as
->phireg
[dest
] == lref
) {
691 ra_modified(as
, left
);
692 ra_rename(as
, left
, dest
);
694 emit_movrr(as
, ir
, dest
, left
);
699 /* Similar to ra_left, except we override any hints. */
700 static void ra_leftov(ASMState
*as
, Reg dest
, IRRef lref
)
702 IRIns
*ir
= IR(lref
);
704 if (ra_noreg(left
)) {
705 ra_sethint(ir
->r
, dest
); /* Propagate register hint. */
706 left
= ra_allocref(as
, lref
,
707 (LJ_SOFTFP
|| dest
< RID_MAX_GPR
) ? RSET_GPR
: RSET_FPR
);
711 /* Use register renaming if dest is the PHI reg. */
712 if (irt_isphi(ir
->t
) && as
->phireg
[dest
] == lref
) {
713 ra_modified(as
, left
);
714 ra_rename(as
, left
, dest
);
716 emit_movrr(as
, ir
, dest
, left
);
723 /* Force a RID_RETLO/RID_RETHI destination register pair (marked as free). */
724 static void ra_destpair(ASMState
*as
, IRIns
*ir
)
726 Reg destlo
= ir
->r
, desthi
= (ir
+1)->r
;
727 /* First spill unrelated refs blocking the destination registers. */
728 if (!rset_test(as
->freeset
, RID_RETLO
) &&
729 destlo
!= RID_RETLO
&& desthi
!= RID_RETLO
)
730 ra_restore(as
, regcost_ref(as
->cost
[RID_RETLO
]));
731 if (!rset_test(as
->freeset
, RID_RETHI
) &&
732 destlo
!= RID_RETHI
&& desthi
!= RID_RETHI
)
733 ra_restore(as
, regcost_ref(as
->cost
[RID_RETHI
]));
734 /* Next free the destination registers (if any). */
735 if (ra_hasreg(destlo
)) {
737 ra_modified(as
, destlo
);
741 if (ra_hasreg(desthi
)) {
743 ra_modified(as
, desthi
);
747 /* Check for conflicts and shuffle the registers as needed. */
748 if (destlo
== RID_RETHI
) {
749 if (desthi
== RID_RETLO
) {
751 *--as
->mcp
= XI_XCHGa
+ RID_RETHI
;
753 emit_movrr(as
, ir
, RID_RETHI
, RID_TMP
);
754 emit_movrr(as
, ir
, RID_RETLO
, RID_RETHI
);
755 emit_movrr(as
, ir
, RID_TMP
, RID_RETLO
);
758 emit_movrr(as
, ir
, RID_RETHI
, RID_RETLO
);
759 if (desthi
!= RID_RETHI
) emit_movrr(as
, ir
, desthi
, RID_RETHI
);
761 } else if (desthi
== RID_RETLO
) {
762 emit_movrr(as
, ir
, RID_RETLO
, RID_RETHI
);
763 if (destlo
!= RID_RETLO
) emit_movrr(as
, ir
, destlo
, RID_RETLO
);
765 if (desthi
!= RID_RETHI
) emit_movrr(as
, ir
, desthi
, RID_RETHI
);
766 if (destlo
!= RID_RETLO
) emit_movrr(as
, ir
, destlo
, RID_RETLO
);
768 /* Restore spill slots (if any). */
769 if (ra_hasspill((ir
+1)->s
)) ra_save(as
, ir
+1, RID_RETHI
);
770 if (ra_hasspill(ir
->s
)) ra_save(as
, ir
, RID_RETLO
);
774 /* -- Snapshot handling --------- ----------------------------------------- */
776 /* Can we rematerialize a KNUM instead of forcing a spill? */
777 static int asm_snap_canremat(ASMState
*as
)
780 for (r
= RID_MIN_FPR
; r
< RID_MAX_FPR
; r
++)
781 if (irref_isk(regcost_ref(as
->cost
[r
])))
786 /* Check whether a sunk store corresponds to an allocation. */
787 static int asm_sunk_store(ASMState
*as
, IRIns
*ira
, IRIns
*irs
)
790 if (irs
->o
== IR_ASTORE
|| irs
->o
== IR_HSTORE
||
791 irs
->o
== IR_FSTORE
|| irs
->o
== IR_XSTORE
) {
792 IRIns
*irk
= IR(irs
->op1
);
793 if (irk
->o
== IR_AREF
|| irk
->o
== IR_HREFK
)
795 return (IR(irk
->op1
) == ira
);
799 return (ira
+ irs
->s
== irs
); /* Quick check. */
803 /* Allocate register or spill slot for a ref that escapes to a snapshot. */
804 static void asm_snap_alloc1(ASMState
*as
, IRRef ref
)
807 if (!irref_isk(ref
) && (!(ra_used(ir
) || ir
->r
== RID_SUNK
))) {
808 if (ir
->r
== RID_SINK
) {
811 if (ir
->o
== IR_CNEWI
) { /* Allocate CNEWI value. */
812 asm_snap_alloc1(as
, ir
->op2
);
813 if (LJ_32
&& (ir
+1)->o
== IR_HIOP
)
814 asm_snap_alloc1(as
, (ir
+1)->op2
);
817 { /* Allocate stored values for TNEW, TDUP and CNEW. */
819 lua_assert(ir
->o
== IR_TNEW
|| ir
->o
== IR_TDUP
|| ir
->o
== IR_CNEW
);
820 for (irs
= IR(as
->snapref
-1); irs
> ir
; irs
--)
821 if (irs
->r
== RID_SINK
&& asm_sunk_store(as
, ir
, irs
)) {
822 lua_assert(irs
->o
== IR_ASTORE
|| irs
->o
== IR_HSTORE
||
823 irs
->o
== IR_FSTORE
|| irs
->o
== IR_XSTORE
);
824 asm_snap_alloc1(as
, irs
->op2
);
825 if (LJ_32
&& (irs
+1)->o
== IR_HIOP
)
826 asm_snap_alloc1(as
, (irs
+1)->op2
);
829 } else if (ir
->o
== IR_CONV
&& ir
->op2
== IRCONV_NUM_INT
) {
830 asm_snap_alloc1(as
, ir
->op1
);
832 RegSet allow
= (!LJ_SOFTFP
&& irt_isfp(ir
->t
)) ? RSET_FPR
: RSET_GPR
;
833 if ((as
->freeset
& allow
) ||
834 (allow
== RSET_FPR
&& asm_snap_canremat(as
))) {
835 /* Get a weak register if we have a free one or can rematerialize. */
836 Reg r
= ra_allocref(as
, ref
, allow
); /* Allocate a register. */
837 if (!irt_isphi(ir
->t
))
838 ra_weak(as
, r
); /* But mark it as weakly referenced. */
840 RA_DBGX((as
, "snapreg $f $r", ref
, ir
->r
));
842 ra_spill(as
, ir
); /* Otherwise force a spill slot. */
843 RA_DBGX((as
, "snapspill $f $s", ref
, ir
->s
));
849 /* Allocate refs escaping to a snapshot. */
850 static void asm_snap_alloc(ASMState
*as
)
852 SnapShot
*snap
= &as
->T
->snap
[as
->snapno
];
853 SnapEntry
*map
= &as
->T
->snapmap
[snap
->mapofs
];
854 MSize n
, nent
= snap
->nent
;
855 for (n
= 0; n
< nent
; n
++) {
856 SnapEntry sn
= map
[n
];
857 IRRef ref
= snap_ref(sn
);
858 if (!irref_isk(ref
)) {
859 asm_snap_alloc1(as
, ref
);
860 if (LJ_SOFTFP
&& (sn
& SNAP_SOFTFPNUM
)) {
861 lua_assert(irt_type(IR(ref
+1)->t
) == IRT_SOFTFP
);
862 asm_snap_alloc1(as
, ref
+1);
868 /* All guards for a snapshot use the same exitno. This is currently the
869 ** same as the snapshot number. Since the exact origin of the exit cannot
870 ** be determined, all guards for the same snapshot must exit with the same
872 ** A renamed ref which has been used in a prior guard for the same snapshot
873 ** would cause an inconsistency. The easy way out is to force a spill slot.
875 static int asm_snap_checkrename(ASMState
*as
, IRRef ren
)
877 SnapShot
*snap
= &as
->T
->snap
[as
->snapno
];
878 SnapEntry
*map
= &as
->T
->snapmap
[snap
->mapofs
];
879 MSize n
, nent
= snap
->nent
;
880 for (n
= 0; n
< nent
; n
++) {
881 SnapEntry sn
= map
[n
];
882 IRRef ref
= snap_ref(sn
);
883 if (ref
== ren
|| (LJ_SOFTFP
&& (sn
& SNAP_SOFTFPNUM
) && ++ref
== ren
)) {
885 ra_spill(as
, ir
); /* Register renamed, so force a spill slot. */
886 RA_DBGX((as
, "snaprensp $f $s", ref
, ir
->s
));
887 return 1; /* Found. */
890 return 0; /* Not found. */
893 /* Prepare snapshot for next guard instruction. */
894 static void asm_snap_prep(ASMState
*as
)
896 if (as
->curins
< as
->snapref
) {
898 if (as
->snapno
== 0) return; /* Called by sunk stores before snap #0. */
900 as
->snapref
= as
->T
->snap
[as
->snapno
].ref
;
901 } while (as
->curins
< as
->snapref
);
903 as
->snaprename
= as
->T
->nins
;
905 /* Process any renames above the highwater mark. */
906 for (; as
->snaprename
< as
->T
->nins
; as
->snaprename
++) {
907 IRIns
*ir
= IR(as
->snaprename
);
908 if (asm_snap_checkrename(as
, ir
->op1
))
909 ir
->op2
= REF_BIAS
-1; /* Kill rename. */
914 /* -- Miscellaneous helpers ----------------------------------------------- */
916 /* Collect arguments from CALL* and CARG instructions. */
917 static void asm_collectargs(ASMState
*as
, IRIns
*ir
,
918 const CCallInfo
*ci
, IRRef
*args
)
920 uint32_t n
= CCI_NARGS(ci
);
921 lua_assert(n
<= CCI_NARGS_MAX
);
922 if ((ci
->flags
& CCI_L
)) { *args
++ = ASMREF_L
; n
--; }
925 lua_assert(ir
->o
== IR_CARG
);
926 args
[n
] = ir
->op2
== REF_NIL
? 0 : ir
->op2
;
928 args
[0] = ir
->op1
== REF_NIL
? 0 : ir
->op1
;
929 lua_assert(IR(ir
->op1
)->o
!= IR_CARG
);
932 /* Reconstruct CCallInfo flags for CALLX*. */
933 static uint32_t asm_callx_flags(ASMState
*as
, IRIns
*ir
)
936 if (ir
->op1
!= REF_NIL
) { /* Count number of arguments first. */
937 IRIns
*ira
= IR(ir
->op1
);
939 while (ira
->o
== IR_CARG
) { nargs
++; ira
= IR(ira
->op1
); }
942 if (IR(ir
->op2
)->o
== IR_CARG
) { /* Copy calling convention info. */
943 CTypeID id
= (CTypeID
)IR(IR(ir
->op2
)->op2
)->i
;
944 CType
*ct
= ctype_get(ctype_ctsG(J2G(as
->J
)), id
);
945 nargs
|= ((ct
->info
& CTF_VARARG
) ? CCI_VARARG
: 0);
947 nargs
|= (ctype_cconv(ct
->info
) << CCI_CC_SHIFT
);
951 return (nargs
| (ir
->t
.irt
<< CCI_OTSHIFT
));
954 /* Calculate stack adjustment. */
955 static int32_t asm_stack_adjust(ASMState
*as
)
957 if (as
->evenspill
<= SPS_FIXED
)
959 return sps_scale(sps_align(as
->evenspill
));
962 /* Must match with hash*() in lj_tab.c. */
963 static uint32_t ir_khash(IRIns
*ir
)
966 if (irt_isstr(ir
->t
)) {
967 return ir_kstr(ir
)->hash
;
968 } else if (irt_isnum(ir
->t
)) {
969 lo
= ir_knum(ir
)->u32
.lo
;
970 hi
= ir_knum(ir
)->u32
.hi
<< 1;
971 } else if (irt_ispri(ir
->t
)) {
972 lua_assert(!irt_isnil(ir
->t
));
973 return irt_type(ir
->t
)-IRT_FALSE
;
975 lua_assert(irt_isgcv(ir
->t
));
976 lo
= u32ptr(ir_kgc(ir
));
979 return hashrot(lo
, hi
);
982 /* -- Allocations --------------------------------------------------------- */
984 static void asm_gencall(ASMState
*as
, const CCallInfo
*ci
, IRRef
*args
);
985 static void asm_setupresult(ASMState
*as
, IRIns
*ir
, const CCallInfo
*ci
);
987 static void asm_snew(ASMState
*as
, IRIns
*ir
)
989 const CCallInfo
*ci
= &lj_ir_callinfo
[IRCALL_lj_str_new
];
991 args
[0] = ASMREF_L
; /* lua_State *L */
992 args
[1] = ir
->op1
; /* const char *str */
993 args
[2] = ir
->op2
; /* size_t len */
995 asm_setupresult(as
, ir
, ci
); /* GCstr * */
996 asm_gencall(as
, ci
, args
);
999 static void asm_tnew(ASMState
*as
, IRIns
*ir
)
1001 const CCallInfo
*ci
= &lj_ir_callinfo
[IRCALL_lj_tab_new1
];
1003 args
[0] = ASMREF_L
; /* lua_State *L */
1004 args
[1] = ASMREF_TMP1
; /* uint32_t ahsize */
1006 asm_setupresult(as
, ir
, ci
); /* GCtab * */
1007 asm_gencall(as
, ci
, args
);
1008 ra_allockreg(as
, ir
->op1
| (ir
->op2
<< 24), ra_releasetmp(as
, ASMREF_TMP1
));
1011 static void asm_tdup(ASMState
*as
, IRIns
*ir
)
1013 const CCallInfo
*ci
= &lj_ir_callinfo
[IRCALL_lj_tab_dup
];
1015 args
[0] = ASMREF_L
; /* lua_State *L */
1016 args
[1] = ir
->op1
; /* const GCtab *kt */
1018 asm_setupresult(as
, ir
, ci
); /* GCtab * */
1019 asm_gencall(as
, ci
, args
);
1022 static void asm_gc_check(ASMState
*as
);
1024 /* Explicit GC step. */
1025 static void asm_gcstep(ASMState
*as
, IRIns
*ir
)
1028 for (ira
= IR(as
->stopins
+1); ira
< ir
; ira
++)
1029 if ((ira
->o
== IR_TNEW
|| ira
->o
== IR_TDUP
||
1030 (LJ_HASFFI
&& (ira
->o
== IR_CNEW
|| ira
->o
== IR_CNEWI
))) &&
1035 as
->gcsteps
= 0x80000000; /* Prevent implicit GC check further up. */
1038 /* -- PHI and loop handling ----------------------------------------------- */
1040 /* Break a PHI cycle by renaming to a free register (evict if needed). */
1041 static void asm_phi_break(ASMState
*as
, RegSet blocked
, RegSet blockedby
,
1044 RegSet candidates
= blocked
& allow
;
1045 if (candidates
) { /* If this register file has candidates. */
1046 /* Note: the set for ra_pick cannot be empty, since each register file
1047 ** has some registers never allocated to PHIs.
1049 Reg down
, up
= ra_pick(as
, ~blocked
& allow
); /* Get a free register. */
1050 if (candidates
& ~blockedby
) /* Optimize shifts, else it's a cycle. */
1051 candidates
= candidates
& ~blockedby
;
1052 down
= rset_picktop(candidates
); /* Pick candidate PHI register. */
1053 ra_rename(as
, down
, up
); /* And rename it to the free register. */
1057 /* PHI register shuffling.
1059 ** The allocator tries hard to preserve PHI register assignments across
1060 ** the loop body. Most of the time this loop does nothing, since there
1061 ** are no register mismatches.
1063 ** If a register mismatch is detected and ...
1064 ** - the register is currently free: rename it.
1065 ** - the register is blocked by an invariant: restore/remat and rename it.
1066 ** - Otherwise the register is used by another PHI, so mark it as blocked.
1068 ** The renames are order-sensitive, so just retry the loop if a register
1069 ** is marked as blocked, but has been freed in the meantime. A cycle is
1070 ** detected if all of the blocked registers are allocated. To break the
1071 ** cycle rename one of them to a free register and retry.
1073 ** Note that PHI spill slots are kept in sync and don't need to be shuffled.
1075 static void asm_phi_shuffle(ASMState
*as
)
1079 /* Find and resolve PHI register mismatches. */
1081 RegSet blocked
= RSET_EMPTY
;
1082 RegSet blockedby
= RSET_EMPTY
;
1083 RegSet phiset
= as
->phiset
;
1084 while (phiset
) { /* Check all left PHI operand registers. */
1085 Reg r
= rset_pickbot(phiset
);
1086 IRIns
*irl
= IR(as
->phireg
[r
]);
1088 if (r
!= left
) { /* Mismatch? */
1089 if (!rset_test(as
->freeset
, r
)) { /* PHI register blocked? */
1090 IRRef ref
= regcost_ref(as
->cost
[r
]);
1091 /* Blocked by other PHI (w/reg)? */
1092 if (!ra_iskref(ref
) && irt_ismarked(IR(ref
)->t
)) {
1093 rset_set(blocked
, r
);
1094 if (ra_hasreg(left
))
1095 rset_set(blockedby
, left
);
1097 } else { /* Otherwise grab register from invariant. */
1098 ra_restore(as
, ref
);
1102 if (ra_hasreg(left
)) {
1103 ra_rename(as
, left
, r
);
1107 rset_clear(phiset
, r
);
1109 if (!blocked
) break; /* Finished. */
1110 if (!(as
->freeset
& blocked
)) { /* Break cycles if none are free. */
1111 asm_phi_break(as
, blocked
, blockedby
, RSET_GPR
);
1112 if (!LJ_SOFTFP
) asm_phi_break(as
, blocked
, blockedby
, RSET_FPR
);
1114 } /* Else retry some more renames. */
1117 /* Restore/remat invariants whose registers are modified inside the loop. */
1119 work
= as
->modset
& ~(as
->freeset
| as
->phiset
) & RSET_FPR
;
1121 Reg r
= rset_pickbot(work
);
1122 ra_restore(as
, regcost_ref(as
->cost
[r
]));
1123 rset_clear(work
, r
);
1127 work
= as
->modset
& ~(as
->freeset
| as
->phiset
);
1129 Reg r
= rset_pickbot(work
);
1130 ra_restore(as
, regcost_ref(as
->cost
[r
]));
1131 rset_clear(work
, r
);
1135 /* Allocate and save all unsaved PHI regs and clear marks. */
1138 Reg r
= rset_picktop(work
);
1139 IRRef lref
= as
->phireg
[r
];
1140 IRIns
*ir
= IR(lref
);
1141 if (ra_hasspill(ir
->s
)) { /* Left PHI gained a spill slot? */
1142 irt_clearmark(ir
->t
); /* Handled here, so clear marker now. */
1143 ra_alloc1(as
, lref
, RID2RSET(r
));
1144 ra_save(as
, ir
, r
); /* Save to spill slot inside the loop. */
1147 rset_clear(work
, r
);
1151 /* Copy unsynced left/right PHI spill slots. Rarely needed. */
1152 static void asm_phi_copyspill(ASMState
*as
)
1156 for (ir
= IR(as
->orignins
-1); ir
->o
== IR_PHI
; ir
--)
1157 if (ra_hasspill(ir
->s
) && ra_hasspill(IR(ir
->op1
)->s
))
1158 need
|= irt_isfp(ir
->t
) ? 2 : 1; /* Unsynced spill slot? */
1159 if ((need
& 1)) { /* Copy integer spill slots. */
1160 #if !LJ_TARGET_X86ORX64
1164 if ((as
->freeset
& RSET_GPR
))
1165 r
= rset_pickbot((as
->freeset
& RSET_GPR
));
1167 emit_spload(as
, IR(regcost_ref(as
->cost
[r
])), r
, SPOFS_TMP
);
1169 for (ir
= IR(as
->orignins
-1); ir
->o
== IR_PHI
; ir
--) {
1170 if (ra_hasspill(ir
->s
)) {
1171 IRIns
*irl
= IR(ir
->op1
);
1172 if (ra_hasspill(irl
->s
) && !irt_isfp(ir
->t
)) {
1173 emit_spstore(as
, irl
, r
, sps_scale(irl
->s
));
1174 emit_spload(as
, ir
, r
, sps_scale(ir
->s
));
1178 #if LJ_TARGET_X86ORX64
1179 if (!rset_test(as
->freeset
, r
))
1180 emit_spstore(as
, IR(regcost_ref(as
->cost
[r
])), r
, SPOFS_TMP
);
1184 if ((need
& 2)) { /* Copy FP spill slots. */
1190 if ((as
->freeset
& RSET_FPR
))
1191 r
= rset_pickbot((as
->freeset
& RSET_FPR
));
1192 if (!rset_test(as
->freeset
, r
))
1193 emit_spload(as
, IR(regcost_ref(as
->cost
[r
])), r
, SPOFS_TMP
);
1194 for (ir
= IR(as
->orignins
-1); ir
->o
== IR_PHI
; ir
--) {
1195 if (ra_hasspill(ir
->s
)) {
1196 IRIns
*irl
= IR(ir
->op1
);
1197 if (ra_hasspill(irl
->s
) && irt_isfp(ir
->t
)) {
1198 emit_spstore(as
, irl
, r
, sps_scale(irl
->s
));
1199 emit_spload(as
, ir
, r
, sps_scale(ir
->s
));
1203 if (!rset_test(as
->freeset
, r
))
1204 emit_spstore(as
, IR(regcost_ref(as
->cost
[r
])), r
, SPOFS_TMP
);
1209 /* Emit renames for left PHIs which are only spilled outside the loop. */
1210 static void asm_phi_fixup(ASMState
*as
)
1212 RegSet work
= as
->phiset
;
1214 Reg r
= rset_picktop(work
);
1215 IRRef lref
= as
->phireg
[r
];
1216 IRIns
*ir
= IR(lref
);
1217 /* Left PHI gained a spill slot before the loop? */
1218 if (irt_ismarked(ir
->t
) && ra_hasspill(ir
->s
)) {
1220 lj_ir_set(as
->J
, IRT(IR_RENAME
, IRT_NIL
), lref
, as
->loopsnapno
);
1221 ren
= tref_ref(lj_ir_emit(as
->J
));
1222 as
->ir
= as
->T
->ir
; /* The IR may have been reallocated. */
1223 IR(ren
)->r
= (uint8_t)r
;
1224 IR(ren
)->s
= SPS_NONE
;
1226 irt_clearmark(ir
->t
); /* Always clear marker. */
1227 rset_clear(work
, r
);
1231 /* Setup right PHI reference. */
1232 static void asm_phi(ASMState
*as
, IRIns
*ir
)
1234 RegSet allow
= ((!LJ_SOFTFP
&& irt_isfp(ir
->t
)) ? RSET_FPR
: RSET_GPR
) &
1236 RegSet afree
= (as
->freeset
& allow
);
1237 IRIns
*irl
= IR(ir
->op1
);
1238 IRIns
*irr
= IR(ir
->op2
);
1239 if (ir
->r
== RID_SINK
) /* Sink PHI. */
1241 /* Spill slot shuffling is not implemented yet (but rarely needed). */
1242 if (ra_hasspill(irl
->s
) || ra_hasspill(irr
->s
))
1243 lj_trace_err(as
->J
, LJ_TRERR_NYIPHI
);
1244 /* Leave at least one register free for non-PHIs (and PHI cycle breaking). */
1245 if ((afree
& (afree
-1))) { /* Two or more free registers? */
1247 if (ra_noreg(irr
->r
)) { /* Get a register for the right PHI. */
1248 r
= ra_allocref(as
, ir
->op2
, allow
);
1249 } else { /* Duplicate right PHI, need a copy (rare). */
1250 r
= ra_scratch(as
, allow
);
1251 emit_movrr(as
, irr
, r
, irr
->r
);
1254 rset_set(as
->phiset
, r
);
1255 as
->phireg
[r
] = (IRRef1
)ir
->op1
;
1256 irt_setmark(irl
->t
); /* Marks left PHIs _with_ register. */
1257 if (ra_noreg(irl
->r
))
1258 ra_sethint(irl
->r
, r
); /* Set register hint for left PHI. */
1259 } else { /* Otherwise allocate a spill slot. */
1260 /* This is overly restrictive, but it triggers only on synthetic code. */
1261 if (ra_hasreg(irl
->r
) || ra_hasreg(irr
->r
))
1262 lj_trace_err(as
->J
, LJ_TRERR_NYIPHI
);
1264 irr
->s
= ir
->s
; /* Set right PHI spill slot. Sync left slot later. */
1268 static void asm_loop_fixup(ASMState
*as
);
1270 /* Middle part of a loop. */
1271 static void asm_loop(ASMState
*as
)
1274 /* LOOP is a guard, so the snapno is up to date. */
1275 as
->loopsnapno
= as
->snapno
;
1278 /* LOOP marks the transition from the variant to the invariant part. */
1279 as
->flagmcp
= as
->invmcp
= NULL
;
1281 if (!neverfuse(as
)) as
->fuseref
= 0;
1282 asm_phi_shuffle(as
);
1284 asm_phi_copyspill(as
);
1286 as
->mcloop
= as
->mcp
;
1287 RA_DBGX((as
, "===== LOOP ====="));
1288 if (!as
->realign
) RA_DBG_FLUSH();
1289 if (as
->mcp
!= mcspill
)
1290 emit_jmp(as
, mcspill
);
1293 /* -- Target-specific assembler ------------------------------------------- */
1295 #if LJ_TARGET_X86ORX64
1296 #include "lj_asm_x86.h"
1298 #include "lj_asm_arm.h"
1300 #include "lj_asm_ppc.h"
1301 #elif LJ_TARGET_MIPS
1302 #include "lj_asm_mips.h"
1304 #error "Missing assembler for target CPU"
1307 /* -- Head of trace ------------------------------------------------------- */
1309 /* Head of a root trace. */
1310 static void asm_head_root(ASMState
*as
)
1313 asm_head_root_base(as
);
1314 emit_setvmstate(as
, (int32_t)as
->T
->traceno
);
1315 spadj
= asm_stack_adjust(as
);
1316 as
->T
->spadjust
= (uint16_t)spadj
;
1317 emit_spsub(as
, spadj
);
1318 /* Root traces assume a checked stack for the starting proto. */
1319 as
->T
->topslot
= gcref(as
->T
->startpt
)->pt
.framesize
;
1322 /* Head of a side trace.
1324 ** The current simplistic algorithm requires that all slots inherited
1325 ** from the parent are live in a register between pass 2 and pass 3. This
1326 ** avoids the complexity of stack slot shuffling. But of course this may
1327 ** overflow the register set in some cases and cause the dreaded error:
1328 ** "NYI: register coalescing too complex". A refined algorithm is needed.
1330 static void asm_head_side(ASMState
*as
)
1332 IRRef1 sloadins
[RID_MAX
];
1333 RegSet allow
= RSET_ALL
; /* Inverse of all coalesced registers. */
1334 RegSet live
= RSET_EMPTY
; /* Live parent registers. */
1335 IRIns
*irp
= &as
->parent
->ir
[REF_BASE
]; /* Parent base. */
1336 int32_t spadj
, spdelta
;
1341 allow
= asm_head_side_base(as
, irp
, allow
);
1343 /* Scan all parent SLOADs and collect register dependencies. */
1344 for (i
= as
->stopins
; i
> REF_BASE
; i
--) {
1347 lua_assert((ir
->o
== IR_SLOAD
&& (ir
->op2
& IRSLOAD_PARENT
)) ||
1348 (LJ_SOFTFP
&& ir
->o
== IR_HIOP
) || ir
->o
== IR_PVAL
);
1349 rs
= as
->parentmap
[i
- REF_FIRST
];
1350 if (ra_hasreg(ir
->r
)) {
1351 rset_clear(allow
, ir
->r
);
1352 if (ra_hasspill(ir
->s
)) {
1353 ra_save(as
, ir
, ir
->r
);
1356 } else if (ra_hasspill(ir
->s
)) {
1360 if (ir
->r
== rs
) { /* Coalesce matching registers right now. */
1362 } else if (ra_hasspill(regsp_spill(rs
))) {
1363 if (ra_hasreg(ir
->r
))
1365 } else if (ra_used(ir
)) {
1366 sloadins
[rs
] = (IRRef1
)i
;
1367 rset_set(live
, rs
); /* Block live parent register. */
1371 /* Calculate stack frame adjustment. */
1372 spadj
= asm_stack_adjust(as
);
1373 spdelta
= spadj
- (int32_t)as
->parent
->spadjust
;
1374 if (spdelta
< 0) { /* Don't shrink the stack frame. */
1375 spadj
= (int32_t)as
->parent
->spadjust
;
1378 as
->T
->spadjust
= (uint16_t)spadj
;
1380 /* Reload spilled target registers. */
1382 for (i
= as
->stopins
; i
> REF_BASE
; i
--) {
1384 if (irt_ismarked(ir
->t
)) {
1388 irt_clearmark(ir
->t
);
1389 rs
= as
->parentmap
[i
- REF_FIRST
];
1390 if (!ra_hasspill(regsp_spill(rs
)))
1391 ra_sethint(ir
->r
, rs
); /* Hint may be gone, set it again. */
1392 else if (sps_scale(regsp_spill(rs
))+spdelta
== sps_scale(ir
->s
))
1393 continue; /* Same spill slot, do nothing. */
1394 mask
= ((!LJ_SOFTFP
&& irt_isnum(ir
->t
)) ? RSET_FPR
: RSET_GPR
) & allow
;
1395 if (mask
== RSET_EMPTY
)
1396 lj_trace_err(as
->J
, LJ_TRERR_NYICOAL
);
1397 r
= ra_allocref(as
, i
, mask
);
1399 rset_clear(allow
, r
);
1400 if (r
== rs
) { /* Coalesce matching registers right now. */
1402 rset_clear(live
, r
);
1403 } else if (ra_hasspill(regsp_spill(rs
))) {
1411 /* Store trace number and adjust stack frame relative to the parent. */
1412 emit_setvmstate(as
, (int32_t)as
->T
->traceno
);
1413 emit_spsub(as
, spdelta
);
1415 #if !LJ_TARGET_X86ORX64
1416 /* Restore BASE register from parent spill slot. */
1417 if (ra_hasspill(irp
->s
))
1418 emit_spload(as
, IR(REF_BASE
), IR(REF_BASE
)->r
, sps_scale(irp
->s
));
1421 /* Restore target registers from parent spill slots. */
1423 RegSet work
= ~as
->freeset
& RSET_ALL
;
1425 Reg r
= rset_pickbot(work
);
1426 IRRef ref
= regcost_ref(as
->cost
[r
]);
1427 RegSP rs
= as
->parentmap
[ref
- REF_FIRST
];
1428 rset_clear(work
, r
);
1429 if (ra_hasspill(regsp_spill(rs
))) {
1430 int32_t ofs
= sps_scale(regsp_spill(rs
));
1432 emit_spload(as
, IR(ref
), r
, ofs
);
1438 /* Shuffle registers to match up target regs with parent regs. */
1442 /* Repeatedly coalesce free live registers by moving to their target. */
1443 while ((work
= as
->freeset
& live
) != RSET_EMPTY
) {
1444 Reg rp
= rset_pickbot(work
);
1445 IRIns
*ir
= IR(sloadins
[rp
]);
1446 rset_clear(live
, rp
);
1447 rset_clear(allow
, rp
);
1449 emit_movrr(as
, ir
, ir
->r
, rp
);
1453 /* We're done if no live registers remain. */
1454 if (live
== RSET_EMPTY
)
1457 /* Break cycles by renaming one target to a temp. register. */
1458 if (live
& RSET_GPR
) {
1459 RegSet tmpset
= as
->freeset
& ~live
& allow
& RSET_GPR
;
1460 if (tmpset
== RSET_EMPTY
)
1461 lj_trace_err(as
->J
, LJ_TRERR_NYICOAL
);
1462 ra_rename(as
, rset_pickbot(live
& RSET_GPR
), rset_pickbot(tmpset
));
1464 if (!LJ_SOFTFP
&& (live
& RSET_FPR
)) {
1465 RegSet tmpset
= as
->freeset
& ~live
& allow
& RSET_FPR
;
1466 if (tmpset
== RSET_EMPTY
)
1467 lj_trace_err(as
->J
, LJ_TRERR_NYICOAL
);
1468 ra_rename(as
, rset_pickbot(live
& RSET_FPR
), rset_pickbot(tmpset
));
1471 /* Continue with coalescing to fix up the broken cycle(s). */
1474 /* Inherit top stack slot already checked by parent trace. */
1475 as
->T
->topslot
= as
->parent
->topslot
;
1476 if (as
->topslot
> as
->T
->topslot
) { /* Need to check for higher slot? */
1477 #ifdef EXITSTATE_CHECKEXIT
1478 /* Highest exit + 1 indicates stack check. */
1479 ExitNo exitno
= as
->T
->nsnap
;
1481 /* Reuse the parent exit in the context of the parent trace. */
1482 ExitNo exitno
= as
->J
->exitno
;
1484 as
->T
->topslot
= (uint8_t)as
->topslot
; /* Remember for child traces. */
1485 asm_stack_check(as
, as
->topslot
, irp
, allow
& RSET_GPR
, exitno
);
1489 /* -- Tail of trace ------------------------------------------------------- */
1491 /* Get base slot for a snapshot. */
1492 static BCReg
asm_baseslot(ASMState
*as
, SnapShot
*snap
, int *gotframe
)
1494 SnapEntry
*map
= &as
->T
->snapmap
[snap
->mapofs
];
1496 for (n
= snap
->nent
; n
> 0; n
--) {
1497 SnapEntry sn
= map
[n
-1];
1498 if ((sn
& SNAP_FRAME
)) {
1500 return snap_slot(sn
);
1506 /* Link to another trace. */
1507 static void asm_tail_link(ASMState
*as
)
1509 SnapNo snapno
= as
->T
->nsnap
-1; /* Last snapshot. */
1510 SnapShot
*snap
= &as
->T
->snap
[snapno
];
1512 BCReg baseslot
= asm_baseslot(as
, snap
, &gotframe
);
1514 as
->topslot
= snap
->topslot
;
1516 ra_allocref(as
, REF_BASE
, RID2RSET(RID_BASE
));
1518 if (as
->T
->link
== 0) {
1519 /* Setup fixed registers for exit to interpreter. */
1520 const BCIns
*pc
= snap_pc(as
->T
->snapmap
[snap
->mapofs
+ snap
->nent
]);
1522 if (bc_op(*pc
) == BC_JLOOP
) { /* NYI: find a better way to do this. */
1523 BCIns
*retpc
= &traceref(as
->J
, bc_d(*pc
))->startins
;
1524 if (bc_isret(bc_op(*retpc
)))
1527 ra_allockreg(as
, i32ptr(J2GG(as
->J
)->dispatch
), RID_DISPATCH
);
1528 ra_allockreg(as
, i32ptr(pc
), RID_LPC
);
1529 mres
= (int32_t)(snap
->nslots
- baseslot
);
1530 switch (bc_op(*pc
)) {
1531 case BC_CALLM
: case BC_CALLMT
:
1532 mres
-= (int32_t)(1 + bc_a(*pc
) + bc_c(*pc
)); break;
1533 case BC_RETM
: mres
-= (int32_t)(bc_a(*pc
) + bc_d(*pc
)); break;
1534 case BC_TSETM
: mres
-= (int32_t)bc_a(*pc
); break;
1535 default: if (bc_op(*pc
) < BC_FUNCF
) mres
= 0; break;
1537 ra_allockreg(as
, mres
, RID_RET
); /* Return MULTRES or 0. */
1538 } else if (baseslot
) {
1539 /* Save modified BASE for linking to trace with higher start frame. */
1540 emit_setgl(as
, RID_BASE
, jit_base
);
1542 emit_addptr(as
, RID_BASE
, 8*(int32_t)baseslot
);
1544 /* Sync the interpreter state with the on-trace state. */
1545 asm_stack_restore(as
, snap
);
1547 /* Root traces that add frames need to check the stack at the end. */
1548 if (!as
->parent
&& gotframe
)
1549 asm_stack_check(as
, as
->topslot
, NULL
, as
->freeset
& RSET_GPR
, snapno
);
1552 /* -- Trace setup --------------------------------------------------------- */
1554 /* Clear reg/sp for all instructions and add register hints. */
1555 static void asm_setup_regsp(ASMState
*as
)
1558 int sink
= T
->sinktags
;
1559 IRRef nins
= T
->nins
;
1563 uint32_t rload
= 0xa6402a64;
1568 /* Clear reg/sp for constants. */
1569 for (ir
= IR(T
->nk
), lastir
= IR(REF_BASE
); ir
< lastir
; ir
++)
1570 ir
->prev
= REGSP_INIT
;
1572 /* REF_BASE is used for implicit references to the BASE register. */
1573 lastir
->prev
= REGSP_HINT(RID_BASE
);
1576 if (ir
->o
== IR_RENAME
) {
1577 do { ir
--; nins
--; } while (ir
->o
== IR_RENAME
);
1578 T
->nins
= nins
; /* Remove any renames left over from ASM restart. */
1580 as
->snaprename
= nins
;
1582 as
->snapno
= T
->nsnap
;
1584 as
->stopins
= REF_BASE
;
1585 as
->orignins
= nins
;
1588 /* Setup register hints for parent link instructions. */
1592 lastir
= lj_snap_regspmap(as
->parent
, as
->J
->exitno
, ir
);
1593 if (lastir
- ir
> LJ_MAX_JSLOTS
)
1594 lj_trace_err(as
->J
, LJ_TRERR_NYICOAL
);
1595 as
->stopins
= (IRRef
)((lastir
-1) - as
->ir
);
1596 for (p
= as
->parentmap
; ir
< lastir
; ir
++) {
1597 RegSP rs
= ir
->prev
;
1598 *p
++ = (uint16_t)rs
; /* Copy original parent RegSP to parentmap. */
1599 if (!ra_hasspill(regsp_spill(rs
)))
1600 ir
->prev
= (uint16_t)REGSP_HINT(regsp_reg(rs
));
1602 ir
->prev
= REGSP_INIT
;
1607 as
->evenspill
= SPS_FIRST
;
1608 for (lastir
= IR(nins
); ir
< lastir
; ir
++) {
1610 if (ir
->r
== RID_SINK
)
1612 if (ir
->r
== RID_SUNK
) { /* Revert after ASM restart. */
1623 if (!((ir
->op2
& IRSLOAD_TYPECHECK
) || (ir
+1)->o
== IR_HIOP
))
1626 case IR_ALOAD
: case IR_HLOAD
: case IR_ULOAD
: case IR_VLOAD
:
1627 if (!LJ_SOFTFP
&& irt_isnum(ir
->t
)) break;
1628 ir
->prev
= (uint16_t)REGSP_HINT((rload
& 15));
1629 rload
= lj_ror(rload
, 4);
1634 ci
.flags
= asm_callx_flags(as
, ir
);
1635 ir
->prev
= asm_setup_call_slots(as
, ir
, &ci
);
1637 as
->modset
|= RSET_SCRATCH
;
1640 case IR_CALLN
: case IR_CALLL
: case IR_CALLS
: {
1641 const CCallInfo
*ci
= &lj_ir_callinfo
[ir
->op2
];
1642 ir
->prev
= asm_setup_call_slots(as
, ir
, ci
);
1644 as
->modset
|= (ci
->flags
& CCI_NOFPRCLOBBER
) ?
1645 (RSET_SCRATCH
& ~RSET_FPR
) : RSET_SCRATCH
;
1648 #if LJ_SOFTFP || (LJ_32 && LJ_HASFFI)
1650 switch ((ir
-1)->o
) {
1651 #if LJ_SOFTFP && LJ_TARGET_ARM
1652 case IR_SLOAD
: case IR_ALOAD
: case IR_HLOAD
: case IR_ULOAD
: case IR_VLOAD
:
1653 if (ra_hashint((ir
-1)->r
)) {
1654 ir
->prev
= (ir
-1)->prev
+ 1;
1659 #if !LJ_SOFTFP && LJ_NEED_FP64
1661 if (irt_isfp((ir
-1)->t
)) {
1662 ir
->prev
= REGSP_HINT(RID_FPRET
);
1667 case IR_CALLN
: case IR_CALLXS
:
1669 case IR_MIN
: case IR_MAX
:
1671 (ir
-1)->prev
= REGSP_HINT(RID_RETLO
);
1672 ir
->prev
= REGSP_HINT(RID_RETHI
);
1680 case IR_MIN
: case IR_MAX
:
1681 if ((ir
+1)->o
!= IR_HIOP
) break;
1684 /* C calls evict all scratch regs and return results in RID_RET. */
1685 case IR_SNEW
: case IR_XSNEW
: case IR_NEWREF
:
1686 if (REGARG_NUMGPR
< 3 && as
->evenspill
< 3)
1687 as
->evenspill
= 3; /* lj_str_new and lj_tab_newkey need 3 args. */
1688 case IR_TNEW
: case IR_TDUP
: case IR_CNEW
: case IR_CNEWI
: case IR_TOSTR
:
1689 ir
->prev
= REGSP_HINT(RID_RET
);
1691 as
->modset
= RSET_SCRATCH
;
1693 case IR_STRTO
: case IR_OBAR
:
1695 as
->modset
= RSET_SCRATCH
;
1697 #if !LJ_TARGET_X86ORX64 && !LJ_SOFTFP
1698 case IR_ATAN2
: case IR_LDEXP
:
1701 if (!LJ_SOFTFP
&& irt_isnum(ir
->t
)) {
1702 #if LJ_TARGET_X86ORX64
1703 ir
->prev
= REGSP_HINT(RID_XMM0
);
1705 as
->modset
|= RSET_RANGE(RID_XMM0
, RID_XMM1
+1)|RID2RSET(RID_EAX
);
1707 ir
->prev
= REGSP_HINT(RID_FPRET
);
1709 as
->modset
|= RSET_SCRATCH
;
1713 /* fallthrough for integer POW */
1714 case IR_DIV
: case IR_MOD
:
1715 if (!irt_isnum(ir
->t
)) {
1716 ir
->prev
= REGSP_HINT(RID_RET
);
1718 as
->modset
|= (RSET_SCRATCH
& RSET_GPR
);
1723 #if LJ_TARGET_X86ORX64
1724 if (ir
->op2
== IRFPM_EXP2
) { /* May be joined to lj_vm_pow_sse. */
1725 ir
->prev
= REGSP_HINT(RID_XMM0
);
1727 if (as
->evenspill
< 4) /* Leave room for 16 byte scratch area. */
1731 as
->modset
|= RSET_RANGE(RID_XMM0
, RID_XMM2
+1)|RID2RSET(RID_EAX
);
1733 } else if (ir
->op2
<= IRFPM_TRUNC
&& !(as
->flags
& JIT_F_SSE4_1
)) {
1734 ir
->prev
= REGSP_HINT(RID_XMM0
);
1736 as
->modset
|= RSET_RANGE(RID_XMM0
, RID_XMM3
+1)|RID2RSET(RID_EAX
);
1741 ir
->prev
= REGSP_HINT(RID_FPRET
);
1743 as
->modset
|= RSET_SCRATCH
;
1746 #if LJ_TARGET_X86ORX64
1747 /* Non-constant shift counts need to be in RID_ECX on x86/x64. */
1748 case IR_BSHL
: case IR_BSHR
: case IR_BSAR
: case IR_BROL
: case IR_BROR
:
1749 if (!irref_isk(ir
->op2
) && !ra_hashint(IR(ir
->op2
)->r
)) {
1750 IR(ir
->op2
)->r
= REGSP_HINT(RID_ECX
);
1752 rset_set(as
->modset
, RID_ECX
);
1756 /* Do not propagate hints across type conversions or loads. */
1760 case IR_ALOAD
: case IR_HLOAD
: case IR_ULOAD
: case IR_VLOAD
:
1764 if (irt_isfp(ir
->t
) || (ir
->op2
& IRCONV_SRCMASK
) == IRT_NUM
||
1765 (ir
->op2
& IRCONV_SRCMASK
) == IRT_FLOAT
)
1769 /* Propagate hints across likely 'op reg, imm' or 'op reg'. */
1770 if (irref_isk(ir
->op2
) && !irref_isk(ir
->op1
) &&
1771 ra_hashint(regsp_reg(IR(ir
->op1
)->prev
))) {
1772 ir
->prev
= IR(ir
->op1
)->prev
;
1777 ir
->prev
= REGSP_INIT
;
1779 if ((as
->evenspill
& 1))
1780 as
->oddspill
= as
->evenspill
++;
1785 /* -- Assembler core ------------------------------------------------------ */
1787 /* Assemble a trace. */
1788 void lj_asm_trace(jit_State
*J
, GCtrace
*T
)
1791 ASMState
*as
= &as_
;
1794 /* Ensure an initialized instruction beyond the last one for HIOP checks. */
1795 J
->cur
.nins
= lj_ir_nextins(J
);
1796 J
->cur
.ir
[J
->cur
.nins
].o
= IR_NOP
;
1798 /* Setup initial state. Copy some fields to reduce indirections. */
1802 as
->flags
= J
->flags
;
1803 as
->loopref
= J
->loopref
;
1806 as
->parent
= J
->parent
? traceref(J
, J
->parent
) : NULL
;
1808 /* Reserve MCode memory. */
1809 as
->mctop
= origtop
= lj_mcode_reserve(J
, &as
->mcbot
);
1810 as
->mcp
= as
->mctop
;
1811 as
->mclim
= as
->mcbot
+ MCLIM_REDZONE
;
1812 asm_setup_target(as
);
1815 as
->mcp
= as
->mctop
;
1816 as
->curins
= T
->nins
;
1818 RA_DBGX((as
, "===== STOP ====="));
1820 /* General trace setup. Emit tail of trace. */
1826 as
->sectref
= as
->loopref
;
1827 as
->fuseref
= (as
->flags
& JIT_F_OPT_FUSE
) ? as
->loopref
: FUSE_DISABLED
;
1828 asm_setup_regsp(as
);
1832 /* Assemble a trace in linear backwards order. */
1833 for (as
->curins
--; as
->curins
> as
->stopins
; as
->curins
--) {
1834 IRIns
*ir
= IR(as
->curins
);
1835 lua_assert(!(LJ_32
&& irt_isint64(ir
->t
))); /* Handled by SPLIT. */
1836 if (!ra_used(ir
) && !ir_sideeff(ir
) && (as
->flags
& JIT_F_OPT_DCE
))
1837 continue; /* Dead-code elimination can be soooo easy. */
1838 if (irt_isguard(ir
->t
))
1844 } while (as
->realign
); /* Retry in case the MCode needs to be realigned. */
1846 /* Emit head of trace. */
1849 if (as
->gcsteps
> 0) {
1850 as
->curins
= as
->T
->snap
[0].ref
;
1851 asm_snap_prep(as
); /* The GC check is a guard. */
1861 RA_DBGX((as
, "===== START ===="));
1863 if (as
->freeset
!= RSET_ALL
)
1864 lj_trace_err(as
->J
, LJ_TRERR_BADRA
); /* Ouch! Should never happen. */
1866 /* Set trace entry point before fixing up tail to allow link to self. */
1868 T
->mcloop
= as
->mcloop
? (MSize
)((char *)as
->mcloop
- (char *)as
->mcp
) : 0;
1870 asm_tail_fixup(as
, T
->link
); /* Note: this may change as->mctop! */
1871 T
->szmcode
= (MSize
)((char *)as
->mctop
- (char *)as
->mcp
);
1872 lj_mcode_sync(T
->mcode
, origtop
);