1 From 1bcbfe173abb9650c8ae13677d4dca4f0222ab7e Mon Sep 17 00:00:00 2001
2 From: Ilari Liusvaara <ilari.liusvaara@elisanet.fi>
3 Date: Mon, 18 Nov 2013 01:53:58 +0200
4 Subject: [PATCH 2/5] Expose CPU registers
7 libgambatte/include/gambatte.h | 22 +++++++++++++++++++
8 libgambatte/src/cpu.h | 4 ++--
9 libgambatte/src/gambatte.cpp | 48 ++++++++++++++++++++++++++++++++++++++++++
10 3 files changed, 72 insertions(+), 2 deletions(-)
12 diff --git a/libgambatte/include/gambatte.h b/libgambatte/include/gambatte.h
13 index 2901fdf..5094906 100644
14 --- a/libgambatte/include/gambatte.h
15 +++ b/libgambatte/include/gambatte.h
16 @@ -237,6 +237,28 @@ public:
19 static std::string version();
21 + /** CPU registers. */
40 + uint32_t get_cpureg(enum cpu_register reg);
41 + void set_cpureg(enum cpu_register reg, uint32_t val);
43 void preload_common();
44 void postload_common(const unsigned flags);
45 diff --git a/libgambatte/src/cpu.h b/libgambatte/src/cpu.h
46 index 9f9a11e..224ba0b 100644
47 --- a/libgambatte/src/cpu.h
48 +++ b/libgambatte/src/cpu.h
49 @@ -88,13 +88,13 @@ public:
50 std::pair<unsigned char*, size_t> getIoRam() { return mem_.getIoRam(); }
51 std::pair<unsigned char*, size_t> getVideoRam() { return mem_.getVideoRam(); };
55 unsigned cycleCounter_;
58 unsigned hf1, hf2, zf, cf;
59 unsigned char a_, b, c, d, e, /*f,*/ h, l;
64 void process(unsigned cycles);
65 diff --git a/libgambatte/src/gambatte.cpp b/libgambatte/src/gambatte.cpp
66 index 0204557..a61e177 100644
67 --- a/libgambatte/src/gambatte.cpp
68 +++ b/libgambatte/src/gambatte.cpp
69 @@ -298,4 +298,52 @@ std::string GB::version()
73 +uint32_t GB::get_cpureg(enum cpu_register _reg)
76 + case REG_CYCLECOUNTER: return p_->cpu.cycleCounter_;
77 + case REG_PC: return p_->cpu.pc_;
78 + case REG_SP: return p_->cpu.sp;
79 + case REG_HF1: return p_->cpu.hf1;
80 + case REG_HF2: return p_->cpu.hf2;
81 + case REG_ZF: return p_->cpu.zf;
82 + case REG_CF: return p_->cpu.cf;
83 + case REG_A: return p_->cpu.a_;
84 + case REG_B: return p_->cpu.b;
85 + case REG_C: return p_->cpu.c;
86 + case REG_D: return p_->cpu.d;
87 + case REG_E: return p_->cpu.e;
89 + return ((p_->cpu.hf2 & 0x600 | (p_->cpu.cf & 0x100)) >> 4)
90 + | (p_->cpu.zf & 0xFF ? 0 : 0x80);
91 + case REG_H: return p_->cpu.h;
92 + case REG_L: return p_->cpu.l;
97 +void GB::set_cpureg(enum cpu_register _reg, uint32_t val)
100 + case REG_PC: p_->cpu.pc_ = val; break;
101 + case REG_SP: p_->cpu.sp = val; break;
102 + case REG_HF1: p_->cpu.hf1 = val; break;
103 + case REG_HF2: p_->cpu.hf2 = val; break;
104 + case REG_ZF: p_->cpu.zf = val; break;
105 + case REG_CF: p_->cpu.cf = val; break;
106 + case REG_A: p_->cpu.a_ = val; break;
107 + case REG_B: p_->cpu.b = val; break;
108 + case REG_C: p_->cpu.c = val; break;
109 + case REG_D: p_->cpu.d = val; break;
110 + case REG_E: p_->cpu.e = val; break;
112 + p_->cpu.hf2 = (val << 4) & 0x600;
113 + p_->cpu.cf = (val << 4) & 0x100;
114 + p_->cpu.zf = val & 0x80;
116 + case REG_H: p_->cpu.h = val; break;
117 + case REG_L: p_->cpu.l = val; break;