utils/TableGen/InstrInfoEmitter.cpp

   1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This tablegen backend is responsible for emitting a description of the target
  11 // instruction set for the code generator.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "InstrInfoEmitter.h"
  16 #include "CodeGenTarget.h"
  17 #include "Record.h"
  18 #include "llvm/ADT/StringExtras.h"
  19 #include <algorithm>
  20 using namespace llvm;
  21
  22 static void PrintDefList(const std::vector<Record*> &Uses,
  23                          unsigned Num, raw_ostream &OS) {
  24   OS << "static const unsigned ImplicitList" << Num << "[] = { ";
  25   for (unsigned i = 0, e = Uses.size(); i != e; ++i)
  26     OS << getQualifiedName(Uses[i]) << ", ";
  27   OS << "0 };\n";
  28 }
  29
  30 //===----------------------------------------------------------------------===//
  31 // Instruction Itinerary Information.
  32 //===----------------------------------------------------------------------===//
  33
  34 void InstrInfoEmitter::GatherItinClasses() {
  35   std::vector<Record*> DefList =
  36   Records.getAllDerivedDefinitions("InstrItinClass");
  37   std::sort(DefList.begin(), DefList.end(), LessRecord());
  38
  39   for (unsigned i = 0, N = DefList.size(); i < N; i++)
  40     ItinClassMap[DefList[i]->getName()] = i;
  41 }
  42
  43 unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
  44   return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
  45 }
  46
  47 //===----------------------------------------------------------------------===//
  48 // Operand Info Emission.
  49 //===----------------------------------------------------------------------===//
  50
  51 std::vector<std::string>
  52 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
  53   std::vector<std::string> Result;
  54
  55   for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
  56     // Handle aggregate operands and normal operands the same way by expanding
  57     // either case into a list of operands for this op.
  58     std::vector<CGIOperandList::OperandInfo> OperandList;
  59
  60     // This might be a multiple operand thing.  Targets like X86 have
  61     // registers in their multi-operand operands.  It may also be an anonymous
  62     // operand, which has a single operand, but no declared class for the
  63     // operand.
  64     DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
  65
  66     if (!MIOI || MIOI->getNumArgs() == 0) {
  67       // Single, anonymous, operand.
  68       OperandList.push_back(Inst.Operands[i]);
  69     } else {
  70       for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
  71         OperandList.push_back(Inst.Operands[i]);
  72
  73         Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
  74         OperandList.back().Rec = OpR;
  75       }
  76     }
  77
  78     for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
  79       Record *OpR = OperandList[j].Rec;
  80       std::string Res;
  81
  82       if (OpR->isSubClassOf("RegisterOperand"))
  83         OpR = OpR->getValueAsDef("RegClass");
  84       if (OpR->isSubClassOf("RegisterClass"))
  85         Res += getQualifiedName(OpR) + "RegClassID, ";
  86       else if (OpR->isSubClassOf("PointerLikeRegClass"))
  87         Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
  88       else
  89         // -1 means the operand does not have a fixed register class.
  90         Res += "-1, ";
  91
  92       // Fill in applicable flags.
  93       Res += "0";
  94
  95       // Ptr value whose register class is resolved via callback.
  96       if (OpR->isSubClassOf("PointerLikeRegClass"))
  97         Res += "|(1<<MCOI::LookupPtrRegClass)";
  98
  99       // Predicate operands.  Check to see if the original unexpanded operand
 100       // was of type PredicateOperand.
 101       if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
 102         Res += "|(1<<MCOI::Predicate)";
 103
 104       // Optional def operands.  Check to see if the original unexpanded operand
 105       // was of type OptionalDefOperand.
 106       if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
 107         Res += "|(1<<MCOI::OptionalDef)";
 108
 109       // Fill in constraint info.
 110       Res += ", ";
 111
 112       const CGIOperandList::ConstraintInfo &Constraint =
 113         Inst.Operands[i].Constraints[j];
 114       if (Constraint.isNone())
 115         Res += "0";
 116       else if (Constraint.isEarlyClobber())
 117         Res += "(1 << MCOI::EARLY_CLOBBER)";
 118       else {
 119         assert(Constraint.isTied());
 120         Res += "((" + utostr(Constraint.getTiedOperand()) +
 121                     " << 16) | (1 << MCOI::TIED_TO))";
 122       }
 123
 124       Result.push_back(Res);
 125     }
 126   }
 127
 128   return Result;
 129 }
 130
 131 void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
 132                                        OperandInfoMapTy &OperandInfoIDs) {
 133   // ID #0 is for no operand info.
 134   unsigned OperandListNum = 0;
 135   OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
 136
 137   OS << "\n";
 138   const CodeGenTarget &Target = CDP.getTargetInfo();
 139   for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
 140        E = Target.inst_end(); II != E; ++II) {
 141     std::vector<std::string> OperandInfo = GetOperandInfo(**II);
 142     unsigned &N = OperandInfoIDs[OperandInfo];
 143     if (N != 0) continue;
 144
 145     N = ++OperandListNum;
 146     OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
 147     for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
 148       OS << "{ " << OperandInfo[i] << " }, ";
 149     OS << "};\n";
 150   }
 151 }
 152
 153 //===----------------------------------------------------------------------===//
 154 // Main Output.
 155 //===----------------------------------------------------------------------===//
 156
 157 // run - Emit the main instruction description records for the target...
 158 void InstrInfoEmitter::run(raw_ostream &OS) {
 159   emitEnums(OS);
 160
 161   GatherItinClasses();
 162
 163   EmitSourceFileHeader("Target Instruction Descriptors", OS);
 164
 165   OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n";
 166   OS << "#undef GET_INSTRINFO_MC_DESC\n";
 167
 168   OS << "namespace llvm {\n\n";
 169
 170   CodeGenTarget &Target = CDP.getTargetInfo();
 171   const std::string &TargetName = Target.getName();
 172   Record *InstrInfo = Target.getInstructionSet();
 173
 174   // Keep track of all of the def lists we have emitted already.
 175   std::map<std::vector<Record*>, unsigned> EmittedLists;
 176   unsigned ListNumber = 0;
 177
 178   // Emit all of the instruction's implicit uses and defs.
 179   for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
 180          E = Target.inst_end(); II != E; ++II) {
 181     Record *Inst = (*II)->TheDef;
 182     std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
 183     if (!Uses.empty()) {
 184       unsigned &IL = EmittedLists[Uses];
 185       if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
 186     }
 187     std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
 188     if (!Defs.empty()) {
 189       unsigned &IL = EmittedLists[Defs];
 190       if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
 191     }
 192   }
 193
 194   OperandInfoMapTy OperandInfoIDs;
 195
 196   // Emit all of the operand info records.
 197   EmitOperandInfo(OS, OperandInfoIDs);
 198
 199   // Emit all of the MCInstrDesc records in their ENUM ordering.
 200   //
 201   OS << "\nstatic const MCInstrDesc " << TargetName
 202      << "Insts[] = {\n";
 203   const std::vector<const CodeGenInstruction*> &NumberedInstructions =
 204     Target.getInstructionsByEnumValue();
 205
 206   for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
 207     emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
 208                OperandInfoIDs, OS);
 209   OS << "};\n\n";
 210
 211   // MCInstrInfo initialization routine.
 212   OS << "static inline void Init" << TargetName
 213      << "MCInstrInfo(MCInstrInfo *II) {\n";
 214   OS << "  II->InitMCInstrInfo(" << TargetName << "Insts, "
 215      << NumberedInstructions.size() << ");\n}\n\n";
 216
 217   OS << "} // End llvm namespace \n";
 218
 219   OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
 220
 221   // Create a TargetInstrInfo subclass to hide the MC layer initialization.
 222   OS << "\n#ifdef GET_INSTRINFO_HEADER\n";
 223   OS << "#undef GET_INSTRINFO_HEADER\n";
 224
 225   std::string ClassName = TargetName + "GenInstrInfo";
 226   OS << "namespace llvm {\n";
 227   OS << "struct " << ClassName << " : public TargetInstrInfoImpl {\n"
 228      << "  explicit " << ClassName << "(int SO = -1, int DO = -1);\n"
 229      << "};\n";
 230   OS << "} // End llvm namespace \n";
 231
 232   OS << "#endif // GET_INSTRINFO_HEADER\n\n";
 233
 234   OS << "\n#ifdef GET_INSTRINFO_CTOR\n";
 235   OS << "#undef GET_INSTRINFO_CTOR\n";
 236
 237   OS << "namespace llvm {\n";
 238   OS << ClassName << "::" << ClassName << "(int SO, int DO)\n"
 239      << "  : TargetInstrInfoImpl(SO, DO) {\n"
 240      << "  InitMCInstrInfo(" << TargetName << "Insts, "
 241      << NumberedInstructions.size() << ");\n}\n";
 242   OS << "} // End llvm namespace \n";
 243
 244   OS << "#endif // GET_INSTRINFO_CTOR\n\n";
 245 }
 246
 247 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
 248                                   Record *InstrInfo,
 249                          std::map<std::vector<Record*>, unsigned> &EmittedLists,
 250                                   const OperandInfoMapTy &OpInfo,
 251                                   raw_ostream &OS) {
 252   int MinOperands = 0;
 253   if (!Inst.Operands.size() == 0)
 254     // Each logical operand can be multiple MI operands.
 255     MinOperands = Inst.Operands.back().MIOperandNo +
 256                   Inst.Operands.back().MINumOperands;
 257
 258   OS << "  { ";
 259   OS << Num << ",\t" << MinOperands << ",\t"
 260      << Inst.Operands.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
 261      << ",\t\"" << Inst.TheDef->getName() << "\", 0";
 262
 263   // Emit all of the target indepedent flags...
 264   if (Inst.isReturn)           OS << "|(1<<MCID::Return)";
 265   if (Inst.isBranch)           OS << "|(1<<MCID::Branch)";
 266   if (Inst.isIndirectBranch)   OS << "|(1<<MCID::IndirectBranch)";
 267   if (Inst.isCompare)          OS << "|(1<<MCID::Compare)";
 268   if (Inst.isMoveImm)          OS << "|(1<<MCID::MoveImm)";
 269   if (Inst.isBitcast)          OS << "|(1<<MCID::Bitcast)";
 270   if (Inst.isBarrier)          OS << "|(1<<MCID::Barrier)";
 271   if (Inst.hasDelaySlot)       OS << "|(1<<MCID::DelaySlot)";
 272   if (Inst.isCall)             OS << "|(1<<MCID::Call)";
 273   if (Inst.canFoldAsLoad)      OS << "|(1<<MCID::FoldableAsLoad)";
 274   if (Inst.mayLoad)            OS << "|(1<<MCID::MayLoad)";
 275   if (Inst.mayStore)           OS << "|(1<<MCID::MayStore)";
 276   if (Inst.isPredicable)       OS << "|(1<<MCID::Predicable)";
 277   if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)";
 278   if (Inst.isCommutable)       OS << "|(1<<MCID::Commutable)";
 279   if (Inst.isTerminator)       OS << "|(1<<MCID::Terminator)";
 280   if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)";
 281   if (Inst.isNotDuplicable)    OS << "|(1<<MCID::NotDuplicable)";
 282   if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)";
 283   if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)";
 284   if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)";
 285   if (Inst.hasSideEffects)     OS << "|(1<<MCID::UnmodeledSideEffects)";
 286   if (Inst.isAsCheapAsAMove)   OS << "|(1<<MCID::CheapAsAMove)";
 287   if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)";
 288   if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)";
 289
 290   // Emit all of the target-specific flags...
 291   BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
 292   if (!TSF) throw "no TSFlags?";
 293   uint64_t Value = 0;
 294   for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
 295     if (BitInit *Bit = dynamic_cast<BitInit*>(TSF->getBit(i)))
 296       Value |= uint64_t(Bit->getValue()) << i;
 297     else
 298       throw "Invalid TSFlags bit in " + Inst.TheDef->getName();
 299   }
 300   OS << ", 0x";
 301   OS.write_hex(Value);
 302   OS << "ULL, ";
 303
 304   // Emit the implicit uses and defs lists...
 305   std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
 306   if (UseList.empty())
 307     OS << "NULL, ";
 308   else
 309     OS << "ImplicitList" << EmittedLists[UseList] << ", ";
 310
 311   std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
 312   if (DefList.empty())
 313     OS << "NULL, ";
 314   else
 315     OS << "ImplicitList" << EmittedLists[DefList] << ", ";
 316
 317   // Emit the operand info.
 318   std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
 319   if (OperandInfo.empty())
 320     OS << "0";
 321   else
 322     OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
 323
 324   OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
 325 }
 326
 327 // emitEnums - Print out enum values for all of the instructions.
 328 void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
 329   EmitSourceFileHeader("Target Instruction Enum Values", OS);
 330
 331   OS << "\n#ifdef GET_INSTRINFO_ENUM\n";
 332   OS << "#undef GET_INSTRINFO_ENUM\n";
 333
 334   OS << "namespace llvm {\n\n";
 335
 336   CodeGenTarget Target(Records);
 337
 338   // We must emit the PHI opcode first...
 339   std::string Namespace = Target.getInstNamespace();
 340
 341   if (Namespace.empty()) {
 342     fprintf(stderr, "No instructions defined!\n");
 343     exit(1);
 344   }
 345
 346   const std::vector<const CodeGenInstruction*> &NumberedInstructions =
 347     Target.getInstructionsByEnumValue();
 348
 349   OS << "namespace " << Namespace << " {\n";
 350   OS << "  enum {\n";
 351   for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
 352     OS << "    " << NumberedInstructions[i]->TheDef->getName()
 353        << "\t= " << i << ",\n";
 354   }
 355   OS << "    INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
 356   OS << "  };\n}\n";
 357   OS << "} // End llvm namespace \n";
 358
 359   OS << "#endif // GET_INSTRINFO_ENUM\n\n";
 360 }