lib/Target/Mips/MipsTargetMachine.cpp

   1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Implements the info about Mips target spec.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsMCAsmInfo.h"
  16 #include "MipsTargetMachine.h"
  17 #include "llvm/PassManager.h"
  18 #include "llvm/Target/TargetRegistry.h"
  19 using namespace llvm;
  20
  21 extern "C" void LLVMInitializeMipsTarget() {
  22   // Register the target.
  23   RegisterTargetMachine<MipsTargetMachine> X(TheMipsTarget);
  24   RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
  25   RegisterAsmInfo<MipsMCAsmInfo> A(TheMipsTarget);
  26   RegisterAsmInfo<MipsMCAsmInfo> B(TheMipselTarget);
  27 }
  28
  29 // DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
  30 // The stack is always 8 byte aligned
  31 // On function prologue, the stack is created by decrementing
  32 // its pointer. Once decremented, all references are done with positive
  33 // offset from the stack/frame pointer, using StackGrowsUp enables
  34 // an easier handling.
  35 // Using CodeModel::Large enables different CALL behavior.
  36 MipsTargetMachine::
  37 MipsTargetMachine(const Target &T, const std::string &TT,
  38                   const std::string &CPU, const std::string &FS,
  39                   bool isLittle=false):
  40   LLVMTargetMachine(T, TT, CPU, FS),
  41   Subtarget(TT, CPU, FS, isLittle),
  42   DataLayout(isLittle ?
  43              std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
  44              std::string("E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
  45   InstrInfo(*this),
  46   FrameLowering(Subtarget),
  47   TLInfo(*this), TSInfo(*this) {
  48   // Abicall enables PIC by default
  49   if (getRelocationModel() == Reloc::Default) {
  50     if (Subtarget.isABI_O32())
  51       setRelocationModel(Reloc::PIC_);
  52     else
  53       setRelocationModel(Reloc::Static);
  54   }
  55 }
  56
  57 MipselTargetMachine::
  58 MipselTargetMachine(const Target &T, const std::string &TT,
  59                     const std::string &CPU, const std::string &FS) :
  60   MipsTargetMachine(T, TT, CPU, FS, true) {}
  61
  62 // Install an instruction selector pass using
  63 // the ISelDag to gen Mips code.
  64 bool MipsTargetMachine::
  65 addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
  66 {
  67   PM.add(createMipsISelDag(*this));
  68   return false;
  69 }
  70
  71 // Implemented by targets that want to run passes immediately before
  72 // machine code is emitted. return true if -print-machineinstrs should
  73 // print out the code after the passes.
  74 bool MipsTargetMachine::
  75 addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
  76 {
  77   PM.add(createMipsDelaySlotFillerPass(*this));
  78   return true;
  79 }
  80
  81 bool MipsTargetMachine::
  82 addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
  83   PM.add(createMipsEmitGPRestorePass(*this));
  84   return true;
  85 }
  86
  87 bool MipsTargetMachine::
  88 addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
  89   PM.add(createMipsExpandPseudoPass(*this));
  90   return true;
  91 }