Silence -Wunused-variable in release builds.
[llvm/stm8.git] / lib / Target / Mips / MipsSubtarget.cpp
blobb2b26521fffdc0192c8cf9feb3830552e6695eea
1 //===- MipsSubtarget.cpp - Mips Subtarget Information -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSubtarget.h"
15 #include "Mips.h"
16 #include "llvm/Target/TargetRegistry.h"
18 #define GET_SUBTARGETINFO_ENUM
19 #define GET_SUBTARGETINFO_MC_DESC
20 #define GET_SUBTARGETINFO_TARGET_DESC
21 #define GET_SUBTARGETINFO_CTOR
22 #include "MipsGenSubtargetInfo.inc"
24 using namespace llvm;
26 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
27 const std::string &FS, bool little) :
28 MipsGenSubtargetInfo(TT, CPU, FS),
29 MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
30 IsFP64bit(false), IsGP64bit(false), HasVFPU(false), IsLinux(true),
31 HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), HasMinMax(false),
32 HasSwap(false), HasBitCount(false)
34 std::string CPUName = CPU;
35 if (CPUName.empty())
36 CPUName = "mips1";
37 MipsArchVersion = Mips1;
39 // Parse features string.
40 ParseSubtargetFeatures(CPUName, FS);
42 // Initialize scheduling itinerary for the specified CPU.
43 InstrItins = getInstrItineraryForCPU(CPUName);
45 // Is the target system Linux ?
46 if (TT.find("linux") == std::string::npos)
47 IsLinux = false;
49 // When only the target triple is specified and is
50 // a allegrex target, set the features. We also match
51 // big and little endian allegrex cores (dont really
52 // know if a big one exists)
53 if (TT.find("mipsallegrex") != std::string::npos ||
54 TT.find("psp") != std::string::npos) {
55 MipsABI = EABI;
56 IsSingleFloat = true;
57 MipsArchVersion = Mips2;
58 HasVFPU = true; // Enables Allegrex Vector FPU (not supported yet)
59 HasSEInReg = true;
60 HasBitCount = true;
61 HasSwap = true;
62 HasCondMov = true;
66 MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
67 StringRef FS) {
68 MCSubtargetInfo *X = new MCSubtargetInfo();
69 InitMipsMCSubtargetInfo(X, CPU, FS);
70 return X;
73 extern "C" void LLVMInitializeMipsMCSubtargetInfo() {
74 TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,
75 createMipsMCSubtargetInfo);