Silence -Wunused-variable in release builds.
[llvm/stm8.git] / lib / Target / Mips / MipsRegisterInfo.cpp
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1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
16 #include "Mips.h"
17 #include "MipsSubtarget.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsMachineFunction.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Type.h"
22 #include "llvm/Function.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineLocation.h"
28 #include "llvm/Target/TargetFrameLowering.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/ADT/BitVector.h"
37 #include "llvm/ADT/STLExtras.h"
38 #include "llvm/Analysis/DebugInfo.h"
40 #define GET_REGINFO_MC_DESC
41 #define GET_REGINFO_TARGET_DESC
42 #include "MipsGenRegisterInfo.inc"
44 using namespace llvm;
46 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
47 const TargetInstrInfo &tii)
48 : MipsGenRegisterInfo(), Subtarget(ST), TII(tii) {}
50 /// getRegisterNumbering - Given the enum value for some register, e.g.
51 /// Mips::RA, return the number that it corresponds to (e.g. 31).
52 unsigned MipsRegisterInfo::
53 getRegisterNumbering(unsigned RegEnum)
55 switch (RegEnum) {
56 case Mips::ZERO : case Mips::F0 : case Mips::D0 : return 0;
57 case Mips::AT : case Mips::F1 : return 1;
58 case Mips::V0 : case Mips::F2 : case Mips::D1 : return 2;
59 case Mips::V1 : case Mips::F3 : return 3;
60 case Mips::A0 : case Mips::F4 : case Mips::D2 : return 4;
61 case Mips::A1 : case Mips::F5 : return 5;
62 case Mips::A2 : case Mips::F6 : case Mips::D3 : return 6;
63 case Mips::A3 : case Mips::F7 : return 7;
64 case Mips::T0 : case Mips::F8 : case Mips::D4 : return 8;
65 case Mips::T1 : case Mips::F9 : return 9;
66 case Mips::T2 : case Mips::F10: case Mips::D5: return 10;
67 case Mips::T3 : case Mips::F11: return 11;
68 case Mips::T4 : case Mips::F12: case Mips::D6: return 12;
69 case Mips::T5 : case Mips::F13: return 13;
70 case Mips::T6 : case Mips::F14: case Mips::D7: return 14;
71 case Mips::T7 : case Mips::F15: return 15;
72 case Mips::S0 : case Mips::F16: case Mips::D8: return 16;
73 case Mips::S1 : case Mips::F17: return 17;
74 case Mips::S2 : case Mips::F18: case Mips::D9: return 18;
75 case Mips::S3 : case Mips::F19: return 19;
76 case Mips::S4 : case Mips::F20: case Mips::D10: return 20;
77 case Mips::S5 : case Mips::F21: return 21;
78 case Mips::S6 : case Mips::F22: case Mips::D11: return 22;
79 case Mips::S7 : case Mips::F23: return 23;
80 case Mips::T8 : case Mips::F24: case Mips::D12: return 24;
81 case Mips::T9 : case Mips::F25: return 25;
82 case Mips::K0 : case Mips::F26: case Mips::D13: return 26;
83 case Mips::K1 : case Mips::F27: return 27;
84 case Mips::GP : case Mips::F28: case Mips::D14: return 28;
85 case Mips::SP : case Mips::F29: return 29;
86 case Mips::FP : case Mips::F30: case Mips::D15: return 30;
87 case Mips::RA : case Mips::F31: return 31;
88 default: llvm_unreachable("Unknown register number!");
90 return 0; // Not reached
93 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
95 //===----------------------------------------------------------------------===//
96 // Callee Saved Registers methods
97 //===----------------------------------------------------------------------===//
99 /// Mips Callee Saved Registers
100 const unsigned* MipsRegisterInfo::
101 getCalleeSavedRegs(const MachineFunction *MF) const
103 // Mips callee-save register range is $16-$23, $f20-$f30
104 static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
105 Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26,
106 Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20,
107 Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
108 Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
111 static const unsigned Mips32CalleeSavedRegs[] = {
112 Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10,
113 Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
114 Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
117 if (Subtarget.isSingleFloat())
118 return SingleFloatOnlyCalleeSavedRegs;
119 else
120 return Mips32CalleeSavedRegs;
123 BitVector MipsRegisterInfo::
124 getReservedRegs(const MachineFunction &MF) const {
125 BitVector Reserved(getNumRegs());
126 Reserved.set(Mips::ZERO);
127 Reserved.set(Mips::AT);
128 Reserved.set(Mips::K0);
129 Reserved.set(Mips::K1);
130 Reserved.set(Mips::GP);
131 Reserved.set(Mips::SP);
132 Reserved.set(Mips::FP);
133 Reserved.set(Mips::RA);
134 Reserved.set(Mips::F31);
135 Reserved.set(Mips::D15);
137 // SRV4 requires that odd register can't be used.
138 if (!Subtarget.isSingleFloat() && !Subtarget.isMips32())
139 for (unsigned FReg=(Mips::F0)+1; FReg < Mips::F30; FReg+=2)
140 Reserved.set(FReg);
142 return Reserved;
145 // This function eliminate ADJCALLSTACKDOWN,
146 // ADJCALLSTACKUP pseudo instructions
147 void MipsRegisterInfo::
148 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
149 MachineBasicBlock::iterator I) const {
150 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
151 MBB.erase(I);
154 // FrameIndex represent objects inside a abstract stack.
155 // We must replace FrameIndex with an stack/frame pointer
156 // direct reference.
157 void MipsRegisterInfo::
158 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
159 RegScavenger *RS) const {
160 MachineInstr &MI = *II;
161 MachineFunction &MF = *MI.getParent()->getParent();
162 MachineFrameInfo *MFI = MF.getFrameInfo();
163 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
165 unsigned i = 0;
166 while (!MI.getOperand(i).isFI()) {
167 ++i;
168 assert(i < MI.getNumOperands() &&
169 "Instr doesn't have FrameIndex operand!");
172 DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
173 errs() << "<--------->\n" << MI);
175 int FrameIndex = MI.getOperand(i).getIndex();
176 int stackSize = MF.getFrameInfo()->getStackSize();
177 int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
179 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
180 << "spOffset : " << spOffset << "\n"
181 << "stackSize : " << stackSize << "\n");
183 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
184 int MinCSFI = 0;
185 int MaxCSFI = -1;
187 if (CSI.size()) {
188 MinCSFI = CSI[0].getFrameIdx();
189 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
192 // The following stack frame objects are always referenced relative to $sp:
193 // 1. Outgoing arguments.
194 // 2. Pointer to dynamically allocated stack space.
195 // 3. Locations for callee-saved registers.
196 // Everything else is referenced relative to whatever register
197 // getFrameRegister() returns.
198 unsigned FrameReg;
200 if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
201 (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
202 FrameReg = Mips::SP;
203 else
204 FrameReg = getFrameRegister(MF);
206 // Calculate final offset.
207 // - There is no need to change the offset if the frame object is one of the
208 // following: an outgoing argument, pointer to a dynamically allocated
209 // stack space or a $gp restore location,
210 // - If the frame object is any of the following, its offset must be adjusted
211 // by adding the size of the stack:
212 // incoming argument, callee-saved register location or local variable.
213 int Offset;
215 if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) ||
216 MipsFI->isDynAllocFI(FrameIndex))
217 Offset = spOffset;
218 else
219 Offset = spOffset + stackSize;
221 Offset += MI.getOperand(i+1).getImm();
223 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
225 // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
226 // field.
227 if (!MI.isDebugValue() && (Offset >= 0x8000 || Offset < -0x8000)) {
228 MachineBasicBlock &MBB = *MI.getParent();
229 DebugLoc DL = II->getDebugLoc();
230 int ImmHi = (((unsigned)Offset & 0xffff0000) >> 16) +
231 ((Offset & 0x8000) != 0);
233 // FIXME: change this when mips goes MC".
234 BuildMI(MBB, II, DL, TII.get(Mips::NOAT));
235 BuildMI(MBB, II, DL, TII.get(Mips::LUi), Mips::AT).addImm(ImmHi);
236 BuildMI(MBB, II, DL, TII.get(Mips::ADDu), Mips::AT).addReg(FrameReg)
237 .addReg(Mips::AT);
238 FrameReg = Mips::AT;
239 Offset = (short)(Offset & 0xffff);
241 BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO));
244 MI.getOperand(i).ChangeToRegister(FrameReg, false);
245 MI.getOperand(i+1).ChangeToImmediate(Offset);
248 unsigned MipsRegisterInfo::
249 getRARegister() const {
250 return Mips::RA;
253 unsigned MipsRegisterInfo::
254 getFrameRegister(const MachineFunction &MF) const {
255 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
257 return TFI->hasFP(MF) ? Mips::FP : Mips::SP;
260 unsigned MipsRegisterInfo::
261 getEHExceptionRegister() const {
262 llvm_unreachable("What is the exception register");
263 return 0;
266 unsigned MipsRegisterInfo::
267 getEHHandlerRegister() const {
268 llvm_unreachable("What is the exception handler register");
269 return 0;
272 int MipsRegisterInfo::
273 getDwarfRegNum(unsigned RegNum, bool isEH) const {
274 return MipsGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
277 int MipsRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
278 return MipsGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);