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Silence -Wunused-variable in release builds.
[llvm/stm8.git] / lib / Target / Mips / MipsISelLowering.cpp
blobb4f4b1b4bf045bff383a2f893e60f1dff2bcee24
1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsTargetObjectFile.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "InstPrinter/MipsInstPrinter.h"
27 #include "llvm/CodeGen/CallingConvLower.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 using namespace llvm;
37
38 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
39 switch (Opcode) {
40 case MipsISD::JmpLink: return "MipsISD::JmpLink";
41 case MipsISD::Hi: return "MipsISD::Hi";
42 case MipsISD::Lo: return "MipsISD::Lo";
43 case MipsISD::GPRel: return "MipsISD::GPRel";
44 case MipsISD::TlsGd: return "MipsISD::TlsGd";
45 case MipsISD::TprelHi: return "MipsISD::TprelHi";
46 case MipsISD::TprelLo: return "MipsISD::TprelLo";
47 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
48 case MipsISD::Ret: return "MipsISD::Ret";
49 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
50 case MipsISD::FPCmp: return "MipsISD::FPCmp";
51 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
52 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
53 case MipsISD::FPRound: return "MipsISD::FPRound";
54 case MipsISD::MAdd: return "MipsISD::MAdd";
55 case MipsISD::MAddu: return "MipsISD::MAddu";
56 case MipsISD::MSub: return "MipsISD::MSub";
57 case MipsISD::MSubu: return "MipsISD::MSubu";
58 case MipsISD::DivRem: return "MipsISD::DivRem";
59 case MipsISD::DivRemU: return "MipsISD::DivRemU";
60 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
61 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
62 case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC";
63 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
64 default: return NULL;
65 }
66 }
67
68 MipsTargetLowering::
69 MipsTargetLowering(MipsTargetMachine &TM)
70 : TargetLowering(TM, new MipsTargetObjectFile()) {
71 Subtarget = &TM.getSubtarget<MipsSubtarget>();
72
73 // Mips does not have i1 type, so use i32 for
74 // setcc operations results (slt, sgt, ...).
75 setBooleanContents(ZeroOrOneBooleanContent);
76
77 // Set up the register classes
78 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
79 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
80
81 // When dealing with single precision only, use libcalls
82 if (!Subtarget->isSingleFloat())
83 if (!Subtarget->isFP64bit())
84 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
85
86 // Load extented operations for i1 types must be promoted
87 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
88 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
89 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
90
91 // MIPS doesn't have extending float->double load/store
92 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
93 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
94
95 // Used by legalize types to correctly generate the setcc result.
96 // Without this, every float setcc comes with a AND/OR with the result,
97 // we don't want this, since the fpcmp result goes to a flag register,
98 // which is used implicitly by brcond and select operations.
99 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
100
101 // Mips Custom Operations
102 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
103 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
104 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
105 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
106 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
107 setOperationAction(ISD::SELECT, MVT::f32, Custom);
108 setOperationAction(ISD::SELECT, MVT::f64, Custom);
109 setOperationAction(ISD::SELECT, MVT::i32, Custom);
110 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
111 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
112 setOperationAction(ISD::VASTART, MVT::Other, Custom);
113
114 setOperationAction(ISD::SDIV, MVT::i32, Expand);
115 setOperationAction(ISD::SREM, MVT::i32, Expand);
116 setOperationAction(ISD::UDIV, MVT::i32, Expand);
117 setOperationAction(ISD::UREM, MVT::i32, Expand);
118
119 // Operations not directly supported by Mips.
120 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
121 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
122 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
123 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
124 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
125 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
126 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
127 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
128 setOperationAction(ISD::ROTL, MVT::i32, Expand);
129
130 if (!Subtarget->isMips32r2())
131 setOperationAction(ISD::ROTR, MVT::i32, Expand);
132
133 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
134 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
135 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
136 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
137 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
138 setOperationAction(ISD::FSIN, MVT::f32, Expand);
139 setOperationAction(ISD::FSIN, MVT::f64, Expand);
140 setOperationAction(ISD::FCOS, MVT::f32, Expand);
141 setOperationAction(ISD::FCOS, MVT::f64, Expand);
142 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
143 setOperationAction(ISD::FPOW, MVT::f32, Expand);
144 setOperationAction(ISD::FPOW, MVT::f64, Expand);
145 setOperationAction(ISD::FLOG, MVT::f32, Expand);
146 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
147 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
148 setOperationAction(ISD::FEXP, MVT::f32, Expand);
149 setOperationAction(ISD::FMA, MVT::f32, Expand);
150 setOperationAction(ISD::FMA, MVT::f64, Expand);
151
152 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
153 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
154
155 setOperationAction(ISD::VAARG, MVT::Other, Expand);
156 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
157 setOperationAction(ISD::VAEND, MVT::Other, Expand);
158
159 // Use the default for now
160 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
161 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
162 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
163
164 if (Subtarget->isSingleFloat())
165 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
166
167 if (!Subtarget->hasSEInReg()) {
168 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
169 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
170 }
171
172 if (!Subtarget->hasBitCount())
173 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
174
175 if (!Subtarget->hasSwap())
176 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
177
178 setTargetDAGCombine(ISD::ADDE);
179 setTargetDAGCombine(ISD::SUBE);
180 setTargetDAGCombine(ISD::SDIVREM);
181 setTargetDAGCombine(ISD::UDIVREM);
182 setTargetDAGCombine(ISD::SETCC);
183
184 setMinFunctionAlignment(2);
185
186 setStackPointerRegisterToSaveRestore(Mips::SP);
187 computeRegisterProperties();
188
189 setExceptionPointerRegister(Mips::A0);
190 setExceptionSelectorRegister(Mips::A1);
191 }
192
193 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
194 return MVT::i32;
195 }
196
197 // SelectMadd -
198 // Transforms a subgraph in CurDAG if the following pattern is found:
199 // (addc multLo, Lo0), (adde multHi, Hi0),
200 // where,
201 // multHi/Lo: product of multiplication
202 // Lo0: initial value of Lo register
203 // Hi0: initial value of Hi register
204 // Return true if pattern matching was successful.
205 static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
206 // ADDENode's second operand must be a flag output of an ADDC node in order
207 // for the matching to be successful.
208 SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
209
210 if (ADDCNode->getOpcode() != ISD::ADDC)
211 return false;
212
213 SDValue MultHi = ADDENode->getOperand(0);
214 SDValue MultLo = ADDCNode->getOperand(0);
215 SDNode* MultNode = MultHi.getNode();
216 unsigned MultOpc = MultHi.getOpcode();
217
218 // MultHi and MultLo must be generated by the same node,
219 if (MultLo.getNode() != MultNode)
220 return false;
221
222 // and it must be a multiplication.
223 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
224 return false;
225
226 // MultLo amd MultHi must be the first and second output of MultNode
227 // respectively.
228 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
229 return false;
230
231 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
232 // of the values of MultNode, in which case MultNode will be removed in later
233 // phases.
234 // If there exist users other than ADDENode or ADDCNode, this function returns
235 // here, which will result in MultNode being mapped to a single MULT
236 // instruction node rather than a pair of MULT and MADD instructions being
237 // produced.
238 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
239 return false;
240
241 SDValue Chain = CurDAG->getEntryNode();
242 DebugLoc dl = ADDENode->getDebugLoc();
243
244 // create MipsMAdd(u) node
245 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
246
247 SDValue MAdd = CurDAG->getNode(MultOpc, dl,
248 MVT::Glue,
249 MultNode->getOperand(0),// Factor 0
250 MultNode->getOperand(1),// Factor 1
251 ADDCNode->getOperand(1),// Lo0
252 ADDENode->getOperand(1));// Hi0
253
254 // create CopyFromReg nodes
255 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
256 MAdd);
257 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
258 Mips::HI, MVT::i32,
259 CopyFromLo.getValue(2));
260
261 // replace uses of adde and addc here
262 if (!SDValue(ADDCNode, 0).use_empty())
263 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
264
265 if (!SDValue(ADDENode, 0).use_empty())
266 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
267
268 return true;
269 }
270
271 // SelectMsub -
272 // Transforms a subgraph in CurDAG if the following pattern is found:
273 // (addc Lo0, multLo), (sube Hi0, multHi),
274 // where,
275 // multHi/Lo: product of multiplication
276 // Lo0: initial value of Lo register
277 // Hi0: initial value of Hi register
278 // Return true if pattern matching was successful.
279 static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
280 // SUBENode's second operand must be a flag output of an SUBC node in order
281 // for the matching to be successful.
282 SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
283
284 if (SUBCNode->getOpcode() != ISD::SUBC)
285 return false;
286
287 SDValue MultHi = SUBENode->getOperand(1);
288 SDValue MultLo = SUBCNode->getOperand(1);
289 SDNode* MultNode = MultHi.getNode();
290 unsigned MultOpc = MultHi.getOpcode();
291
292 // MultHi and MultLo must be generated by the same node,
293 if (MultLo.getNode() != MultNode)
294 return false;
295
296 // and it must be a multiplication.
297 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
298 return false;
299
300 // MultLo amd MultHi must be the first and second output of MultNode
301 // respectively.
302 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
303 return false;
304
305 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
306 // of the values of MultNode, in which case MultNode will be removed in later
307 // phases.
308 // If there exist users other than SUBENode or SUBCNode, this function returns
309 // here, which will result in MultNode being mapped to a single MULT
310 // instruction node rather than a pair of MULT and MSUB instructions being
311 // produced.
312 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
313 return false;
314
315 SDValue Chain = CurDAG->getEntryNode();
316 DebugLoc dl = SUBENode->getDebugLoc();
317
318 // create MipsSub(u) node
319 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
320
321 SDValue MSub = CurDAG->getNode(MultOpc, dl,
322 MVT::Glue,
323 MultNode->getOperand(0),// Factor 0
324 MultNode->getOperand(1),// Factor 1
325 SUBCNode->getOperand(0),// Lo0
326 SUBENode->getOperand(0));// Hi0
327
328 // create CopyFromReg nodes
329 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
330 MSub);
331 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
332 Mips::HI, MVT::i32,
333 CopyFromLo.getValue(2));
334
335 // replace uses of sube and subc here
336 if (!SDValue(SUBCNode, 0).use_empty())
337 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
338
339 if (!SDValue(SUBENode, 0).use_empty())
340 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
341
342 return true;
343 }
344
345 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
346 TargetLowering::DAGCombinerInfo &DCI,
347 const MipsSubtarget* Subtarget) {
348 if (DCI.isBeforeLegalize())
349 return SDValue();
350
351 if (Subtarget->isMips32() && SelectMadd(N, &DAG))
352 return SDValue(N, 0);
353
354 return SDValue();
355 }
356
357 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
358 TargetLowering::DAGCombinerInfo &DCI,
359 const MipsSubtarget* Subtarget) {
360 if (DCI.isBeforeLegalize())
361 return SDValue();
362
363 if (Subtarget->isMips32() && SelectMsub(N, &DAG))
364 return SDValue(N, 0);
365
366 return SDValue();
367 }
368
369 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
370 TargetLowering::DAGCombinerInfo &DCI,
371 const MipsSubtarget* Subtarget) {
372 if (DCI.isBeforeLegalizeOps())
373 return SDValue();
374
375 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
376 MipsISD::DivRemU;
377 DebugLoc dl = N->getDebugLoc();
378
379 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
380 N->getOperand(0), N->getOperand(1));
381 SDValue InChain = DAG.getEntryNode();
382 SDValue InGlue = DivRem;
383
384 // insert MFLO
385 if (N->hasAnyUseOfValue(0)) {
386 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32,
387 InGlue);
388 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
389 InChain = CopyFromLo.getValue(1);
390 InGlue = CopyFromLo.getValue(2);
391 }
392
393 // insert MFHI
394 if (N->hasAnyUseOfValue(1)) {
395 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
396 Mips::HI, MVT::i32, InGlue);
397 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
398 }
399
400 return SDValue();
401 }
402
403 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
404 switch (CC) {
405 default: llvm_unreachable("Unknown fp condition code!");
406 case ISD::SETEQ:
407 case ISD::SETOEQ: return Mips::FCOND_OEQ;
408 case ISD::SETUNE: return Mips::FCOND_UNE;
409 case ISD::SETLT:
410 case ISD::SETOLT: return Mips::FCOND_OLT;
411 case ISD::SETGT:
412 case ISD::SETOGT: return Mips::FCOND_OGT;
413 case ISD::SETLE:
414 case ISD::SETOLE: return Mips::FCOND_OLE;
415 case ISD::SETGE:
416 case ISD::SETOGE: return Mips::FCOND_OGE;
417 case ISD::SETULT: return Mips::FCOND_ULT;
418 case ISD::SETULE: return Mips::FCOND_ULE;
419 case ISD::SETUGT: return Mips::FCOND_UGT;
420 case ISD::SETUGE: return Mips::FCOND_UGE;
421 case ISD::SETUO: return Mips::FCOND_UN;
422 case ISD::SETO: return Mips::FCOND_OR;
423 case ISD::SETNE:
424 case ISD::SETONE: return Mips::FCOND_ONE;
425 case ISD::SETUEQ: return Mips::FCOND_UEQ;
426 }
427 }
428
429
430 // Returns true if condition code has to be inverted.
431 static bool InvertFPCondCode(Mips::CondCode CC) {
432 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
433 return false;
434
435 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
436 return true;
437
438 assert(false && "Illegal Condition Code");
439 return false;
440 }
441
442 // Creates and returns an FPCmp node from a setcc node.
443 // Returns Op if setcc is not a floating point comparison.
444 static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
445 // must be a SETCC node
446 if (Op.getOpcode() != ISD::SETCC)
447 return Op;
448
449 SDValue LHS = Op.getOperand(0);
450
451 if (!LHS.getValueType().isFloatingPoint())
452 return Op;
453
454 SDValue RHS = Op.getOperand(1);
455 DebugLoc dl = Op.getDebugLoc();
456
457 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
458 // node if necessary.
459 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
460
461 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
462 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
463 }
464
465 // Creates and returns a CMovFPT/F node.
466 static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True,
467 SDValue False, DebugLoc DL) {
468 bool invert = InvertFPCondCode((Mips::CondCode)
469 cast<ConstantSDNode>(Cond.getOperand(2))
470 ->getSExtValue());
471
472 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
473 True.getValueType(), True, False, Cond);
474 }
475
476 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG,
477 TargetLowering::DAGCombinerInfo &DCI,
478 const MipsSubtarget* Subtarget) {
479 if (DCI.isBeforeLegalizeOps())
480 return SDValue();
481
482 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0));
483
484 if (Cond.getOpcode() != MipsISD::FPCmp)
485 return SDValue();
486
487 SDValue True = DAG.getConstant(1, MVT::i32);
488 SDValue False = DAG.getConstant(0, MVT::i32);
489
490 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc());
491 }
492
493 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
494 const {
495 SelectionDAG &DAG = DCI.DAG;
496 unsigned opc = N->getOpcode();
497
498 switch (opc) {
499 default: break;
500 case ISD::ADDE:
501 return PerformADDECombine(N, DAG, DCI, Subtarget);
502 case ISD::SUBE:
503 return PerformSUBECombine(N, DAG, DCI, Subtarget);
504 case ISD::SDIVREM:
505 case ISD::UDIVREM:
506 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
507 case ISD::SETCC:
508 return PerformSETCCCombine(N, DAG, DCI, Subtarget);
509 }
510
511 return SDValue();
512 }
513
514 SDValue MipsTargetLowering::
515 LowerOperation(SDValue Op, SelectionDAG &DAG) const
516 {
517 switch (Op.getOpcode())
518 {
519 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
520 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
521 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
522 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
523 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
524 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
525 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
526 case ISD::SELECT: return LowerSELECT(Op, DAG);
527 case ISD::VASTART: return LowerVASTART(Op, DAG);
528 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
529 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
530 }
531 return SDValue();
532 }
533
534 //===----------------------------------------------------------------------===//
535 // Lower helper functions
536 //===----------------------------------------------------------------------===//
537
538 // AddLiveIn - This helper function adds the specified physical register to the
539 // MachineFunction as a live in value. It also creates a corresponding
540 // virtual register for it.
541 static unsigned
542 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
543 {
544 assert(RC->contains(PReg) && "Not the correct regclass!");
545 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
546 MF.getRegInfo().addLiveIn(PReg, VReg);
547 return VReg;
548 }
549
550 // Get fp branch code (not opcode) from condition code.
551 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
552 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
553 return Mips::BRANCH_T;
554
555 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
556 return Mips::BRANCH_F;
557
558 return Mips::BRANCH_INVALID;
559 }
560
561 static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
562 DebugLoc dl,
563 const MipsSubtarget* Subtarget,
564 const TargetInstrInfo *TII,
565 bool isFPCmp, unsigned Opc) {
566 // There is no need to expand CMov instructions if target has
567 // conditional moves.
568 if (Subtarget->hasCondMov())
569 return BB;
570
571 // To "insert" a SELECT_CC instruction, we actually have to insert the
572 // diamond control-flow pattern. The incoming instruction knows the
573 // destination vreg to set, the condition code register to branch on, the
574 // true/false values to select between, and a branch opcode to use.
575 const BasicBlock *LLVM_BB = BB->getBasicBlock();
576 MachineFunction::iterator It = BB;
577 ++It;
578
579 // thisMBB:
580 // ...
581 // TrueVal = ...
582 // setcc r1, r2, r3
583 // bNE r1, r0, copy1MBB
584 // fallthrough --> copy0MBB
585 MachineBasicBlock *thisMBB = BB;
586 MachineFunction *F = BB->getParent();
587 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
588 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
589 F->insert(It, copy0MBB);
590 F->insert(It, sinkMBB);
591
592 // Transfer the remainder of BB and its successor edges to sinkMBB.
593 sinkMBB->splice(sinkMBB->begin(), BB,
594 llvm::next(MachineBasicBlock::iterator(MI)),
595 BB->end());
596 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
597
598 // Next, add the true and fallthrough blocks as its successors.
599 BB->addSuccessor(copy0MBB);
600 BB->addSuccessor(sinkMBB);
601
602 // Emit the right instruction according to the type of the operands compared
603 if (isFPCmp)
604 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
605 else
606 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
607 .addReg(Mips::ZERO).addMBB(sinkMBB);
608
609 // copy0MBB:
610 // %FalseValue = ...
611 // # fallthrough to sinkMBB
612 BB = copy0MBB;
613
614 // Update machine-CFG edges
615 BB->addSuccessor(sinkMBB);
616
617 // sinkMBB:
618 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
619 // ...
620 BB = sinkMBB;
621
622 if (isFPCmp)
623 BuildMI(*BB, BB->begin(), dl,
624 TII->get(Mips::PHI), MI->getOperand(0).getReg())
625 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
626 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
627 else
628 BuildMI(*BB, BB->begin(), dl,
629 TII->get(Mips::PHI), MI->getOperand(0).getReg())
630 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
631 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
632
633 MI->eraseFromParent(); // The pseudo instruction is gone now.
634 return BB;
635 }
636
637 MachineBasicBlock *
638 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
639 MachineBasicBlock *BB) const {
640 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
641 DebugLoc dl = MI->getDebugLoc();
642
643 switch (MI->getOpcode()) {
644 default:
645 assert(false && "Unexpected instr type to insert");
646 return NULL;
647 case Mips::MOVT:
648 case Mips::MOVT_S:
649 case Mips::MOVT_D:
650 return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1F);
651 case Mips::MOVF:
652 case Mips::MOVF_S:
653 case Mips::MOVF_D:
654 return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1T);
655 case Mips::MOVZ_I:
656 case Mips::MOVZ_S:
657 case Mips::MOVZ_D:
658 return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BNE);
659 case Mips::MOVN_I:
660 case Mips::MOVN_S:
661 case Mips::MOVN_D:
662 return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BEQ);
663
664 case Mips::ATOMIC_LOAD_ADD_I8:
665 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
666 case Mips::ATOMIC_LOAD_ADD_I16:
667 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
668 case Mips::ATOMIC_LOAD_ADD_I32:
669 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
670
671 case Mips::ATOMIC_LOAD_AND_I8:
672 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
673 case Mips::ATOMIC_LOAD_AND_I16:
674 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
675 case Mips::ATOMIC_LOAD_AND_I32:
676 return EmitAtomicBinary(MI, BB, 4, Mips::AND);
677
678 case Mips::ATOMIC_LOAD_OR_I8:
679 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
680 case Mips::ATOMIC_LOAD_OR_I16:
681 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
682 case Mips::ATOMIC_LOAD_OR_I32:
683 return EmitAtomicBinary(MI, BB, 4, Mips::OR);
684
685 case Mips::ATOMIC_LOAD_XOR_I8:
686 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
687 case Mips::ATOMIC_LOAD_XOR_I16:
688 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
689 case Mips::ATOMIC_LOAD_XOR_I32:
690 return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
691
692 case Mips::ATOMIC_LOAD_NAND_I8:
693 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
694 case Mips::ATOMIC_LOAD_NAND_I16:
695 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
696 case Mips::ATOMIC_LOAD_NAND_I32:
697 return EmitAtomicBinary(MI, BB, 4, 0, true);
698
699 case Mips::ATOMIC_LOAD_SUB_I8:
700 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
701 case Mips::ATOMIC_LOAD_SUB_I16:
702 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
703 case Mips::ATOMIC_LOAD_SUB_I32:
704 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
705
706 case Mips::ATOMIC_SWAP_I8:
707 return EmitAtomicBinaryPartword(MI, BB, 1, 0);
708 case Mips::ATOMIC_SWAP_I16:
709 return EmitAtomicBinaryPartword(MI, BB, 2, 0);
710 case Mips::ATOMIC_SWAP_I32:
711 return EmitAtomicBinary(MI, BB, 4, 0);
712
713 case Mips::ATOMIC_CMP_SWAP_I8:
714 return EmitAtomicCmpSwapPartword(MI, BB, 1);
715 case Mips::ATOMIC_CMP_SWAP_I16:
716 return EmitAtomicCmpSwapPartword(MI, BB, 2);
717 case Mips::ATOMIC_CMP_SWAP_I32:
718 return EmitAtomicCmpSwap(MI, BB, 4);
719 }
720 }
721
722 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
723 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
724 MachineBasicBlock *
725 MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
726 unsigned Size, unsigned BinOpcode,
727 bool Nand) const {
728 assert(Size == 4 && "Unsupported size for EmitAtomicBinary.");
729
730 MachineFunction *MF = BB->getParent();
731 MachineRegisterInfo &RegInfo = MF->getRegInfo();
732 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
733 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
734 DebugLoc dl = MI->getDebugLoc();
735
736 unsigned Dest = MI->getOperand(0).getReg();
737 unsigned Ptr = MI->getOperand(1).getReg();
738 unsigned Incr = MI->getOperand(2).getReg();
739
740 unsigned Oldval = RegInfo.createVirtualRegister(RC);
741 unsigned Tmp1 = RegInfo.createVirtualRegister(RC);
742 unsigned Tmp2 = RegInfo.createVirtualRegister(RC);
743
744 // insert new blocks after the current block
745 const BasicBlock *LLVM_BB = BB->getBasicBlock();
746 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
747 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
748 MachineFunction::iterator It = BB;
749 ++It;
750 MF->insert(It, loopMBB);
751 MF->insert(It, exitMBB);
752
753 // Transfer the remainder of BB and its successor edges to exitMBB.
754 exitMBB->splice(exitMBB->begin(), BB,
755 llvm::next(MachineBasicBlock::iterator(MI)),
756 BB->end());
757 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
758
759 // thisMBB:
760 // ...
761 // sw incr, fi(sp) // store incr to stack (when BinOpcode == 0)
762 // fallthrough --> loopMBB
763
764 // Note: for atomic.swap (when BinOpcode == 0), storing incr to stack before
765 // the loop and then loading it from stack in block loopMBB is necessary to
766 // prevent MachineLICM pass to hoist "or" instruction out of the block
767 // loopMBB.
768
769 int fi = 0;
770 if (BinOpcode == 0 && !Nand) {
771 // Get or create a temporary stack location.
772 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
773 fi = MipsFI->getAtomicFrameIndex();
774 if (fi == -1) {
775 fi = MF->getFrameInfo()->CreateStackObject(Size, Size, false);
776 MipsFI->setAtomicFrameIndex(fi);
777 }
778
779 BuildMI(BB, dl, TII->get(Mips::SW))
780 .addReg(Incr).addFrameIndex(fi).addImm(0);
781 }
782 BB->addSuccessor(loopMBB);
783
784 // loopMBB:
785 // ll oldval, 0(ptr)
786 // or dest, $0, oldval
787 // <binop> tmp1, oldval, incr
788 // sc tmp1, 0(ptr)
789 // beq tmp1, $0, loopMBB
790 BB = loopMBB;
791 BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Ptr).addImm(0);
792 BuildMI(BB, dl, TII->get(Mips::OR), Dest).addReg(Mips::ZERO).addReg(Oldval);
793 if (Nand) {
794 // and tmp2, oldval, incr
795 // nor tmp1, $0, tmp2
796 BuildMI(BB, dl, TII->get(Mips::AND), Tmp2).addReg(Oldval).addReg(Incr);
797 BuildMI(BB, dl, TII->get(Mips::NOR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2);
798 } else if (BinOpcode) {
799 // <binop> tmp1, oldval, incr
800 BuildMI(BB, dl, TII->get(BinOpcode), Tmp1).addReg(Oldval).addReg(Incr);
801 } else {
802 // lw tmp2, fi(sp) // load incr from stack
803 // or tmp1, $zero, tmp2
804 BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addFrameIndex(fi).addImm(0);
805 BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2);
806 }
807 BuildMI(BB, dl, TII->get(Mips::SC), Tmp1).addReg(Tmp1).addReg(Ptr).addImm(0);
808 BuildMI(BB, dl, TII->get(Mips::BEQ))
809 .addReg(Tmp1).addReg(Mips::ZERO).addMBB(loopMBB);
810 BB->addSuccessor(loopMBB);
811 BB->addSuccessor(exitMBB);
812
813 MI->eraseFromParent(); // The instruction is gone now.
814
815 return BB;
816 }
817
818 MachineBasicBlock *
819 MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
820 MachineBasicBlock *BB,
821 unsigned Size, unsigned BinOpcode,
822 bool Nand) const {
823 assert((Size == 1 || Size == 2) &&
824 "Unsupported size for EmitAtomicBinaryPartial.");
825
826 MachineFunction *MF = BB->getParent();
827 MachineRegisterInfo &RegInfo = MF->getRegInfo();
828 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
829 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
830 DebugLoc dl = MI->getDebugLoc();
831
832 unsigned Dest = MI->getOperand(0).getReg();
833 unsigned Ptr = MI->getOperand(1).getReg();
834 unsigned Incr = MI->getOperand(2).getReg();
835
836 unsigned Addr = RegInfo.createVirtualRegister(RC);
837 unsigned Shift = RegInfo.createVirtualRegister(RC);
838 unsigned Mask = RegInfo.createVirtualRegister(RC);
839 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
840 unsigned Newval = RegInfo.createVirtualRegister(RC);
841 unsigned Oldval = RegInfo.createVirtualRegister(RC);
842 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
843 unsigned Tmp1 = RegInfo.createVirtualRegister(RC);
844 unsigned Tmp2 = RegInfo.createVirtualRegister(RC);
845 unsigned Tmp3 = RegInfo.createVirtualRegister(RC);
846 unsigned Tmp4 = RegInfo.createVirtualRegister(RC);
847 unsigned Tmp5 = RegInfo.createVirtualRegister(RC);
848 unsigned Tmp6 = RegInfo.createVirtualRegister(RC);
849 unsigned Tmp7 = RegInfo.createVirtualRegister(RC);
850 unsigned Tmp8 = RegInfo.createVirtualRegister(RC);
851 unsigned Tmp9 = RegInfo.createVirtualRegister(RC);
852 unsigned Tmp10 = RegInfo.createVirtualRegister(RC);
853 unsigned Tmp11 = RegInfo.createVirtualRegister(RC);
854 unsigned Tmp12 = RegInfo.createVirtualRegister(RC);
855
856 // insert new blocks after the current block
857 const BasicBlock *LLVM_BB = BB->getBasicBlock();
858 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
859 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
860 MachineFunction::iterator It = BB;
861 ++It;
862 MF->insert(It, loopMBB);
863 MF->insert(It, exitMBB);
864
865 // Transfer the remainder of BB and its successor edges to exitMBB.
866 exitMBB->splice(exitMBB->begin(), BB,
867 llvm::next(MachineBasicBlock::iterator(MI)),
868 BB->end());
869 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
870
871 // thisMBB:
872 // addiu tmp1,$0,-4 # 0xfffffffc
873 // and addr,ptr,tmp1
874 // andi tmp2,ptr,3
875 // sll shift,tmp2,3
876 // ori tmp3,$0,255 # 0xff
877 // sll mask,tmp3,shift
878 // nor mask2,$0,mask
879 // andi tmp4,incr,255
880 // sll incr2,tmp4,shift
881 // sw incr2, fi(sp) // store incr2 to stack (when BinOpcode == 0)
882
883 // Note: for atomic.swap (when BinOpcode == 0), storing incr2 to stack before
884 // the loop and then loading it from stack in block loopMBB is necessary to
885 // prevent MachineLICM pass to hoist "or" instruction out of the block
886 // loopMBB.
887
888 int64_t MaskImm = (Size == 1) ? 255 : 65535;
889 BuildMI(BB, dl, TII->get(Mips::ADDiu), Tmp1).addReg(Mips::ZERO).addImm(-4);
890 BuildMI(BB, dl, TII->get(Mips::AND), Addr).addReg(Ptr).addReg(Tmp1);
891 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp2).addReg(Ptr).addImm(3);
892 BuildMI(BB, dl, TII->get(Mips::SLL), Shift).addReg(Tmp2).addImm(3);
893 BuildMI(BB, dl, TII->get(Mips::ORi), Tmp3).addReg(Mips::ZERO).addImm(MaskImm);
894 BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(Tmp3).addReg(Shift);
895 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
896 if (BinOpcode != Mips::SUBu) {
897 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Incr).addImm(MaskImm);
898 BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp4).addReg(Shift);
899 } else {
900 BuildMI(BB, dl, TII->get(Mips::SUBu), Tmp4).addReg(Mips::ZERO).addReg(Incr);
901 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp5).addReg(Tmp4).addImm(MaskImm);
902 BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp5).addReg(Shift);
903 }
904
905 int fi = 0;
906 if (BinOpcode == 0 && !Nand) {
907 // Get or create a temporary stack location.
908 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
909 fi = MipsFI->getAtomicFrameIndex();
910 if (fi == -1) {
911 fi = MF->getFrameInfo()->CreateStackObject(Size, Size, false);
912 MipsFI->setAtomicFrameIndex(fi);
913 }
914
915 BuildMI(BB, dl, TII->get(Mips::SW))
916 .addReg(Incr2).addFrameIndex(fi).addImm(0);
917 }
918 BB->addSuccessor(loopMBB);
919
920 // loopMBB:
921 // ll oldval,0(addr)
922 // binop tmp7,oldval,incr2
923 // and newval,tmp7,mask
924 // and tmp8,oldval,mask2
925 // or tmp9,tmp8,newval
926 // sc tmp9,0(addr)
927 // beq tmp9,$0,loopMBB
928 BB = loopMBB;
929 BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Addr).addImm(0);
930 if (Nand) {
931 // and tmp6, oldval, incr2
932 // nor tmp7, $0, tmp6
933 BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval).addReg(Incr2);
934 BuildMI(BB, dl, TII->get(Mips::NOR), Tmp7).addReg(Mips::ZERO).addReg(Tmp6);
935 } else if (BinOpcode == Mips::SUBu) {
936 // addu tmp7, oldval, incr2
937 BuildMI(BB, dl, TII->get(Mips::ADDu), Tmp7).addReg(Oldval).addReg(Incr2);
938 } else if (BinOpcode) {
939 // <binop> tmp7, oldval, incr2
940 BuildMI(BB, dl, TII->get(BinOpcode), Tmp7).addReg(Oldval).addReg(Incr2);
941 } else {
942 // lw tmp6, fi(sp) // load incr2 from stack
943 // or tmp7, $zero, tmp6
944 BuildMI(BB, dl, TII->get(Mips::LW), Tmp6).addFrameIndex(fi).addImm(0);
945 BuildMI(BB, dl, TII->get(Mips::OR), Tmp7).addReg(Mips::ZERO).addReg(Tmp6);
946 }
947 BuildMI(BB, dl, TII->get(Mips::AND), Newval).addReg(Tmp7).addReg(Mask);
948 BuildMI(BB, dl, TII->get(Mips::AND), Tmp8).addReg(Oldval).addReg(Mask2);
949 BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Newval);
950 BuildMI(BB, dl, TII->get(Mips::SC), Tmp9).addReg(Tmp9).addReg(Addr).addImm(0);
951 BuildMI(BB, dl, TII->get(Mips::BEQ))
952 .addReg(Tmp9).addReg(Mips::ZERO).addMBB(loopMBB);
953 BB->addSuccessor(loopMBB);
954 BB->addSuccessor(exitMBB);
955
956 // exitMBB:
957 // and tmp10,oldval,mask
958 // srl tmp11,tmp10,shift
959 // sll tmp12,tmp11,24
960 // sra dest,tmp12,24
961 BB = exitMBB;
962 int64_t ShiftImm = (Size == 1) ? 24 : 16;
963 // reverse order
964 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRA), Dest)
965 .addReg(Tmp12).addImm(ShiftImm);
966 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SLL), Tmp12)
967 .addReg(Tmp11).addImm(ShiftImm);
968 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRL), Tmp11)
969 .addReg(Tmp10).addReg(Shift);
970 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::AND), Tmp10)
971 .addReg(Oldval).addReg(Mask);
972
973 MI->eraseFromParent(); // The instruction is gone now.
974
975 return BB;
976 }
977
978 MachineBasicBlock *
979 MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
980 MachineBasicBlock *BB,
981 unsigned Size) const {
982 assert(Size == 4 && "Unsupported size for EmitAtomicCmpSwap.");
983
984 MachineFunction *MF = BB->getParent();
985 MachineRegisterInfo &RegInfo = MF->getRegInfo();
986 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
987 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
988 DebugLoc dl = MI->getDebugLoc();
989
990 unsigned Dest = MI->getOperand(0).getReg();
991 unsigned Ptr = MI->getOperand(1).getReg();
992 unsigned Oldval = MI->getOperand(2).getReg();
993 unsigned Newval = MI->getOperand(3).getReg();
994
995 unsigned Tmp1 = RegInfo.createVirtualRegister(RC);
996 unsigned Tmp2 = RegInfo.createVirtualRegister(RC);
997
998 // insert new blocks after the current block
999 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1000 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1001 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1002 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1003 MachineFunction::iterator It = BB;
1004 ++It;
1005 MF->insert(It, loop1MBB);
1006 MF->insert(It, loop2MBB);
1007 MF->insert(It, exitMBB);
1008
1009 // Transfer the remainder of BB and its successor edges to exitMBB.
1010 exitMBB->splice(exitMBB->begin(), BB,
1011 llvm::next(MachineBasicBlock::iterator(MI)),
1012 BB->end());
1013 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1014
1015 // Get or create a temporary stack location.
1016 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
1017 int fi = MipsFI->getAtomicFrameIndex();
1018 if (fi == -1) {
1019 fi = MF->getFrameInfo()->CreateStackObject(Size, Size, false);
1020 MipsFI->setAtomicFrameIndex(fi);
1021 }
1022
1023 // thisMBB:
1024 // ...
1025 // sw newval, fi(sp) // store newval to stack
1026 // fallthrough --> loop1MBB
1027
1028 // Note: storing newval to stack before the loop and then loading it from
1029 // stack in block loop2MBB is necessary to prevent MachineLICM pass to
1030 // hoist "or" instruction out of the block loop2MBB.
1031
1032 BuildMI(BB, dl, TII->get(Mips::SW))
1033 .addReg(Newval).addFrameIndex(fi).addImm(0);
1034 BB->addSuccessor(loop1MBB);
1035
1036 // loop1MBB:
1037 // ll dest, 0(ptr)
1038 // bne dest, oldval, exitMBB
1039 BB = loop1MBB;
1040 BuildMI(BB, dl, TII->get(Mips::LL), Dest).addReg(Ptr).addImm(0);
1041 BuildMI(BB, dl, TII->get(Mips::BNE))
1042 .addReg(Dest).addReg(Oldval).addMBB(exitMBB);
1043 BB->addSuccessor(exitMBB);
1044 BB->addSuccessor(loop2MBB);
1045
1046 // loop2MBB:
1047 // lw tmp2, fi(sp) // load newval from stack
1048 // or tmp1, $0, tmp2
1049 // sc tmp1, 0(ptr)
1050 // beq tmp1, $0, loop1MBB
1051 BB = loop2MBB;
1052 BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addFrameIndex(fi).addImm(0);
1053 BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2);
1054 BuildMI(BB, dl, TII->get(Mips::SC), Tmp1).addReg(Tmp1).addReg(Ptr).addImm(0);
1055 BuildMI(BB, dl, TII->get(Mips::BEQ))
1056 .addReg(Tmp1).addReg(Mips::ZERO).addMBB(loop1MBB);
1057 BB->addSuccessor(loop1MBB);
1058 BB->addSuccessor(exitMBB);
1059
1060 MI->eraseFromParent(); // The instruction is gone now.
1061
1062 return BB;
1063 }
1064
1065 MachineBasicBlock *
1066 MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
1067 MachineBasicBlock *BB,
1068 unsigned Size) const {
1069 assert((Size == 1 || Size == 2) &&
1070 "Unsupported size for EmitAtomicCmpSwapPartial.");
1071
1072 MachineFunction *MF = BB->getParent();
1073 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1074 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1075 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1076 DebugLoc dl = MI->getDebugLoc();
1077
1078 unsigned Dest = MI->getOperand(0).getReg();
1079 unsigned Ptr = MI->getOperand(1).getReg();
1080 unsigned Oldval = MI->getOperand(2).getReg();
1081 unsigned Newval = MI->getOperand(3).getReg();
1082
1083 unsigned Addr = RegInfo.createVirtualRegister(RC);
1084 unsigned Shift = RegInfo.createVirtualRegister(RC);
1085 unsigned Mask = RegInfo.createVirtualRegister(RC);
1086 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1087 unsigned Oldval2 = RegInfo.createVirtualRegister(RC);
1088 unsigned Oldval3 = RegInfo.createVirtualRegister(RC);
1089 unsigned Oldval4 = RegInfo.createVirtualRegister(RC);
1090 unsigned Newval2 = RegInfo.createVirtualRegister(RC);
1091 unsigned Tmp1 = RegInfo.createVirtualRegister(RC);
1092 unsigned Tmp2 = RegInfo.createVirtualRegister(RC);
1093 unsigned Tmp3 = RegInfo.createVirtualRegister(RC);
1094 unsigned Tmp4 = RegInfo.createVirtualRegister(RC);
1095 unsigned Tmp5 = RegInfo.createVirtualRegister(RC);
1096 unsigned Tmp6 = RegInfo.createVirtualRegister(RC);
1097 unsigned Tmp7 = RegInfo.createVirtualRegister(RC);
1098 unsigned Tmp8 = RegInfo.createVirtualRegister(RC);
1099 unsigned Tmp9 = RegInfo.createVirtualRegister(RC);
1100
1101 // insert new blocks after the current block
1102 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1103 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1104 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1105 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1106 MachineFunction::iterator It = BB;
1107 ++It;
1108 MF->insert(It, loop1MBB);
1109 MF->insert(It, loop2MBB);
1110 MF->insert(It, exitMBB);
1111
1112 // Transfer the remainder of BB and its successor edges to exitMBB.
1113 exitMBB->splice(exitMBB->begin(), BB,
1114 llvm::next(MachineBasicBlock::iterator(MI)),
1115 BB->end());
1116 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1117
1118 // thisMBB:
1119 // addiu tmp1,$0,-4 # 0xfffffffc
1120 // and addr,ptr,tmp1
1121 // andi tmp2,ptr,3
1122 // sll shift,tmp2,3
1123 // ori tmp3,$0,255 # 0xff
1124 // sll mask,tmp3,shift
1125 // nor mask2,$0,mask
1126 // andi tmp4,oldval,255
1127 // sll oldval2,tmp4,shift
1128 // andi tmp5,newval,255
1129 // sll newval2,tmp5,shift
1130 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1131 BuildMI(BB, dl, TII->get(Mips::ADDiu), Tmp1).addReg(Mips::ZERO).addImm(-4);
1132 BuildMI(BB, dl, TII->get(Mips::AND), Addr).addReg(Ptr).addReg(Tmp1);
1133 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp2).addReg(Ptr).addImm(3);
1134 BuildMI(BB, dl, TII->get(Mips::SLL), Shift).addReg(Tmp2).addImm(3);
1135 BuildMI(BB, dl, TII->get(Mips::ORi), Tmp3).addReg(Mips::ZERO).addImm(MaskImm);
1136 BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(Tmp3).addReg(Shift);
1137 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1138 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Oldval).addImm(MaskImm);
1139 BuildMI(BB, dl, TII->get(Mips::SLL), Oldval2).addReg(Tmp4).addReg(Shift);
1140 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp5).addReg(Newval).addImm(MaskImm);
1141 BuildMI(BB, dl, TII->get(Mips::SLL), Newval2).addReg(Tmp5).addReg(Shift);
1142 BB->addSuccessor(loop1MBB);
1143
1144 // loop1MBB:
1145 // ll oldval3,0(addr)
1146 // and oldval4,oldval3,mask
1147 // bne oldval4,oldval2,exitMBB
1148 BB = loop1MBB;
1149 BuildMI(BB, dl, TII->get(Mips::LL), Oldval3).addReg(Addr).addImm(0);
1150 BuildMI(BB, dl, TII->get(Mips::AND), Oldval4).addReg(Oldval3).addReg(Mask);
1151 BuildMI(BB, dl, TII->get(Mips::BNE))
1152 .addReg(Oldval4).addReg(Oldval2).addMBB(exitMBB);
1153 BB->addSuccessor(exitMBB);
1154 BB->addSuccessor(loop2MBB);
1155
1156 // loop2MBB:
1157 // and tmp6,oldval3,mask2
1158 // or tmp7,tmp6,newval2
1159 // sc tmp7,0(addr)
1160 // beq tmp7,$0,loop1MBB
1161 BB = loop2MBB;
1162 BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval3).addReg(Mask2);
1163 BuildMI(BB, dl, TII->get(Mips::OR), Tmp7).addReg(Tmp6).addReg(Newval2);
1164 BuildMI(BB, dl, TII->get(Mips::SC), Tmp7)
1165 .addReg(Tmp7).addReg(Addr).addImm(0);
1166 BuildMI(BB, dl, TII->get(Mips::BEQ))
1167 .addReg(Tmp7).addReg(Mips::ZERO).addMBB(loop1MBB);
1168 BB->addSuccessor(loop1MBB);
1169 BB->addSuccessor(exitMBB);
1170
1171 // exitMBB:
1172 // srl tmp8,oldval4,shift
1173 // sll tmp9,tmp8,24
1174 // sra dest,tmp9,24
1175 BB = exitMBB;
1176 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1177 // reverse order
1178 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRA), Dest)
1179 .addReg(Tmp9).addImm(ShiftImm);
1180 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SLL), Tmp9)
1181 .addReg(Tmp8).addImm(ShiftImm);
1182 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRL), Tmp8)
1183 .addReg(Oldval4).addReg(Shift);
1184
1185 MI->eraseFromParent(); // The instruction is gone now.
1186
1187 return BB;
1188 }
1189
1190 //===----------------------------------------------------------------------===//
1191 // Misc Lower Operation implementation
1192 //===----------------------------------------------------------------------===//
1193 SDValue MipsTargetLowering::
1194 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
1195 {
1196 MachineFunction &MF = DAG.getMachineFunction();
1197 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1198
1199 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >=
1200 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() &&
1201 "Cannot lower if the alignment of the allocated space is larger than \
1202 that of the stack.");
1203
1204 SDValue Chain = Op.getOperand(0);
1205 SDValue Size = Op.getOperand(1);
1206 DebugLoc dl = Op.getDebugLoc();
1207
1208 // Get a reference from Mips stack pointer
1209 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
1210
1211 // Subtract the dynamic size from the actual stack size to
1212 // obtain the new stack size.
1213 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
1214
1215 // The Sub result contains the new stack start address, so it
1216 // must be placed in the stack pointer register.
1217 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub,
1218 SDValue());
1219
1220 // This node always has two return values: a new stack pointer
1221 // value and a chain
1222 SDVTList VTLs = DAG.getVTList(MVT::i32, MVT::Other);
1223 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy());
1224 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) };
1225
1226 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3);
1227 }
1228
1229 SDValue MipsTargetLowering::
1230 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
1231 {
1232 // The first operand is the chain, the second is the condition, the third is
1233 // the block to branch to if the condition is true.
1234 SDValue Chain = Op.getOperand(0);
1235 SDValue Dest = Op.getOperand(2);
1236 DebugLoc dl = Op.getDebugLoc();
1237
1238 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
1239
1240 // Return if flag is not set by a floating point comparison.
1241 if (CondRes.getOpcode() != MipsISD::FPCmp)
1242 return Op;
1243
1244 SDValue CCNode = CondRes.getOperand(2);
1245 Mips::CondCode CC =
1246 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1247 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
1248
1249 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
1250 Dest, CondRes);
1251 }
1252
1253 SDValue MipsTargetLowering::
1254 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
1255 {
1256 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
1257
1258 // Return if flag is not set by a floating point comparison.
1259 if (Cond.getOpcode() != MipsISD::FPCmp)
1260 return Op;
1261
1262 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1263 Op.getDebugLoc());
1264 }
1265
1266 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
1267 SelectionDAG &DAG) const {
1268 // FIXME there isn't actually debug info here
1269 DebugLoc dl = Op.getDebugLoc();
1270 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1271
1272 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
1273 SDVTList VTs = DAG.getVTList(MVT::i32);
1274
1275 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
1276
1277 // %gp_rel relocation
1278 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1279 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1280 MipsII::MO_GPREL);
1281 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
1282 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1283 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
1284 }
1285 // %hi/%lo relocation
1286 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1287 MipsII::MO_ABS_HI);
1288 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1289 MipsII::MO_ABS_LO);
1290 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
1291 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
1292 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1293 }
1294
1295 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1296 MipsII::MO_GOT);
1297 GA = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, GA);
1298 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
1299 DAG.getEntryNode(), GA, MachinePointerInfo(),
1300 false, false, 0);
1301 // On functions and global targets not internal linked only
1302 // a load from got/GP is necessary for PIC to work.
1303 if (!GV->hasInternalLinkage() &&
1304 (!GV->hasLocalLinkage() || isa<Function>(GV)))
1305 return ResNode;
1306 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1307 MipsII::MO_ABS_LO);
1308 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
1309 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
1310 }
1311
1312 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
1313 SelectionDAG &DAG) const {
1314 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1315 // FIXME there isn't actually debug info here
1316 DebugLoc dl = Op.getDebugLoc();
1317
1318 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
1319 // %hi/%lo relocation
1320 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true,
1321 MipsII::MO_ABS_HI);
1322 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true,
1323 MipsII::MO_ABS_LO);
1324 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
1325 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
1326 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
1327 }
1328
1329 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true,
1330 MipsII::MO_GOT);
1331 BAGOTOffset = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, BAGOTOffset);
1332 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true,
1333 MipsII::MO_ABS_LO);
1334 SDValue Load = DAG.getLoad(MVT::i32, dl,
1335 DAG.getEntryNode(), BAGOTOffset,
1336 MachinePointerInfo(), false, false, 0);
1337 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset);
1338 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
1339 }
1340
1341 SDValue MipsTargetLowering::
1342 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1343 {
1344 // If the relocation model is PIC, use the General Dynamic TLS Model,
1345 // otherwise use the Initial Exec or Local Exec TLS Model.
1346 // TODO: implement Local Dynamic TLS model
1347
1348 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1349 DebugLoc dl = GA->getDebugLoc();
1350 const GlobalValue *GV = GA->getGlobal();
1351 EVT PtrVT = getPointerTy();
1352
1353 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1354 // General Dynamic TLS Model
1355 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32,
1356 0, MipsII::MO_TLSGD);
1357 SDValue Tlsgd = DAG.getNode(MipsISD::TlsGd, dl, MVT::i32, TGA);
1358 SDValue GP = DAG.getRegister(Mips::GP, MVT::i32);
1359 SDValue Argument = DAG.getNode(ISD::ADD, dl, MVT::i32, GP, Tlsgd);
1360
1361 ArgListTy Args;
1362 ArgListEntry Entry;
1363 Entry.Node = Argument;
1364 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1365 Args.push_back(Entry);
1366 std::pair<SDValue, SDValue> CallResult =
1367 LowerCallTo(DAG.getEntryNode(),
1368 (const Type *) Type::getInt32Ty(*DAG.getContext()),
1369 false, false, false, false, 0, CallingConv::C, false, true,
1370 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG,
1371 dl);
1372
1373 return CallResult.first;
1374 }
1375
1376 SDValue Offset;
1377 if (GV->isDeclaration()) {
1378 // Initial Exec TLS Model
1379 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1380 MipsII::MO_GOTTPREL);
1381 Offset = DAG.getLoad(MVT::i32, dl,
1382 DAG.getEntryNode(), TGA, MachinePointerInfo(),
1383 false, false, 0);
1384 } else {
1385 // Local Exec TLS Model
1386 SDVTList VTs = DAG.getVTList(MVT::i32);
1387 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1388 MipsII::MO_TPREL_HI);
1389 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1390 MipsII::MO_TPREL_LO);
1391 SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1);
1392 SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo);
1393 Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
1394 }
1395
1396 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
1397 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1398 }
1399
1400 SDValue MipsTargetLowering::
1401 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1402 {
1403 SDValue ResNode;
1404 SDValue HiPart;
1405 // FIXME there isn't actually debug info here
1406 DebugLoc dl = Op.getDebugLoc();
1407 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1408 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI;
1409
1410 EVT PtrVT = Op.getValueType();
1411 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1412
1413 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
1414
1415 if (!IsPIC) {
1416 SDValue Ops[] = { JTI };
1417 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
1418 } else {// Emit Load from Global Pointer
1419 JTI = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, JTI);
1420 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI,
1421 MachinePointerInfo(),
1422 false, false, 0);
1423 }
1424
1425 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1426 MipsII::MO_ABS_LO);
1427 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo);
1428 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1429
1430 return ResNode;
1431 }
1432
1433 SDValue MipsTargetLowering::
1434 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1435 {
1436 SDValue ResNode;
1437 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1438 const Constant *C = N->getConstVal();
1439 // FIXME there isn't actually debug info here
1440 DebugLoc dl = Op.getDebugLoc();
1441
1442 // gp_rel relocation
1443 // FIXME: we should reference the constant pool using small data sections,
1444 // but the asm printer currently doesn't support this feature without
1445 // hacking it. This feature should come soon so we can uncomment the
1446 // stuff below.
1447 //if (IsInSmallSection(C->getType())) {
1448 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1449 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1450 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
1451
1452 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
1453 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1454 N->getOffset(), MipsII::MO_ABS_HI);
1455 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1456 N->getOffset(), MipsII::MO_ABS_LO);
1457 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
1458 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
1459 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1460 } else {
1461 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1462 N->getOffset(), MipsII::MO_GOT);
1463 CP = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, CP);
1464 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
1465 CP, MachinePointerInfo::getConstantPool(),
1466 false, false, 0);
1467 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1468 N->getOffset(), MipsII::MO_ABS_LO);
1469 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
1470 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
1471 }
1472
1473 return ResNode;
1474 }
1475
1476 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1477 MachineFunction &MF = DAG.getMachineFunction();
1478 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1479
1480 DebugLoc dl = Op.getDebugLoc();
1481 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1482 getPointerTy());
1483
1484 // vastart just stores the address of the VarArgsFrameIndex slot into the
1485 // memory location argument.
1486 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1487 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
1488 MachinePointerInfo(SV),
1489 false, false, 0);
1490 }
1491
1492 static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG) {
1493 // FIXME: Use ext/ins instructions if target architecture is Mips32r2.
1494 DebugLoc dl = Op.getDebugLoc();
1495 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0));
1496 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1));
1497 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op0,
1498 DAG.getConstant(0x7fffffff, MVT::i32));
1499 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op1,
1500 DAG.getConstant(0x80000000, MVT::i32));
1501 SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1);
1502 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Result);
1503 }
1504
1505 static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) {
1506 // FIXME:
1507 // Use ext/ins instructions if target architecture is Mips32r2.
1508 // Eliminate redundant mfc1 and mtc1 instructions.
1509 unsigned LoIdx = 0, HiIdx = 1;
1510
1511 if (!isLittle)
1512 std::swap(LoIdx, HiIdx);
1513
1514 DebugLoc dl = Op.getDebugLoc();
1515 SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1516 Op.getOperand(0),
1517 DAG.getConstant(LoIdx, MVT::i32));
1518 SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1519 Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32));
1520 SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1521 Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32));
1522 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0,
1523 DAG.getConstant(0x7fffffff, MVT::i32));
1524 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1,
1525 DAG.getConstant(0x80000000, MVT::i32));
1526 SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1);
1527
1528 if (!isLittle)
1529 std::swap(Word0, Word1);
1530
1531 return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1);
1532 }
1533
1534 SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
1535 const {
1536 EVT Ty = Op.getValueType();
1537
1538 assert(Ty == MVT::f32 || Ty == MVT::f64);
1539
1540 if (Ty == MVT::f32)
1541 return LowerFCOPYSIGN32(Op, DAG);
1542 else
1543 return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle());
1544 }
1545
1546 SDValue MipsTargetLowering::
1547 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1548 // check the depth
1549 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1550 "Frame address can only be determined for current frame.");
1551
1552 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1553 MFI->setFrameAddressIsTaken(true);
1554 EVT VT = Op.getValueType();
1555 DebugLoc dl = Op.getDebugLoc();
1556 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Mips::FP, VT);
1557 return FrameAddr;
1558 }
1559
1560 //===----------------------------------------------------------------------===//
1561 // Calling Convention Implementation
1562 //===----------------------------------------------------------------------===//
1563
1564 #include "MipsGenCallingConv.inc"
1565
1566 //===----------------------------------------------------------------------===//
1567 // TODO: Implement a generic logic using tblgen that can support this.
1568 // Mips O32 ABI rules:
1569 // ---
1570 // i32 - Passed in A0, A1, A2, A3 and stack
1571 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
1572 // an argument. Otherwise, passed in A1, A2, A3 and stack.
1573 // f64 - Only passed in two aliased f32 registers if no int reg has been used
1574 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
1575 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
1576 // go to stack.
1577 //
1578 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
1579 //===----------------------------------------------------------------------===//
1580
1581 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
1582 MVT LocVT, CCValAssign::LocInfo LocInfo,
1583 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1584
1585 static const unsigned IntRegsSize=4, FloatRegsSize=2;
1586
1587 static const unsigned IntRegs[] = {
1588 Mips::A0, Mips::A1, Mips::A2, Mips::A3
1589 };
1590 static const unsigned F32Regs[] = {
1591 Mips::F12, Mips::F14
1592 };
1593 static const unsigned F64Regs[] = {
1594 Mips::D6, Mips::D7
1595 };
1596
1597 // ByVal Args
1598 if (ArgFlags.isByVal()) {
1599 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo,
1600 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags);
1601 unsigned NextReg = (State.getNextStackOffset() + 3) / 4;
1602 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize);
1603 r < std::min(IntRegsSize, NextReg); ++r)
1604 State.AllocateReg(IntRegs[r]);
1605 return false;
1606 }
1607
1608 // Promote i8 and i16
1609 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
1610 LocVT = MVT::i32;
1611 if (ArgFlags.isSExt())
1612 LocInfo = CCValAssign::SExt;
1613 else if (ArgFlags.isZExt())
1614 LocInfo = CCValAssign::ZExt;
1615 else
1616 LocInfo = CCValAssign::AExt;
1617 }
1618
1619 unsigned Reg;
1620
1621 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
1622 // is true: function is vararg, argument is 3rd or higher, there is previous
1623 // argument which is not f32 or f64.
1624 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
1625 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
1626 unsigned OrigAlign = ArgFlags.getOrigAlign();
1627 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
1628
1629 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
1630 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1631 // If this is the first part of an i64 arg,
1632 // the allocated register must be either A0 or A2.
1633 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
1634 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1635 LocVT = MVT::i32;
1636 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
1637 // Allocate int register and shadow next int register. If first
1638 // available register is Mips::A1 or Mips::A3, shadow it too.
1639 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1640 if (Reg == Mips::A1 || Reg == Mips::A3)
1641 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1642 State.AllocateReg(IntRegs, IntRegsSize);
1643 LocVT = MVT::i32;
1644 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
1645 // we are guaranteed to find an available float register
1646 if (ValVT == MVT::f32) {
1647 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
1648 // Shadow int register
1649 State.AllocateReg(IntRegs, IntRegsSize);
1650 } else {
1651 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
1652 // Shadow int registers
1653 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
1654 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
1655 State.AllocateReg(IntRegs, IntRegsSize);
1656 State.AllocateReg(IntRegs, IntRegsSize);
1657 }
1658 } else
1659 llvm_unreachable("Cannot handle this ValVT.");
1660
1661 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
1662 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign);
1663
1664 if (!Reg)
1665 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
1666 else
1667 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1668
1669 return false; // CC must always match
1670 }
1671
1672 //===----------------------------------------------------------------------===//
1673 // Call Calling Convention Implementation
1674 //===----------------------------------------------------------------------===//
1675
1676 static const unsigned O32IntRegsSize = 4;
1677
1678 static const unsigned O32IntRegs[] = {
1679 Mips::A0, Mips::A1, Mips::A2, Mips::A3
1680 };
1681
1682 // Write ByVal Arg to arg registers and stack.
1683 static void
1684 WriteByValArg(SDValue& Chain, DebugLoc dl,
1685 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass,
1686 SmallVector<SDValue, 8>& MemOpChains, int& LastFI,
1687 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
1688 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
1689 MVT PtrType) {
1690 unsigned FirstWord = VA.getLocMemOffset() / 4;
1691 unsigned NumWords = (Flags.getByValSize() + 3) / 4;
1692 unsigned LastWord = FirstWord + NumWords;
1693 unsigned CurWord;
1694
1695 // copy the first 4 words of byval arg to registers A0 - A3
1696 for (CurWord = FirstWord; CurWord < std::min(LastWord, O32IntRegsSize);
1697 ++CurWord) {
1698 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
1699 DAG.getConstant((CurWord - FirstWord) * 4,
1700 MVT::i32));
1701 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
1702 MachinePointerInfo(),
1703 false, false, 0);
1704 MemOpChains.push_back(LoadVal.getValue(1));
1705 unsigned DstReg = O32IntRegs[CurWord];
1706 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
1707 }
1708
1709 // copy remaining part of byval arg to stack.
1710 if (CurWord < LastWord) {
1711 unsigned SizeInBytes = (LastWord - CurWord) * 4;
1712 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
1713 DAG.getConstant((CurWord - FirstWord) * 4,
1714 MVT::i32));
1715 LastFI = MFI->CreateFixedObject(SizeInBytes, CurWord * 4, true);
1716 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType);
1717 Chain = DAG.getMemcpy(Chain, dl, Dst, Src,
1718 DAG.getConstant(SizeInBytes, MVT::i32),
1719 /*Align*/4,
1720 /*isVolatile=*/false, /*AlwaysInline=*/false,
1721 MachinePointerInfo(0), MachinePointerInfo(0));
1722 MemOpChains.push_back(Chain);
1723 }
1724 }
1725
1726 /// LowerCall - functions arguments are copied from virtual regs to
1727 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
1728 /// TODO: isTailCall.
1729 SDValue
1730 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1731 CallingConv::ID CallConv, bool isVarArg,
1732 bool &isTailCall,
1733 const SmallVectorImpl<ISD::OutputArg> &Outs,
1734 const SmallVectorImpl<SDValue> &OutVals,
1735 const SmallVectorImpl<ISD::InputArg> &Ins,
1736 DebugLoc dl, SelectionDAG &DAG,
1737 SmallVectorImpl<SDValue> &InVals) const {
1738 // MIPs target does not yet support tail call optimization.
1739 isTailCall = false;
1740
1741 MachineFunction &MF = DAG.getMachineFunction();
1742 MachineFrameInfo *MFI = MF.getFrameInfo();
1743 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
1744 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1745 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1746
1747 // Analyze operands of the call, assigning locations to each operand.
1748 SmallVector<CCValAssign, 16> ArgLocs;
1749 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1750 getTargetMachine(), ArgLocs, *DAG.getContext());
1751
1752 if (Subtarget->isABI_O32())
1753 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
1754 else
1755 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
1756
1757 // Get a count of how many bytes are to be pushed on the stack.
1758 unsigned NextStackOffset = CCInfo.getNextStackOffset();
1759
1760 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NextStackOffset,
1761 true));
1762
1763 // If this is the first call, create a stack frame object that points to
1764 // a location to which .cprestore saves $gp.
1765 if (IsPIC && !MipsFI->getGPFI())
1766 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true));
1767
1768 // Get the frame index of the stack frame object that points to the location
1769 // of dynamically allocated area on the stack.
1770 int DynAllocFI = MipsFI->getDynAllocFI();
1771
1772 // Update size of the maximum argument space.
1773 // For O32, a minimum of four words (16 bytes) of argument space is
1774 // allocated.
1775 if (Subtarget->isABI_O32())
1776 NextStackOffset = std::max(NextStackOffset, (unsigned)16);
1777
1778 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize();
1779
1780 if (MaxCallFrameSize < NextStackOffset) {
1781 MipsFI->setMaxCallFrameSize(NextStackOffset);
1782
1783 // Set the offsets relative to $sp of the $gp restore slot and dynamically
1784 // allocated stack space. These offsets must be aligned to a boundary
1785 // determined by the stack alignment of the ABI.
1786 unsigned StackAlignment = TFL->getStackAlignment();
1787 NextStackOffset = (NextStackOffset + StackAlignment - 1) /
1788 StackAlignment * StackAlignment;
1789
1790 if (IsPIC)
1791 MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset);
1792
1793 MFI->setObjectOffset(DynAllocFI, NextStackOffset);
1794 }
1795
1796 // With EABI is it possible to have 16 args on registers.
1797 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
1798 SmallVector<SDValue, 8> MemOpChains;
1799
1800 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0;
1801
1802 // Walk the register/memloc assignments, inserting copies/loads.
1803 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1804 SDValue Arg = OutVals[i];
1805 CCValAssign &VA = ArgLocs[i];
1806
1807 // Promote the value if needed.
1808 switch (VA.getLocInfo()) {
1809 default: llvm_unreachable("Unknown loc info!");
1810 case CCValAssign::Full:
1811 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
1812 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
1813 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
1814 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
1815 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1816 Arg, DAG.getConstant(0, MVT::i32));
1817 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1818 Arg, DAG.getConstant(1, MVT::i32));
1819 if (!Subtarget->isLittle())
1820 std::swap(Lo, Hi);
1821 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
1822 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
1823 continue;
1824 }
1825 }
1826 break;
1827 case CCValAssign::SExt:
1828 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1829 break;
1830 case CCValAssign::ZExt:
1831 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1832 break;
1833 case CCValAssign::AExt:
1834 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1835 break;
1836 }
1837
1838 // Arguments that can be passed on register must be kept at
1839 // RegsToPass vector
1840 if (VA.isRegLoc()) {
1841 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1842 continue;
1843 }
1844
1845 // Register can't get to this point...
1846 assert(VA.isMemLoc());
1847
1848 // ByVal Arg.
1849 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1850 if (Flags.isByVal()) {
1851 assert(Subtarget->isABI_O32() &&
1852 "No support for ByVal args by ABIs other than O32 yet.");
1853 assert(Flags.getByValSize() &&
1854 "ByVal args of size 0 should have been ignored by front-end.");
1855 WriteByValArg(Chain, dl, RegsToPass, MemOpChains, LastFI, MFI, DAG, Arg,
1856 VA, Flags, getPointerTy());
1857 continue;
1858 }
1859
1860 // Create the frame index object for this incoming parameter
1861 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1862 VA.getLocMemOffset(), true);
1863 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
1864
1865 // emit ISD::STORE whichs stores the
1866 // parameter value to a stack Location
1867 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
1868 MachinePointerInfo(),
1869 false, false, 0));
1870 }
1871
1872 // Extend range of indices of frame objects for outgoing arguments that were
1873 // created during this function call. Skip this step if no such objects were
1874 // created.
1875 if (LastFI)
1876 MipsFI->extendOutArgFIRange(FirstFI, LastFI);
1877
1878 // Transform all store nodes into one single node because all store
1879 // nodes are independent of each other.
1880 if (!MemOpChains.empty())
1881 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1882 &MemOpChains[0], MemOpChains.size());
1883
1884 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1885 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1886 // node so that legalize doesn't hack it.
1887 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
1888 bool LoadSymAddr = false;
1889 SDValue CalleeLo;
1890
1891 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1892 if (IsPIC && G->getGlobal()->hasInternalLinkage()) {
1893 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
1894 getPointerTy(), 0,MipsII:: MO_GOT);
1895 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
1896 0, MipsII::MO_ABS_LO);
1897 } else {
1898 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
1899 getPointerTy(), 0, OpFlag);
1900 }
1901
1902 LoadSymAddr = true;
1903 }
1904 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1905 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
1906 getPointerTy(), OpFlag);
1907 LoadSymAddr = true;
1908 }
1909
1910 SDValue InFlag;
1911
1912 // Create nodes that load address of callee and copy it to T9
1913 if (IsPIC) {
1914 if (LoadSymAddr) {
1915 // Load callee address
1916 Callee = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, Callee);
1917 SDValue LoadValue = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), Callee,
1918 MachinePointerInfo::getGOT(),
1919 false, false, 0);
1920
1921 // Use GOT+LO if callee has internal linkage.
1922 if (CalleeLo.getNode()) {
1923 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CalleeLo);
1924 Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo);
1925 } else
1926 Callee = LoadValue;
1927 }
1928
1929 // copy to T9
1930 Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0));
1931 InFlag = Chain.getValue(1);
1932 Callee = DAG.getRegister(Mips::T9, MVT::i32);
1933 }
1934
1935 // Build a sequence of copy-to-reg nodes chained together with token
1936 // chain and flag operands which copy the outgoing args into registers.
1937 // The InFlag in necessary since all emitted instructions must be
1938 // stuck together.
1939 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1940 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1941 RegsToPass[i].second, InFlag);
1942 InFlag = Chain.getValue(1);
1943 }
1944
1945 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
1946 // = Chain, Callee, Reg#1, Reg#2, ...
1947 //
1948 // Returns a chain & a flag for retval copy to use.
1949 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1950 SmallVector<SDValue, 8> Ops;
1951 Ops.push_back(Chain);
1952 Ops.push_back(Callee);
1953
1954 // Add argument registers to the end of the list so that they are
1955 // known live into the call.
1956 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1957 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1958 RegsToPass[i].second.getValueType()));
1959
1960 if (InFlag.getNode())
1961 Ops.push_back(InFlag);
1962
1963 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
1964 InFlag = Chain.getValue(1);
1965
1966 // Create the CALLSEQ_END node.
1967 Chain = DAG.getCALLSEQ_END(Chain,
1968 DAG.getIntPtrConstant(NextStackOffset, true),
1969 DAG.getIntPtrConstant(0, true), InFlag);
1970 InFlag = Chain.getValue(1);
1971
1972 // Handle result values, copying them out of physregs into vregs that we
1973 // return.
1974 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
1975 Ins, dl, DAG, InVals);
1976 }
1977
1978 /// LowerCallResult - Lower the result values of a call into the
1979 /// appropriate copies out of appropriate physical registers.
1980 SDValue
1981 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1982 CallingConv::ID CallConv, bool isVarArg,
1983 const SmallVectorImpl<ISD::InputArg> &Ins,
1984 DebugLoc dl, SelectionDAG &DAG,
1985 SmallVectorImpl<SDValue> &InVals) const {
1986 // Assign locations to each value returned by this call.
1987 SmallVector<CCValAssign, 16> RVLocs;
1988 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1989 getTargetMachine(), RVLocs, *DAG.getContext());
1990
1991 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
1992
1993 // Copy all of the result registers out of their specified physreg.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
1996 RVLocs[i].getValVT(), InFlag).getValue(1);
1997 InFlag = Chain.getValue(2);
1998 InVals.push_back(Chain.getValue(0));
1999 }
2000
2001 return Chain;
2002 }
2003
2004 //===----------------------------------------------------------------------===//
2005 // Formal Arguments Calling Convention Implementation
2006 //===----------------------------------------------------------------------===//
2007 static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl,
2008 std::vector<SDValue>& OutChains,
2009 SelectionDAG &DAG, unsigned NumWords, SDValue FIN,
2010 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags) {
2011 unsigned LocMem = VA.getLocMemOffset();
2012 unsigned FirstWord = LocMem / 4;
2013
2014 // copy register A0 - A3 to frame object
2015 for (unsigned i = 0; i < NumWords; ++i) {
2016 unsigned CurWord = FirstWord + i;
2017 if (CurWord >= O32IntRegsSize)
2018 break;
2019
2020 unsigned SrcReg = O32IntRegs[CurWord];
2021 unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass);
2022 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
2023 DAG.getConstant(i * 4, MVT::i32));
2024 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32),
2025 StorePtr, MachinePointerInfo(), false,
2026 false, 0);
2027 OutChains.push_back(Store);
2028 }
2029 }
2030
2031 /// LowerFormalArguments - transform physical registers into virtual registers
2032 /// and generate load operations for arguments places on the stack.
2033 SDValue
2034 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2035 CallingConv::ID CallConv,
2036 bool isVarArg,
2037 const SmallVectorImpl<ISD::InputArg>
2038 &Ins,
2039 DebugLoc dl, SelectionDAG &DAG,
2040 SmallVectorImpl<SDValue> &InVals)
2041 const {
2042 MachineFunction &MF = DAG.getMachineFunction();
2043 MachineFrameInfo *MFI = MF.getFrameInfo();
2044 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2045
2046 MipsFI->setVarArgsFrameIndex(0);
2047
2048 // Used with vargs to acumulate store chains.
2049 std::vector<SDValue> OutChains;
2050
2051 // Assign locations to all of the incoming arguments.
2052 SmallVector<CCValAssign, 16> ArgLocs;
2053 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2054 getTargetMachine(), ArgLocs, *DAG.getContext());
2055
2056 if (Subtarget->isABI_O32())
2057 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
2058 else
2059 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
2060
2061 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function.
2062
2063 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2064 CCValAssign &VA = ArgLocs[i];
2065
2066 // Arguments stored on registers
2067 if (VA.isRegLoc()) {
2068 EVT RegVT = VA.getLocVT();
2069 unsigned ArgReg = VA.getLocReg();
2070 TargetRegisterClass *RC = 0;
2071
2072 if (RegVT == MVT::i32)
2073 RC = Mips::CPURegsRegisterClass;
2074 else if (RegVT == MVT::f32)
2075 RC = Mips::FGR32RegisterClass;
2076 else if (RegVT == MVT::f64) {
2077 if (!Subtarget->isSingleFloat())
2078 RC = Mips::AFGR64RegisterClass;
2079 } else
2080 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
2081
2082 // Transform the arguments stored on
2083 // physical registers into virtual ones
2084 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
2085 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2086
2087 // If this is an 8 or 16-bit value, it has been passed promoted
2088 // to 32 bits. Insert an assert[sz]ext to capture this, then
2089 // truncate to the right size.
2090 if (VA.getLocInfo() != CCValAssign::Full) {
2091 unsigned Opcode = 0;
2092 if (VA.getLocInfo() == CCValAssign::SExt)
2093 Opcode = ISD::AssertSext;
2094 else if (VA.getLocInfo() == CCValAssign::ZExt)
2095 Opcode = ISD::AssertZext;
2096 if (Opcode)
2097 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
2098 DAG.getValueType(VA.getValVT()));
2099 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2100 }
2101
2102 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
2103 if (Subtarget->isABI_O32()) {
2104 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
2105 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue);
2106 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
2107 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
2108 VA.getLocReg()+1, RC);
2109 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
2110 if (!Subtarget->isLittle())
2111 std::swap(ArgValue, ArgValue2);
2112 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
2113 ArgValue, ArgValue2);
2114 }
2115 }
2116
2117 InVals.push_back(ArgValue);
2118 } else { // VA.isRegLoc()
2119
2120 // sanity check
2121 assert(VA.isMemLoc());
2122
2123 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2124
2125 if (Flags.isByVal()) {
2126 assert(Subtarget->isABI_O32() &&
2127 "No support for ByVal args by ABIs other than O32 yet.");
2128 assert(Flags.getByValSize() &&
2129 "ByVal args of size 0 should have been ignored by front-end.");
2130 unsigned NumWords = (Flags.getByValSize() + 3) / 4;
2131 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(),
2132 true);
2133 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
2134 InVals.push_back(FIN);
2135 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags);
2136
2137 continue;
2138 }
2139
2140 // The stack pointer offset is relative to the caller stack frame.
2141 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
2142 VA.getLocMemOffset(), true);
2143
2144 // Create load nodes to retrieve arguments from the stack
2145 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
2146 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2147 MachinePointerInfo::getFixedStack(LastFI),
2148 false, false, 0));
2149 }
2150 }
2151
2152 // The mips ABIs for returning structs by value requires that we copy
2153 // the sret argument into $v0 for the return. Save the argument into
2154 // a virtual register so that we can access it from the return points.
2155 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2156 unsigned Reg = MipsFI->getSRetReturnReg();
2157 if (!Reg) {
2158 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
2159 MipsFI->setSRetReturnReg(Reg);
2160 }
2161 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2162 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2163 }
2164
2165 if (isVarArg && Subtarget->isABI_O32()) {
2166 // Record the frame index of the first variable argument
2167 // which is a value necessary to VASTART.
2168 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2169 assert(NextStackOffset % 4 == 0 &&
2170 "NextStackOffset must be aligned to 4-byte boundaries.");
2171 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
2172 MipsFI->setVarArgsFrameIndex(LastFI);
2173
2174 // If NextStackOffset is smaller than o32's 16-byte reserved argument area,
2175 // copy the integer registers that have not been used for argument passing
2176 // to the caller's stack frame.
2177 for (; NextStackOffset < 16; NextStackOffset += 4) {
2178 TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
2179 unsigned Idx = NextStackOffset / 4;
2180 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), O32IntRegs[Idx], RC);
2181 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
2182 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
2183 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
2184 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
2185 MachinePointerInfo(),
2186 false, false, 0));
2187 }
2188 }
2189
2190 MipsFI->setLastInArgFI(LastFI);
2191
2192 // All stores are grouped in one node to allow the matching between
2193 // the size of Ins and InVals. This only happens when on varg functions
2194 if (!OutChains.empty()) {
2195 OutChains.push_back(Chain);
2196 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2197 &OutChains[0], OutChains.size());
2198 }
2199
2200 return Chain;
2201 }
2202
2203 //===----------------------------------------------------------------------===//
2204 // Return Value Calling Convention Implementation
2205 //===----------------------------------------------------------------------===//
2206
2207 SDValue
2208 MipsTargetLowering::LowerReturn(SDValue Chain,
2209 CallingConv::ID CallConv, bool isVarArg,
2210 const SmallVectorImpl<ISD::OutputArg> &Outs,
2211 const SmallVectorImpl<SDValue> &OutVals,
2212 DebugLoc dl, SelectionDAG &DAG) const {
2213
2214 // CCValAssign - represent the assignment of
2215 // the return value to a location
2216 SmallVector<CCValAssign, 16> RVLocs;
2217
2218 // CCState - Info about the registers and stack slot.
2219 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2220 getTargetMachine(), RVLocs, *DAG.getContext());
2221
2222 // Analize return values.
2223 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
2224
2225 // If this is the first return lowered for this function, add
2226 // the regs to the liveout set for the function.
2227 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2228 for (unsigned i = 0; i != RVLocs.size(); ++i)
2229 if (RVLocs[i].isRegLoc())
2230 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2231 }
2232
2233 SDValue Flag;
2234
2235 // Copy the result values into the output registers.
2236 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2237 CCValAssign &VA = RVLocs[i];
2238 assert(VA.isRegLoc() && "Can only return in registers!");
2239
2240 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2241 OutVals[i], Flag);
2242
2243 // guarantee that all emitted copies are
2244 // stuck together, avoiding something bad
2245 Flag = Chain.getValue(1);
2246 }
2247
2248 // The mips ABIs for returning structs by value requires that we copy
2249 // the sret argument into $v0 for the return. We saved the argument into
2250 // a virtual register in the entry block, so now we copy the value out
2251 // and into $v0.
2252 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2253 MachineFunction &MF = DAG.getMachineFunction();
2254 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2255 unsigned Reg = MipsFI->getSRetReturnReg();
2256
2257 if (!Reg)
2258 llvm_unreachable("sret virtual register not created in the entry block");
2259 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2260
2261 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
2262 Flag = Chain.getValue(1);
2263 }
2264
2265 // Return on Mips is always a "jr $ra"
2266 if (Flag.getNode())
2267 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
2268 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
2269 else // Return Void
2270 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
2271 Chain, DAG.getRegister(Mips::RA, MVT::i32));
2272 }
2273
2274 //===----------------------------------------------------------------------===//
2275 // Mips Inline Assembly Support
2276 //===----------------------------------------------------------------------===//
2277
2278 /// getConstraintType - Given a constraint letter, return the type of
2279 /// constraint it is for this target.
2280 MipsTargetLowering::ConstraintType MipsTargetLowering::
2281 getConstraintType(const std::string &Constraint) const
2282 {
2283 // Mips specific constrainy
2284 // GCC config/mips/constraints.md
2285 //
2286 // 'd' : An address register. Equivalent to r
2287 // unless generating MIPS16 code.
2288 // 'y' : Equivalent to r; retained for
2289 // backwards compatibility.
2290 // 'f' : Floating Point registers.
2291 if (Constraint.size() == 1) {
2292 switch (Constraint[0]) {
2293 default : break;
2294 case 'd':
2295 case 'y':
2296 case 'f':
2297 return C_RegisterClass;
2298 break;
2299 }
2300 }
2301 return TargetLowering::getConstraintType(Constraint);
2302 }
2303
2304 /// Examine constraint type and operand type and determine a weight value.
2305 /// This object must already have been set up with the operand type
2306 /// and the current alternative constraint selected.
2307 TargetLowering::ConstraintWeight
2308 MipsTargetLowering::getSingleConstraintMatchWeight(
2309 AsmOperandInfo &info, const char *constraint) const {
2310 ConstraintWeight weight = CW_Invalid;
2311 Value *CallOperandVal = info.CallOperandVal;
2312 // If we don't have a value, we can't do a match,
2313 // but allow it at the lowest weight.
2314 if (CallOperandVal == NULL)
2315 return CW_Default;
2316 const Type *type = CallOperandVal->getType();
2317 // Look at the constraint type.
2318 switch (*constraint) {
2319 default:
2320 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
2321 break;
2322 case 'd':
2323 case 'y':
2324 if (type->isIntegerTy())
2325 weight = CW_Register;
2326 break;
2327 case 'f':
2328 if (type->isFloatTy())
2329 weight = CW_Register;
2330 break;
2331 }
2332 return weight;
2333 }
2334
2335 /// Given a register class constraint, like 'r', if this corresponds directly
2336 /// to an LLVM register class, return a register of 0 and the register class
2337 /// pointer.
2338 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
2339 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
2340 {
2341 if (Constraint.size() == 1) {
2342 switch (Constraint[0]) {
2343 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
2344 case 'y': // Same as 'r'. Exists for compatibility.
2345 case 'r':
2346 return std::make_pair(0U, Mips::CPURegsRegisterClass);
2347 case 'f':
2348 if (VT == MVT::f32)
2349 return std::make_pair(0U, Mips::FGR32RegisterClass);
2350 if (VT == MVT::f64)
2351 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
2352 return std::make_pair(0U, Mips::AFGR64RegisterClass);
2353 break;
2354 }
2355 }
2356 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2357 }
2358
2359 bool
2360 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
2361 // The Mips target isn't yet aware of offsets.
2362 return false;
2363 }
2364
2365 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2366 if (VT != MVT::f32 && VT != MVT::f64)
2367 return false;
2368 if (Imm.isNegZero())
2369 return false;
2370 return Imm.isZero();
2371 }
STM8 backend for LLVM