lib/Target/TargetRegisterInfo.cpp

   1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the TargetRegisterInfo interface.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/Target/TargetMachine.h"
  15 #include "llvm/Target/TargetRegisterInfo.h"
  16 #include "llvm/CodeGen/MachineFunction.h"
  17 #include "llvm/CodeGen/MachineFrameInfo.h"
  18 #include "llvm/ADT/BitVector.h"
  19 #include "llvm/Support/raw_ostream.h"
  20
  21 using namespace llvm;
  22
  23 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
  24                              regclass_iterator RCB, regclass_iterator RCE,
  25                              const char *const *subregindexnames,
  26                              int CFSO, int CFDO,
  27                              const unsigned* subregs, const unsigned subregsize,
  28                          const unsigned* aliases, const unsigned aliasessize)
  29   : SubregHash(subregs), SubregHashSize(subregsize),
  30     AliasesHash(aliases), AliasesHashSize(aliasessize),
  31     Desc(D), SubRegIndexNames(subregindexnames), NumRegs(NR),
  32     RegClassBegin(RCB), RegClassEnd(RCE) {
  33   assert(isPhysicalRegister(NumRegs) &&
  34          "Target has too many physical registers!");
  35
  36   CallFrameSetupOpcode   = CFSO;
  37   CallFrameDestroyOpcode = CFDO;
  38 }
  39
  40 TargetRegisterInfo::~TargetRegisterInfo() {}
  41
  42 void PrintReg::print(raw_ostream &OS) const {
  43   if (!Reg)
  44     OS << "%noreg";
  45   else if (TargetRegisterInfo::isStackSlot(Reg))
  46     OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
  47   else if (TargetRegisterInfo::isVirtualRegister(Reg))
  48     OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
  49   else if (TRI && Reg < TRI->getNumRegs())
  50     OS << '%' << TRI->getName(Reg);
  51   else
  52     OS << "%physreg" << Reg;
  53   if (SubIdx) {
  54     if (TRI)
  55       OS << ':' << TRI->getSubRegIndexName(SubIdx);
  56     else
  57       OS << ":sub(" << SubIdx << ')';
  58   }
  59 }
  60
  61 /// getMinimalPhysRegClass - Returns the Register Class of a physical
  62 /// register of the given type, picking the most sub register class of
  63 /// the right type that contains this physreg.
  64 const TargetRegisterClass *
  65 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
  66   assert(isPhysicalRegister(reg) && "reg must be a physical register");
  67
  68   // Pick the most sub register class of the right type that contains
  69   // this physreg.
  70   const TargetRegisterClass* BestRC = 0;
  71   for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
  72     const TargetRegisterClass* RC = *I;
  73     if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
  74         (!BestRC || BestRC->hasSubClass(RC)))
  75       BestRC = RC;
  76   }
  77
  78   assert(BestRC && "Couldn't find the register class");
  79   return BestRC;
  80 }
  81
  82 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
  83 /// registers for the specific register class.
  84 static void getAllocatableSetForRC(const MachineFunction &MF,
  85                                    const TargetRegisterClass *RC, BitVector &R){
  86   for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
  87          E = RC->allocation_order_end(MF); I != E; ++I)
  88     R.set(*I);
  89 }
  90
  91 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
  92                                           const TargetRegisterClass *RC) const {
  93   BitVector Allocatable(NumRegs);
  94   if (RC) {
  95     getAllocatableSetForRC(MF, RC, Allocatable);
  96   } else {
  97     for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
  98          E = regclass_end(); I != E; ++I)
  99       getAllocatableSetForRC(MF, *I, Allocatable);
 100   }
 101
 102   // Mask out the reserved registers
 103   BitVector Reserved = getReservedRegs(MF);
 104   Allocatable &= Reserved.flip();
 105
 106   return Allocatable;
 107 }
 108
 109 const TargetRegisterClass *
 110 llvm::getCommonSubClass(const TargetRegisterClass *A,
 111                         const TargetRegisterClass *B) {
 112   // First take care of the trivial cases
 113   if (A == B)
 114     return A;
 115   if (!A || !B)
 116     return 0;
 117
 118   // If B is a subclass of A, it will be handled in the loop below
 119   if (B->hasSubClass(A))
 120     return A;
 121
 122   const TargetRegisterClass *Best = 0;
 123   for (TargetRegisterClass::sc_iterator I = A->subclasses_begin();
 124        const TargetRegisterClass *X = *I; ++I) {
 125     if (X == B)
 126       return B;                 // B is a subclass of A
 127
 128     // X must be a common subclass of A and B
 129     if (!B->hasSubClass(X))
 130       continue;
 131
 132     // A superclass is definitely better.
 133     if (!Best || Best->hasSuperClass(X)) {
 134       Best = X;
 135       continue;
 136     }
 137
 138     // A subclass is definitely worse
 139     if (Best->hasSubClass(X))
 140       continue;
 141
 142     // Best and *I have no super/sub class relation - pick the larger class, or
 143     // the smaller spill size.
 144     int nb = std::distance(Best->begin(), Best->end());
 145     int ni = std::distance(X->begin(), X->end());
 146     if (ni>nb || (ni==nb && X->getSize() < Best->getSize()))
 147       Best = X;
 148   }
 149   return Best;
 150 }