Add a small missed optimization: turn X == C ? X : Y into X == C ? C : Y. This
[llvm/stm8.git] / lib / CodeGen / SimpleRegisterCoalescing.h
blob11849dfca05871068e5b9be648d43afc3123a9cc
1 //===-- SimpleRegisterCoalescing.h - Register Coalescing --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements a simple register copy coalescing phase.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
15 #define LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/RegisterCoalescer.h"
20 #include "llvm/ADT/BitVector.h"
22 namespace llvm {
23 class SimpleRegisterCoalescing;
24 class LiveDebugVariables;
25 class TargetRegisterInfo;
26 class TargetInstrInfo;
27 class VirtRegMap;
28 class MachineLoopInfo;
30 /// CopyRec - Representation for copy instructions in coalescer queue.
31 ///
32 struct CopyRec {
33 MachineInstr *MI;
34 unsigned LoopDepth;
35 CopyRec(MachineInstr *mi, unsigned depth)
36 : MI(mi), LoopDepth(depth) {}
39 class SimpleRegisterCoalescing : public MachineFunctionPass,
40 public RegisterCoalescer {
41 MachineFunction* mf_;
42 MachineRegisterInfo* mri_;
43 const TargetMachine* tm_;
44 const TargetRegisterInfo* tri_;
45 const TargetInstrInfo* tii_;
46 LiveIntervals *li_;
47 LiveDebugVariables *ldv_;
48 const MachineLoopInfo* loopInfo;
49 AliasAnalysis *AA;
51 DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
53 /// JoinedCopies - Keep track of copies eliminated due to coalescing.
54 ///
55 SmallPtrSet<MachineInstr*, 32> JoinedCopies;
57 /// ReMatCopies - Keep track of copies eliminated due to remat.
58 ///
59 SmallPtrSet<MachineInstr*, 32> ReMatCopies;
61 /// ReMatDefs - Keep track of definition instructions which have
62 /// been remat'ed.
63 SmallPtrSet<MachineInstr*, 8> ReMatDefs;
65 public:
66 static char ID; // Pass identifcation, replacement for typeid
67 SimpleRegisterCoalescing() : MachineFunctionPass(ID) {
68 initializeSimpleRegisterCoalescingPass(*PassRegistry::getPassRegistry());
71 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
72 virtual void releaseMemory();
74 /// runOnMachineFunction - pass entry point
75 virtual bool runOnMachineFunction(MachineFunction&);
77 bool coalesceFunction(MachineFunction &mf, RegallocQuery &) {
78 // This runs as an independent pass, so don't do anything.
79 return false;
82 /// print - Implement the dump method.
83 virtual void print(raw_ostream &O, const Module* = 0) const;
85 private:
86 /// joinIntervals - join compatible live intervals
87 void joinIntervals();
89 /// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
90 /// copies that cannot yet be coalesced into the "TryAgain" list.
91 void CopyCoalesceInMBB(MachineBasicBlock *MBB,
92 std::vector<CopyRec> &TryAgain);
94 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
95 /// which are the src/dst of the copy instruction CopyMI. This returns true
96 /// if the copy was successfully coalesced away. If it is not currently
97 /// possible to coalesce this interval, but it may be possible if other
98 /// things get coalesced, then it returns true by reference in 'Again'.
99 bool JoinCopy(CopyRec &TheCopy, bool &Again);
101 /// JoinIntervals - Attempt to join these two intervals. On failure, this
102 /// returns false. The output "SrcInt" will not have been modified, so we can
103 /// use this information below to update aliases.
104 bool JoinIntervals(CoalescerPair &CP);
106 /// Return true if the two specified registers belong to different register
107 /// classes. The registers may be either phys or virt regs.
108 bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
110 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
111 /// the source value number is defined by a copy from the destination reg
112 /// see if we can merge these two destination reg valno# into a single
113 /// value number, eliminating a copy.
114 bool AdjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
116 /// HasOtherReachingDefs - Return true if there are definitions of IntB
117 /// other than BValNo val# that can reach uses of AValno val# of IntA.
118 bool HasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
119 VNInfo *AValNo, VNInfo *BValNo);
121 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy.
122 /// If the source value number is defined by a commutable instruction and
123 /// its other operand is coalesced to the copy dest register, see if we
124 /// can transform the copy into a noop by commuting the definition.
125 bool RemoveCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
127 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic
128 /// block as the copy instruction, trim the ive interval to the last use
129 /// and return true.
130 bool TrimLiveIntervalToLastUse(SlotIndex CopyIdx,
131 MachineBasicBlock *CopyMBB,
132 LiveInterval &li, const LiveRange *LR);
134 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
135 /// computation, replace the copy by rematerialize the definition.
136 /// If PreserveSrcInt is true, make sure SrcInt is valid after the call.
137 bool ReMaterializeTrivialDef(LiveInterval &SrcInt, bool PreserveSrcInt,
138 unsigned DstReg, unsigned DstSubIdx,
139 MachineInstr *CopyMI);
141 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
142 /// two virtual registers from different register classes.
143 bool isWinToJoinCrossClass(unsigned SrcReg,
144 unsigned DstReg,
145 const TargetRegisterClass *SrcRC,
146 const TargetRegisterClass *DstRC,
147 const TargetRegisterClass *NewRC);
149 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
150 /// update the subregister number if it is not zero. If DstReg is a
151 /// physical register and the existing subregister number of the def / use
152 /// being updated is not zero, make sure to set it to the correct physical
153 /// subregister.
154 void UpdateRegDefsUses(const CoalescerPair &CP);
156 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
157 /// Return true if live interval is removed.
158 bool ShortenDeadCopyLiveRange(LiveInterval &li, MachineInstr *CopyMI);
160 /// ShortenDeadCopyLiveRange - Shorten a live range as it's artificially
161 /// extended by a dead copy. Mark the last use (if any) of the val# as kill
162 /// as ends the live range there. If there isn't another use, then this
163 /// live range is dead. Return true if live interval is removed.
164 bool ShortenDeadCopySrcLiveRange(LiveInterval &li, MachineInstr *CopyMI);
166 /// RemoveDeadDef - If a def of a live interval is now determined dead,
167 /// remove the val# it defines. If the live interval becomes empty, remove
168 /// it as well.
169 bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
171 /// RemoveCopyFlag - If DstReg is no longer defined by CopyMI, clear the
172 /// VNInfo copy flag for DstReg and all aliases.
173 void RemoveCopyFlag(unsigned DstReg, const MachineInstr *CopyMI);
175 /// lastRegisterUse - Returns the last use of the specific register between
176 /// cycles Start and End or NULL if there are no uses.
177 MachineOperand *lastRegisterUse(SlotIndex Start, SlotIndex End,
178 unsigned Reg, SlotIndex &LastUseIdx) const;
181 } // End llvm namespace
183 #endif