lib/CodeGen/MachineVerifier.cpp

   1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Pass to verify generated machine code. The following is checked:
  11 //
  12 // Operand counts: All explicit operands must be present.
  13 //
  14 // Register classes: All physical and virtual register operands must be
  15 // compatible with the register class required by the instruction descriptor.
  16 //
  17 // Register live intervals: Registers must be defined only once, and must be
  18 // defined before use.
  19 //
  20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
  21 // command-line option -verify-machineinstrs, or by defining the environment
  22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
  23 // the verifier errors.
  24 //===----------------------------------------------------------------------===//
  25
  26 #include "llvm/Function.h"
  27 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
  28 #include "llvm/CodeGen/LiveVariables.h"
  29 #include "llvm/CodeGen/LiveStackAnalysis.h"
  30 #include "llvm/CodeGen/MachineFunctionPass.h"
  31 #include "llvm/CodeGen/MachineFrameInfo.h"
  32 #include "llvm/CodeGen/MachineMemOperand.h"
  33 #include "llvm/CodeGen/MachineRegisterInfo.h"
  34 #include "llvm/CodeGen/Passes.h"
  35 #include "llvm/Target/TargetMachine.h"
  36 #include "llvm/Target/TargetRegisterInfo.h"
  37 #include "llvm/Target/TargetInstrInfo.h"
  38 #include "llvm/ADT/DenseSet.h"
  39 #include "llvm/ADT/SetOperations.h"
  40 #include "llvm/ADT/SmallVector.h"
  41 #include "llvm/Support/Debug.h"
  42 #include "llvm/Support/ErrorHandling.h"
  43 #include "llvm/Support/raw_ostream.h"
  44 using namespace llvm;
  45
  46 namespace {
  47   struct MachineVerifier {
  48
  49     MachineVerifier(Pass *pass, const char *b) :
  50       PASS(pass),
  51       Banner(b),
  52       OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
  53       {}
  54
  55     bool runOnMachineFunction(MachineFunction &MF);
  56
  57     Pass *const PASS;
  58     const char *Banner;
  59     const char *const OutFileName;
  60     raw_ostream *OS;
  61     const MachineFunction *MF;
  62     const TargetMachine *TM;
  63     const TargetRegisterInfo *TRI;
  64     const MachineRegisterInfo *MRI;
  65
  66     unsigned foundErrors;
  67
  68     typedef SmallVector<unsigned, 16> RegVector;
  69     typedef DenseSet<unsigned> RegSet;
  70     typedef DenseMap<unsigned, const MachineInstr*> RegMap;
  71
  72     BitVector regsReserved;
  73     RegSet regsLive;
  74     RegVector regsDefined, regsDead, regsKilled;
  75     RegSet regsLiveInButUnused;
  76
  77     SlotIndex lastIndex;
  78
  79     // Add Reg and any sub-registers to RV
  80     void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
  81       RV.push_back(Reg);
  82       if (TargetRegisterInfo::isPhysicalRegister(Reg))
  83         for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
  84           RV.push_back(*R);
  85     }
  86
  87     struct BBInfo {
  88       // Is this MBB reachable from the MF entry point?
  89       bool reachable;
  90
  91       // Vregs that must be live in because they are used without being
  92       // defined. Map value is the user.
  93       RegMap vregsLiveIn;
  94
  95       // Regs killed in MBB. They may be defined again, and will then be in both
  96       // regsKilled and regsLiveOut.
  97       RegSet regsKilled;
  98
  99       // Regs defined in MBB and live out. Note that vregs passing through may
 100       // be live out without being mentioned here.
 101       RegSet regsLiveOut;
 102
 103       // Vregs that pass through MBB untouched. This set is disjoint from
 104       // regsKilled and regsLiveOut.
 105       RegSet vregsPassed;
 106
 107       // Vregs that must pass through MBB because they are needed by a successor
 108       // block. This set is disjoint from regsLiveOut.
 109       RegSet vregsRequired;
 110
 111       BBInfo() : reachable(false) {}
 112
 113       // Add register to vregsPassed if it belongs there. Return true if
 114       // anything changed.
 115       bool addPassed(unsigned Reg) {
 116         if (!TargetRegisterInfo::isVirtualRegister(Reg))
 117           return false;
 118         if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
 119           return false;
 120         return vregsPassed.insert(Reg).second;
 121       }
 122
 123       // Same for a full set.
 124       bool addPassed(const RegSet &RS) {
 125         bool changed = false;
 126         for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
 127           if (addPassed(*I))
 128             changed = true;
 129         return changed;
 130       }
 131
 132       // Add register to vregsRequired if it belongs there. Return true if
 133       // anything changed.
 134       bool addRequired(unsigned Reg) {
 135         if (!TargetRegisterInfo::isVirtualRegister(Reg))
 136           return false;
 137         if (regsLiveOut.count(Reg))
 138           return false;
 139         return vregsRequired.insert(Reg).second;
 140       }
 141
 142       // Same for a full set.
 143       bool addRequired(const RegSet &RS) {
 144         bool changed = false;
 145         for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
 146           if (addRequired(*I))
 147             changed = true;
 148         return changed;
 149       }
 150
 151       // Same for a full map.
 152       bool addRequired(const RegMap &RM) {
 153         bool changed = false;
 154         for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
 155           if (addRequired(I->first))
 156             changed = true;
 157         return changed;
 158       }
 159
 160       // Live-out registers are either in regsLiveOut or vregsPassed.
 161       bool isLiveOut(unsigned Reg) const {
 162         return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
 163       }
 164     };
 165
 166     // Extra register info per MBB.
 167     DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
 168
 169     bool isReserved(unsigned Reg) {
 170       return Reg < regsReserved.size() && regsReserved.test(Reg);
 171     }
 172
 173     // Analysis information if available
 174     LiveVariables *LiveVars;
 175     LiveIntervals *LiveInts;
 176     LiveStacks *LiveStks;
 177     SlotIndexes *Indexes;
 178
 179     void visitMachineFunctionBefore();
 180     void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
 181     void visitMachineInstrBefore(const MachineInstr *MI);
 182     void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
 183     void visitMachineInstrAfter(const MachineInstr *MI);
 184     void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
 185     void visitMachineFunctionAfter();
 186
 187     void report(const char *msg, const MachineFunction *MF);
 188     void report(const char *msg, const MachineBasicBlock *MBB);
 189     void report(const char *msg, const MachineInstr *MI);
 190     void report(const char *msg, const MachineOperand *MO, unsigned MONum);
 191
 192     void markReachable(const MachineBasicBlock *MBB);
 193     void calcRegsPassed();
 194     void checkPHIOps(const MachineBasicBlock *MBB);
 195
 196     void calcRegsRequired();
 197     void verifyLiveVariables();
 198     void verifyLiveIntervals();
 199   };
 200
 201   struct MachineVerifierPass : public MachineFunctionPass {
 202     static char ID; // Pass ID, replacement for typeid
 203     const char *const Banner;
 204
 205     MachineVerifierPass(const char *b = 0)
 206       : MachineFunctionPass(ID), Banner(b) {
 207         initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
 208       }
 209
 210     void getAnalysisUsage(AnalysisUsage &AU) const {
 211       AU.setPreservesAll();
 212       MachineFunctionPass::getAnalysisUsage(AU);
 213     }
 214
 215     bool runOnMachineFunction(MachineFunction &MF) {
 216       MF.verify(this, Banner);
 217       return false;
 218     }
 219   };
 220
 221 }
 222
 223 char MachineVerifierPass::ID = 0;
 224 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
 225                 "Verify generated machine code", false, false)
 226
 227 FunctionPass *llvm::createMachineVerifierPass(const char *Banner) {
 228   return new MachineVerifierPass(Banner);
 229 }
 230
 231 void MachineFunction::verify(Pass *p, const char *Banner) const {
 232   MachineVerifier(p, Banner)
 233     .runOnMachineFunction(const_cast<MachineFunction&>(*this));
 234 }
 235
 236 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
 237   raw_ostream *OutFile = 0;
 238   if (OutFileName) {
 239     std::string ErrorInfo;
 240     OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
 241                                  raw_fd_ostream::F_Append);
 242     if (!ErrorInfo.empty()) {
 243       errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
 244       exit(1);
 245     }
 246
 247     OS = OutFile;
 248   } else {
 249     OS = &errs();
 250   }
 251
 252   foundErrors = 0;
 253
 254   this->MF = &MF;
 255   TM = &MF.getTarget();
 256   TRI = TM->getRegisterInfo();
 257   MRI = &MF.getRegInfo();
 258
 259   LiveVars = NULL;
 260   LiveInts = NULL;
 261   LiveStks = NULL;
 262   Indexes = NULL;
 263   if (PASS) {
 264     LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
 265     // We don't want to verify LiveVariables if LiveIntervals is available.
 266     if (!LiveInts)
 267       LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
 268     LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
 269     Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
 270   }
 271
 272   visitMachineFunctionBefore();
 273   for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
 274        MFI!=MFE; ++MFI) {
 275     visitMachineBasicBlockBefore(MFI);
 276     for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
 277            MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
 278       if (MBBI->getParent() != MFI) {
 279         report("Bad instruction parent pointer", MFI);
 280         *OS << "Instruction: " << *MBBI;
 281         continue;
 282       }
 283       visitMachineInstrBefore(MBBI);
 284       for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
 285         visitMachineOperand(&MBBI->getOperand(I), I);
 286       visitMachineInstrAfter(MBBI);
 287     }
 288     visitMachineBasicBlockAfter(MFI);
 289   }
 290   visitMachineFunctionAfter();
 291
 292   if (OutFile)
 293     delete OutFile;
 294   else if (foundErrors)
 295     report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
 296
 297   // Clean up.
 298   regsLive.clear();
 299   regsDefined.clear();
 300   regsDead.clear();
 301   regsKilled.clear();
 302   regsLiveInButUnused.clear();
 303   MBBInfoMap.clear();
 304
 305   return false;                 // no changes
 306 }
 307
 308 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
 309   assert(MF);
 310   *OS << '\n';
 311   if (!foundErrors++) {
 312     if (Banner)
 313       *OS << "# " << Banner << '\n';
 314     MF->print(*OS, Indexes);
 315   }
 316   *OS << "*** Bad machine code: " << msg << " ***\n"
 317       << "- function:    " << MF->getFunction()->getNameStr() << "\n";
 318 }
 319
 320 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
 321   assert(MBB);
 322   report(msg, MBB->getParent());
 323   *OS << "- basic block: " << MBB->getName()
 324       << " " << (void*)MBB
 325       << " (BB#" << MBB->getNumber() << ")";
 326   if (Indexes)
 327     *OS << " [" << Indexes->getMBBStartIdx(MBB)
 328         << ';' <<  Indexes->getMBBEndIdx(MBB) << ')';
 329   *OS << '\n';
 330 }
 331
 332 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
 333   assert(MI);
 334   report(msg, MI->getParent());
 335   *OS << "- instruction: ";
 336   if (Indexes && Indexes->hasIndex(MI))
 337     *OS << Indexes->getInstructionIndex(MI) << '\t';
 338   MI->print(*OS, TM);
 339 }
 340
 341 void MachineVerifier::report(const char *msg,
 342                              const MachineOperand *MO, unsigned MONum) {
 343   assert(MO);
 344   report(msg, MO->getParent());
 345   *OS << "- operand " << MONum << ":   ";
 346   MO->print(*OS, TM);
 347   *OS << "\n";
 348 }
 349
 350 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
 351   BBInfo &MInfo = MBBInfoMap[MBB];
 352   if (!MInfo.reachable) {
 353     MInfo.reachable = true;
 354     for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
 355            SuE = MBB->succ_end(); SuI != SuE; ++SuI)
 356       markReachable(*SuI);
 357   }
 358 }
 359
 360 void MachineVerifier::visitMachineFunctionBefore() {
 361   lastIndex = SlotIndex();
 362   regsReserved = TRI->getReservedRegs(*MF);
 363
 364   // A sub-register of a reserved register is also reserved
 365   for (int Reg = regsReserved.find_first(); Reg>=0;
 366        Reg = regsReserved.find_next(Reg)) {
 367     for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
 368       // FIXME: This should probably be:
 369       // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
 370       regsReserved.set(*Sub);
 371     }
 372   }
 373   markReachable(&MF->front());
 374 }
 375
 376 // Does iterator point to a and b as the first two elements?
 377 static bool matchPair(MachineBasicBlock::const_succ_iterator i,
 378                       const MachineBasicBlock *a, const MachineBasicBlock *b) {
 379   if (*i == a)
 380     return *++i == b;
 381   if (*i == b)
 382     return *++i == a;
 383   return false;
 384 }
 385
 386 void
 387 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
 388   const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
 389
 390   // Count the number of landing pad successors.
 391   SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
 392   for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
 393        E = MBB->succ_end(); I != E; ++I) {
 394     if ((*I)->isLandingPad())
 395       LandingPadSuccs.insert(*I);
 396   }
 397   if (LandingPadSuccs.size() > 1)
 398     report("MBB has more than one landing pad successor", MBB);
 399
 400   // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
 401   MachineBasicBlock *TBB = 0, *FBB = 0;
 402   SmallVector<MachineOperand, 4> Cond;
 403   if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
 404                           TBB, FBB, Cond)) {
 405     // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
 406     // check whether its answers match up with reality.
 407     if (!TBB && !FBB) {
 408       // Block falls through to its successor.
 409       MachineFunction::const_iterator MBBI = MBB;
 410       ++MBBI;
 411       if (MBBI == MF->end()) {
 412         // It's possible that the block legitimately ends with a noreturn
 413         // call or an unreachable, in which case it won't actually fall
 414         // out the bottom of the function.
 415       } else if (MBB->succ_size() == LandingPadSuccs.size()) {
 416         // It's possible that the block legitimately ends with a noreturn
 417         // call or an unreachable, in which case it won't actuall fall
 418         // out of the block.
 419       } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
 420         report("MBB exits via unconditional fall-through but doesn't have "
 421                "exactly one CFG successor!", MBB);
 422       } else if (!MBB->isSuccessor(MBBI)) {
 423         report("MBB exits via unconditional fall-through but its successor "
 424                "differs from its CFG successor!", MBB);
 425       }
 426       if (!MBB->empty() && MBB->back().getDesc().isBarrier() &&
 427           !TII->isPredicated(&MBB->back())) {
 428         report("MBB exits via unconditional fall-through but ends with a "
 429                "barrier instruction!", MBB);
 430       }
 431       if (!Cond.empty()) {
 432         report("MBB exits via unconditional fall-through but has a condition!",
 433                MBB);
 434       }
 435     } else if (TBB && !FBB && Cond.empty()) {
 436       // Block unconditionally branches somewhere.
 437       if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
 438         report("MBB exits via unconditional branch but doesn't have "
 439                "exactly one CFG successor!", MBB);
 440       } else if (!MBB->isSuccessor(TBB)) {
 441         report("MBB exits via unconditional branch but the CFG "
 442                "successor doesn't match the actual successor!", MBB);
 443       }
 444       if (MBB->empty()) {
 445         report("MBB exits via unconditional branch but doesn't contain "
 446                "any instructions!", MBB);
 447       } else if (!MBB->back().getDesc().isBarrier()) {
 448         report("MBB exits via unconditional branch but doesn't end with a "
 449                "barrier instruction!", MBB);
 450       } else if (!MBB->back().getDesc().isTerminator()) {
 451         report("MBB exits via unconditional branch but the branch isn't a "
 452                "terminator instruction!", MBB);
 453       }
 454     } else if (TBB && !FBB && !Cond.empty()) {
 455       // Block conditionally branches somewhere, otherwise falls through.
 456       MachineFunction::const_iterator MBBI = MBB;
 457       ++MBBI;
 458       if (MBBI == MF->end()) {
 459         report("MBB conditionally falls through out of function!", MBB);
 460       } if (MBB->succ_size() != 2) {
 461         report("MBB exits via conditional branch/fall-through but doesn't have "
 462                "exactly two CFG successors!", MBB);
 463       } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
 464         report("MBB exits via conditional branch/fall-through but the CFG "
 465                "successors don't match the actual successors!", MBB);
 466       }
 467       if (MBB->empty()) {
 468         report("MBB exits via conditional branch/fall-through but doesn't "
 469                "contain any instructions!", MBB);
 470       } else if (MBB->back().getDesc().isBarrier()) {
 471         report("MBB exits via conditional branch/fall-through but ends with a "
 472                "barrier instruction!", MBB);
 473       } else if (!MBB->back().getDesc().isTerminator()) {
 474         report("MBB exits via conditional branch/fall-through but the branch "
 475                "isn't a terminator instruction!", MBB);
 476       }
 477     } else if (TBB && FBB) {
 478       // Block conditionally branches somewhere, otherwise branches
 479       // somewhere else.
 480       if (MBB->succ_size() != 2) {
 481         report("MBB exits via conditional branch/branch but doesn't have "
 482                "exactly two CFG successors!", MBB);
 483       } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
 484         report("MBB exits via conditional branch/branch but the CFG "
 485                "successors don't match the actual successors!", MBB);
 486       }
 487       if (MBB->empty()) {
 488         report("MBB exits via conditional branch/branch but doesn't "
 489                "contain any instructions!", MBB);
 490       } else if (!MBB->back().getDesc().isBarrier()) {
 491         report("MBB exits via conditional branch/branch but doesn't end with a "
 492                "barrier instruction!", MBB);
 493       } else if (!MBB->back().getDesc().isTerminator()) {
 494         report("MBB exits via conditional branch/branch but the branch "
 495                "isn't a terminator instruction!", MBB);
 496       }
 497       if (Cond.empty()) {
 498         report("MBB exits via conditinal branch/branch but there's no "
 499                "condition!", MBB);
 500       }
 501     } else {
 502       report("AnalyzeBranch returned invalid data!", MBB);
 503     }
 504   }
 505
 506   regsLive.clear();
 507   for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
 508          E = MBB->livein_end(); I != E; ++I) {
 509     if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
 510       report("MBB live-in list contains non-physical register", MBB);
 511       continue;
 512     }
 513     regsLive.insert(*I);
 514     for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
 515       regsLive.insert(*R);
 516   }
 517   regsLiveInButUnused = regsLive;
 518
 519   const MachineFrameInfo *MFI = MF->getFrameInfo();
 520   assert(MFI && "Function has no frame info");
 521   BitVector PR = MFI->getPristineRegs(MBB);
 522   for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
 523     regsLive.insert(I);
 524     for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
 525       regsLive.insert(*R);
 526   }
 527
 528   regsKilled.clear();
 529   regsDefined.clear();
 530
 531   if (Indexes)
 532     lastIndex = Indexes->getMBBStartIdx(MBB);
 533 }
 534
 535 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
 536   const TargetInstrDesc &TI = MI->getDesc();
 537   if (MI->getNumOperands() < TI.getNumOperands()) {
 538     report("Too few operands", MI);
 539     *OS << TI.getNumOperands() << " operands expected, but "
 540         << MI->getNumExplicitOperands() << " given.\n";
 541   }
 542
 543   // Check the MachineMemOperands for basic consistency.
 544   for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
 545        E = MI->memoperands_end(); I != E; ++I) {
 546     if ((*I)->isLoad() && !TI.mayLoad())
 547       report("Missing mayLoad flag", MI);
 548     if ((*I)->isStore() && !TI.mayStore())
 549       report("Missing mayStore flag", MI);
 550   }
 551
 552   // Debug values must not have a slot index.
 553   // Other instructions must have one.
 554   if (LiveInts) {
 555     bool mapped = !LiveInts->isNotInMIMap(MI);
 556     if (MI->isDebugValue()) {
 557       if (mapped)
 558         report("Debug instruction has a slot index", MI);
 559     } else {
 560       if (!mapped)
 561         report("Missing slot index", MI);
 562     }
 563   }
 564
 565 }
 566
 567 void
 568 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
 569   const MachineInstr *MI = MO->getParent();
 570   const TargetInstrDesc &TI = MI->getDesc();
 571   const TargetOperandInfo &TOI = TI.OpInfo[MONum];
 572
 573   // The first TI.NumDefs operands must be explicit register defines
 574   if (MONum < TI.getNumDefs()) {
 575     if (!MO->isReg())
 576       report("Explicit definition must be a register", MO, MONum);
 577     else if (!MO->isDef())
 578       report("Explicit definition marked as use", MO, MONum);
 579     else if (MO->isImplicit())
 580       report("Explicit definition marked as implicit", MO, MONum);
 581   } else if (MONum < TI.getNumOperands()) {
 582     // Don't check if it's the last operand in a variadic instruction. See,
 583     // e.g., LDM_RET in the arm back end.
 584     if (MO->isReg() && !(TI.isVariadic() && MONum == TI.getNumOperands()-1)) {
 585       if (MO->isDef() && !TOI.isOptionalDef())
 586           report("Explicit operand marked as def", MO, MONum);
 587       if (MO->isImplicit())
 588         report("Explicit operand marked as implicit", MO, MONum);
 589     }
 590   } else {
 591     // ARM adds %reg0 operands to indicate predicates. We'll allow that.
 592     if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())
 593       report("Extra explicit operand on non-variadic instruction", MO, MONum);
 594   }
 595
 596   switch (MO->getType()) {
 597   case MachineOperand::MO_Register: {
 598     const unsigned Reg = MO->getReg();
 599     if (!Reg)
 600       return;
 601
 602     // Check Live Variables.
 603     if (MI->isDebugValue()) {
 604       // Liveness checks are not valid for debug values.
 605     } else if (MO->isUndef()) {
 606       // An <undef> doesn't refer to any register, so just skip it.
 607     } else if (MO->isUse()) {
 608       regsLiveInButUnused.erase(Reg);
 609
 610       bool isKill = false;
 611       unsigned defIdx;
 612       if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
 613         // A two-addr use counts as a kill if use and def are the same.
 614         unsigned DefReg = MI->getOperand(defIdx).getReg();
 615         if (Reg == DefReg) {
 616           isKill = true;
 617           // And in that case an explicit kill flag is not allowed.
 618           if (MO->isKill())
 619             report("Illegal kill flag on two-address instruction operand",
 620                    MO, MONum);
 621         } else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
 622           report("Two-address instruction operands must be identical",
 623                  MO, MONum);
 624         }
 625       } else
 626         isKill = MO->isKill();
 627
 628       if (isKill)
 629         addRegWithSubRegs(regsKilled, Reg);
 630
 631       // Check that LiveVars knows this kill.
 632       if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
 633           MO->isKill()) {
 634         LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
 635         if (std::find(VI.Kills.begin(),
 636                       VI.Kills.end(), MI) == VI.Kills.end())
 637           report("Kill missing from LiveVariables", MO, MONum);
 638       }
 639
 640       // Check LiveInts liveness and kill.
 641       if (TargetRegisterInfo::isVirtualRegister(Reg) &&
 642           LiveInts && !LiveInts->isNotInMIMap(MI)) {
 643         SlotIndex UseIdx = LiveInts->getInstructionIndex(MI).getUseIndex();
 644         if (LiveInts->hasInterval(Reg)) {
 645           const LiveInterval &LI = LiveInts->getInterval(Reg);
 646           if (!LI.liveAt(UseIdx)) {
 647             report("No live range at use", MO, MONum);
 648             *OS << UseIdx << " is not live in " << LI << '\n';
 649           }
 650           // Check for extra kill flags.
 651           // Note that we allow missing kill flags for now.
 652           if (MO->isKill() && !LI.killedAt(UseIdx.getDefIndex())) {
 653             report("Live range continues after kill flag", MO, MONum);
 654             *OS << "Live range: " << LI << '\n';
 655           }
 656         } else {
 657           report("Virtual register has no Live interval", MO, MONum);
 658         }
 659       }
 660
 661       // Use of a dead register.
 662       if (!regsLive.count(Reg)) {
 663         if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
 664           // Reserved registers may be used even when 'dead'.
 665           if (!isReserved(Reg))
 666             report("Using an undefined physical register", MO, MONum);
 667         } else {
 668           BBInfo &MInfo = MBBInfoMap[MI->getParent()];
 669           // We don't know which virtual registers are live in, so only complain
 670           // if vreg was killed in this MBB. Otherwise keep track of vregs that
 671           // must be live in. PHI instructions are handled separately.
 672           if (MInfo.regsKilled.count(Reg))
 673             report("Using a killed virtual register", MO, MONum);
 674           else if (!MI->isPHI())
 675             MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
 676         }
 677       }
 678     } else {
 679       assert(MO->isDef());
 680       // Register defined.
 681       // TODO: verify that earlyclobber ops are not used.
 682       if (MO->isDead())
 683         addRegWithSubRegs(regsDead, Reg);
 684       else
 685         addRegWithSubRegs(regsDefined, Reg);
 686
 687       // Check LiveInts for a live range, but only for virtual registers.
 688       if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
 689           !LiveInts->isNotInMIMap(MI)) {
 690         SlotIndex DefIdx = LiveInts->getInstructionIndex(MI).getDefIndex();
 691         if (LiveInts->hasInterval(Reg)) {
 692           const LiveInterval &LI = LiveInts->getInterval(Reg);
 693           if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
 694             assert(VNI && "NULL valno is not allowed");
 695             if (VNI->def != DefIdx && !MO->isEarlyClobber()) {
 696               report("Inconsistent valno->def", MO, MONum);
 697               *OS << "Valno " << VNI->id << " is not defined at "
 698                   << DefIdx << " in " << LI << '\n';
 699             }
 700           } else {
 701             report("No live range at def", MO, MONum);
 702             *OS << DefIdx << " is not live in " << LI << '\n';
 703           }
 704         } else {
 705           report("Virtual register has no Live interval", MO, MONum);
 706         }
 707       }
 708     }
 709
 710     // Check register classes.
 711     if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
 712       unsigned SubIdx = MO->getSubReg();
 713
 714       if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
 715         unsigned sr = Reg;
 716         if (SubIdx) {
 717           unsigned s = TRI->getSubReg(Reg, SubIdx);
 718           if (!s) {
 719             report("Invalid subregister index for physical register",
 720                    MO, MONum);
 721             return;
 722           }
 723           sr = s;
 724         }
 725         if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
 726           if (!DRC->contains(sr)) {
 727             report("Illegal physical register for instruction", MO, MONum);
 728             *OS << TRI->getName(sr) << " is not a "
 729                 << DRC->getName() << " register.\n";
 730           }
 731         }
 732       } else {
 733         // Virtual register.
 734         const TargetRegisterClass *RC = MRI->getRegClass(Reg);
 735         if (SubIdx) {
 736           const TargetRegisterClass *SRC = RC->getSubRegisterRegClass(SubIdx);
 737           if (!SRC) {
 738             report("Invalid subregister index for virtual register", MO, MONum);
 739             *OS << "Register class " << RC->getName()
 740                 << " does not support subreg index " << SubIdx << "\n";
 741             return;
 742           }
 743           RC = SRC;
 744         }
 745         if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
 746           if (RC != DRC && !RC->hasSuperClass(DRC)) {
 747             report("Illegal virtual register for instruction", MO, MONum);
 748             *OS << "Expected a " << DRC->getName() << " register, but got a "
 749                 << RC->getName() << " register\n";
 750           }
 751         }
 752       }
 753     }
 754     break;
 755   }
 756
 757   case MachineOperand::MO_MachineBasicBlock:
 758     if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
 759       report("PHI operand is not in the CFG", MO, MONum);
 760     break;
 761
 762   case MachineOperand::MO_FrameIndex:
 763     if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
 764         LiveInts && !LiveInts->isNotInMIMap(MI)) {
 765       LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
 766       SlotIndex Idx = LiveInts->getInstructionIndex(MI);
 767       if (TI.mayLoad() && !LI.liveAt(Idx.getUseIndex())) {
 768         report("Instruction loads from dead spill slot", MO, MONum);
 769         *OS << "Live stack: " << LI << '\n';
 770       }
 771       if (TI.mayStore() && !LI.liveAt(Idx.getDefIndex())) {
 772         report("Instruction stores to dead spill slot", MO, MONum);
 773         *OS << "Live stack: " << LI << '\n';
 774       }
 775     }
 776     break;
 777
 778   default:
 779     break;
 780   }
 781 }
 782
 783 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
 784   BBInfo &MInfo = MBBInfoMap[MI->getParent()];
 785   set_union(MInfo.regsKilled, regsKilled);
 786   set_subtract(regsLive, regsKilled); regsKilled.clear();
 787   set_subtract(regsLive, regsDead);   regsDead.clear();
 788   set_union(regsLive, regsDefined);   regsDefined.clear();
 789
 790   if (Indexes && Indexes->hasIndex(MI)) {
 791     SlotIndex idx = Indexes->getInstructionIndex(MI);
 792     if (!(idx > lastIndex)) {
 793       report("Instruction index out of order", MI);
 794       *OS << "Last instruction was at " << lastIndex << '\n';
 795     }
 796     lastIndex = idx;
 797   }
 798 }
 799
 800 void
 801 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
 802   MBBInfoMap[MBB].regsLiveOut = regsLive;
 803   regsLive.clear();
 804
 805   if (Indexes) {
 806     SlotIndex stop = Indexes->getMBBEndIdx(MBB);
 807     if (!(stop > lastIndex)) {
 808       report("Block ends before last instruction index", MBB);
 809       *OS << "Block ends at " << stop
 810           << " last instruction was at " << lastIndex << '\n';
 811     }
 812     lastIndex = stop;
 813   }
 814 }
 815
 816 // Calculate the largest possible vregsPassed sets. These are the registers that
 817 // can pass through an MBB live, but may not be live every time. It is assumed
 818 // that all vregsPassed sets are empty before the call.
 819 void MachineVerifier::calcRegsPassed() {
 820   // First push live-out regs to successors' vregsPassed. Remember the MBBs that
 821   // have any vregsPassed.
 822   DenseSet<const MachineBasicBlock*> todo;
 823   for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
 824        MFI != MFE; ++MFI) {
 825     const MachineBasicBlock &MBB(*MFI);
 826     BBInfo &MInfo = MBBInfoMap[&MBB];
 827     if (!MInfo.reachable)
 828       continue;
 829     for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
 830            SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
 831       BBInfo &SInfo = MBBInfoMap[*SuI];
 832       if (SInfo.addPassed(MInfo.regsLiveOut))
 833         todo.insert(*SuI);
 834     }
 835   }
 836
 837   // Iteratively push vregsPassed to successors. This will converge to the same
 838   // final state regardless of DenseSet iteration order.
 839   while (!todo.empty()) {
 840     const MachineBasicBlock *MBB = *todo.begin();
 841     todo.erase(MBB);
 842     BBInfo &MInfo = MBBInfoMap[MBB];
 843     for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
 844            SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
 845       if (*SuI == MBB)
 846         continue;
 847       BBInfo &SInfo = MBBInfoMap[*SuI];
 848       if (SInfo.addPassed(MInfo.vregsPassed))
 849         todo.insert(*SuI);
 850     }
 851   }
 852 }
 853
 854 // Calculate the set of virtual registers that must be passed through each basic
 855 // block in order to satisfy the requirements of successor blocks. This is very
 856 // similar to calcRegsPassed, only backwards.
 857 void MachineVerifier::calcRegsRequired() {
 858   // First push live-in regs to predecessors' vregsRequired.
 859   DenseSet<const MachineBasicBlock*> todo;
 860   for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
 861        MFI != MFE; ++MFI) {
 862     const MachineBasicBlock &MBB(*MFI);
 863     BBInfo &MInfo = MBBInfoMap[&MBB];
 864     for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
 865            PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
 866       BBInfo &PInfo = MBBInfoMap[*PrI];
 867       if (PInfo.addRequired(MInfo.vregsLiveIn))
 868         todo.insert(*PrI);
 869     }
 870   }
 871
 872   // Iteratively push vregsRequired to predecessors. This will converge to the
 873   // same final state regardless of DenseSet iteration order.
 874   while (!todo.empty()) {
 875     const MachineBasicBlock *MBB = *todo.begin();
 876     todo.erase(MBB);
 877     BBInfo &MInfo = MBBInfoMap[MBB];
 878     for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
 879            PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
 880       if (*PrI == MBB)
 881         continue;
 882       BBInfo &SInfo = MBBInfoMap[*PrI];
 883       if (SInfo.addRequired(MInfo.vregsRequired))
 884         todo.insert(*PrI);
 885     }
 886   }
 887 }
 888
 889 // Check PHI instructions at the beginning of MBB. It is assumed that
 890 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
 891 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
 892   for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
 893        BBI != BBE && BBI->isPHI(); ++BBI) {
 894     DenseSet<const MachineBasicBlock*> seen;
 895
 896     for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
 897       unsigned Reg = BBI->getOperand(i).getReg();
 898       const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
 899       if (!Pre->isSuccessor(MBB))
 900         continue;
 901       seen.insert(Pre);
 902       BBInfo &PrInfo = MBBInfoMap[Pre];
 903       if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
 904         report("PHI operand is not live-out from predecessor",
 905                &BBI->getOperand(i), i);
 906     }
 907
 908     // Did we see all predecessors?
 909     for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
 910            PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
 911       if (!seen.count(*PrI)) {
 912         report("Missing PHI operand", BBI);
 913         *OS << "BB#" << (*PrI)->getNumber()
 914             << " is a predecessor according to the CFG.\n";
 915       }
 916     }
 917   }
 918 }
 919
 920 void MachineVerifier::visitMachineFunctionAfter() {
 921   calcRegsPassed();
 922
 923   for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
 924        MFI != MFE; ++MFI) {
 925     BBInfo &MInfo = MBBInfoMap[MFI];
 926
 927     // Skip unreachable MBBs.
 928     if (!MInfo.reachable)
 929       continue;
 930
 931     checkPHIOps(MFI);
 932   }
 933
 934   // Now check liveness info if available
 935   if (LiveVars || LiveInts)
 936     calcRegsRequired();
 937   if (LiveVars)
 938     verifyLiveVariables();
 939   if (LiveInts)
 940     verifyLiveIntervals();
 941 }
 942
 943 void MachineVerifier::verifyLiveVariables() {
 944   assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
 945   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
 946     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
 947     LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
 948     for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
 949          MFI != MFE; ++MFI) {
 950       BBInfo &MInfo = MBBInfoMap[MFI];
 951
 952       // Our vregsRequired should be identical to LiveVariables' AliveBlocks
 953       if (MInfo.vregsRequired.count(Reg)) {
 954         if (!VI.AliveBlocks.test(MFI->getNumber())) {
 955           report("LiveVariables: Block missing from AliveBlocks", MFI);
 956           *OS << "Virtual register " << PrintReg(Reg)
 957               << " must be live through the block.\n";
 958         }
 959       } else {
 960         if (VI.AliveBlocks.test(MFI->getNumber())) {
 961           report("LiveVariables: Block should not be in AliveBlocks", MFI);
 962           *OS << "Virtual register " << PrintReg(Reg)
 963               << " is not needed live through the block.\n";
 964         }
 965       }
 966     }
 967   }
 968 }
 969
 970 void MachineVerifier::verifyLiveIntervals() {
 971   assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
 972   for (LiveIntervals::const_iterator LVI = LiveInts->begin(),
 973        LVE = LiveInts->end(); LVI != LVE; ++LVI) {
 974     const LiveInterval &LI = *LVI->second;
 975
 976     // Spilling and splitting may leave unused registers around. Skip them.
 977     if (MRI->use_empty(LI.reg))
 978       continue;
 979
 980     // Physical registers have much weirdness going on, mostly from coalescing.
 981     // We should probably fix it, but for now just ignore them.
 982     if (TargetRegisterInfo::isPhysicalRegister(LI.reg))
 983       continue;
 984
 985     assert(LVI->first == LI.reg && "Invalid reg to interval mapping");
 986
 987     for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
 988          I!=E; ++I) {
 989       VNInfo *VNI = *I;
 990       const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def);
 991
 992       if (!DefVNI) {
 993         if (!VNI->isUnused()) {
 994           report("Valno not live at def and not marked unused", MF);
 995           *OS << "Valno #" << VNI->id << " in " << LI << '\n';
 996         }
 997         continue;
 998       }
 999
1000       if (VNI->isUnused())
1001         continue;
1002
1003       if (DefVNI != VNI) {
1004         report("Live range at def has different valno", MF);
1005         *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1006             << " where valno #" << DefVNI->id << " is live in " << LI << '\n';
1007         continue;
1008       }
1009
1010       const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
1011       if (!MBB) {
1012         report("Invalid definition index", MF);
1013         *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1014             << " in " << LI << '\n';
1015         continue;
1016       }
1017
1018       if (VNI->isPHIDef()) {
1019         if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
1020           report("PHIDef value is not defined at MBB start", MF);
1021           *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1022               << ", not at the beginning of BB#" << MBB->getNumber()
1023               << " in " << LI << '\n';
1024         }
1025       } else {
1026         // Non-PHI def.
1027         const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
1028         if (!MI) {
1029           report("No instruction at def index", MF);
1030           *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1031               << " in " << LI << '\n';
1032         } else if (!MI->modifiesRegister(LI.reg, TRI)) {
1033           report("Defining instruction does not modify register", MI);
1034           *OS << "Valno #" << VNI->id << " in " << LI << '\n';
1035         }
1036
1037         bool isEarlyClobber = false;
1038         if (MI) {
1039           for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
1040                MOE = MI->operands_end(); MOI != MOE; ++MOI) {
1041             if (MOI->isReg() && MOI->getReg() == LI.reg && MOI->isDef() &&
1042                 MOI->isEarlyClobber()) {
1043               isEarlyClobber = true;
1044               break;
1045             }
1046           }
1047         }
1048
1049         // Early clobber defs begin at USE slots, but other defs must begin at
1050         // DEF slots.
1051         if (isEarlyClobber) {
1052           if (!VNI->def.isUse()) {
1053             report("Early clobber def must be at a USE slot", MF);
1054             *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1055                 << " in " << LI << '\n';
1056           }
1057         } else if (!VNI->def.isDef()) {
1058           report("Non-PHI, non-early clobber def must be at a DEF slot", MF);
1059           *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1060               << " in " << LI << '\n';
1061         }
1062       }
1063     }
1064
1065     for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) {
1066       const VNInfo *VNI = I->valno;
1067       assert(VNI && "Live range has no valno");
1068
1069       if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) {
1070         report("Foreign valno in live range", MF);
1071         I->print(*OS);
1072         *OS << " has a valno not in " << LI << '\n';
1073       }
1074
1075       if (VNI->isUnused()) {
1076         report("Live range valno is marked unused", MF);
1077         I->print(*OS);
1078         *OS << " in " << LI << '\n';
1079       }
1080
1081       const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start);
1082       if (!MBB) {
1083         report("Bad start of live segment, no basic block", MF);
1084         I->print(*OS);
1085         *OS << " in " << LI << '\n';
1086         continue;
1087       }
1088       SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1089       if (I->start != MBBStartIdx && I->start != VNI->def) {
1090         report("Live segment must begin at MBB entry or valno def", MBB);
1091         I->print(*OS);
1092         *OS << " in " << LI << '\n' << "Basic block starts at "
1093             << MBBStartIdx << '\n';
1094       }
1095
1096       const MachineBasicBlock *EndMBB =
1097                                 LiveInts->getMBBFromIndex(I->end.getPrevSlot());
1098       if (!EndMBB) {
1099         report("Bad end of live segment, no basic block", MF);
1100         I->print(*OS);
1101         *OS << " in " << LI << '\n';
1102         continue;
1103       }
1104       if (I->end != LiveInts->getMBBEndIdx(EndMBB)) {
1105         // The live segment is ending inside EndMBB
1106         const MachineInstr *MI =
1107                         LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
1108         if (!MI) {
1109           report("Live segment doesn't end at a valid instruction", EndMBB);
1110         I->print(*OS);
1111         *OS << " in " << LI << '\n' << "Basic block starts at "
1112             << MBBStartIdx << '\n';
1113         } else if (TargetRegisterInfo::isVirtualRegister(LI.reg) &&
1114                    !MI->readsVirtualRegister(LI.reg)) {
1115           // A live range can end with either a redefinition, a kill flag on a
1116           // use, or a dead flag on a def.
1117           // FIXME: Should we check for each of these?
1118           bool hasDeadDef = false;
1119           for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
1120                MOE = MI->operands_end(); MOI != MOE; ++MOI) {
1121             if (MOI->isReg() && MOI->getReg() == LI.reg && MOI->isDef() && MOI->isDead()) {
1122               hasDeadDef = true;
1123               break;
1124             }
1125           }
1126
1127           if (!hasDeadDef) {
1128             report("Instruction killing live segment neither defines nor reads "
1129                    "register", MI);
1130             I->print(*OS);
1131             *OS << " in " << LI << '\n';
1132           }
1133         }
1134       }
1135
1136       // Now check all the basic blocks in this live segment.
1137       MachineFunction::const_iterator MFI = MBB;
1138       // Is this live range the beginning of a non-PHIDef VN?
1139       if (I->start == VNI->def && !VNI->isPHIDef()) {
1140         // Not live-in to any blocks.
1141         if (MBB == EndMBB)
1142           continue;
1143         // Skip this block.
1144         ++MFI;
1145       }
1146       for (;;) {
1147         assert(LiveInts->isLiveInToMBB(LI, MFI));
1148         // We don't know how to track physregs into a landing pad.
1149         if (TargetRegisterInfo::isPhysicalRegister(LI.reg) &&
1150             MFI->isLandingPad()) {
1151           if (&*MFI == EndMBB)
1152             break;
1153           ++MFI;
1154           continue;
1155         }
1156         // Check that VNI is live-out of all predecessors.
1157         for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
1158              PE = MFI->pred_end(); PI != PE; ++PI) {
1159           SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI).getPrevSlot();
1160           const VNInfo *PVNI = LI.getVNInfoAt(PEnd);
1161
1162           if (VNI->isPHIDef() && VNI->def == LiveInts->getMBBStartIdx(MFI)) {
1163             if (PVNI && !PVNI->hasPHIKill()) {
1164               report("Value live out of predecessor doesn't have PHIKill", MF);
1165               *OS << "Valno #" << PVNI->id << " live out of BB#"
1166                   << (*PI)->getNumber() << '@' << PEnd
1167                   << " doesn't have PHIKill, but Valno #" << VNI->id
1168                   << " is PHIDef and defined at the beginning of BB#"
1169                   << MFI->getNumber() << '@' << LiveInts->getMBBStartIdx(MFI)
1170                   << " in " << LI << '\n';
1171             }
1172             continue;
1173           }
1174
1175           if (!PVNI) {
1176             report("Register not marked live out of predecessor", *PI);
1177             *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1178                 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live at "
1179                 << PEnd << " in " << LI << '\n';
1180             continue;
1181           }
1182
1183           if (PVNI != VNI) {
1184             report("Different value live out of predecessor", *PI);
1185             *OS << "Valno #" << PVNI->id << " live out of BB#"
1186                 << (*PI)->getNumber() << '@' << PEnd
1187                 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
1188                 << '@' << LiveInts->getMBBStartIdx(MFI) << " in " << LI << '\n';
1189           }
1190         }
1191         if (&*MFI == EndMBB)
1192           break;
1193         ++MFI;
1194       }
1195     }
1196
1197     // Check the LI only has one connected component.
1198     if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1199       ConnectedVNInfoEqClasses ConEQ(*LiveInts);
1200       unsigned NumComp = ConEQ.Classify(&LI);
1201       if (NumComp > 1) {
1202         report("Multiple connected components in live interval", MF);
1203         *OS << NumComp << " components in " << LI << '\n';
1204         for (unsigned comp = 0; comp != NumComp; ++comp) {
1205           *OS << comp << ": valnos";
1206           for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
1207                E = LI.vni_end(); I!=E; ++I)
1208             if (comp == ConEQ.getEqClass(*I))
1209               *OS << ' ' << (*I)->id;
1210           *OS << '\n';
1211         }
1212       }
1213     }
1214   }
1215 }
1216