1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
26 // runEnums - Print out enum values for all of the registers.
27 void RegisterInfoEmitter::runEnums(raw_ostream
&OS
) {
28 CodeGenTarget
Target(Records
);
29 const std::vector
<CodeGenRegister
> &Registers
= Target
.getRegisters();
31 std::string Namespace
= Registers
[0].TheDef
->getValueAsString("Namespace");
33 EmitSourceFileHeader("Target Register Enum Values", OS
);
34 OS
<< "namespace llvm {\n\n";
36 if (!Namespace
.empty())
37 OS
<< "namespace " << Namespace
<< " {\n";
38 OS
<< "enum {\n NoRegister,\n";
40 for (unsigned i
= 0, e
= Registers
.size(); i
!= e
; ++i
)
41 OS
<< " " << Registers
[i
].getName() << ", \t// " << i
+1 << "\n";
42 OS
<< " NUM_TARGET_REGS \t// " << Registers
.size()+1 << "\n";
44 if (!Namespace
.empty())
47 const std::vector
<Record
*> SubRegIndices
= Target
.getSubRegIndices();
48 if (!SubRegIndices
.empty()) {
49 OS
<< "\n// Subregister indices\n";
50 Namespace
= SubRegIndices
[0]->getValueAsString("Namespace");
51 if (!Namespace
.empty())
52 OS
<< "namespace " << Namespace
<< " {\n";
53 OS
<< "enum {\n NoSubRegister,\n";
54 for (unsigned i
= 0, e
= SubRegIndices
.size(); i
!= e
; ++i
)
55 OS
<< " " << SubRegIndices
[i
]->getName() << ",\t// " << i
+1 << "\n";
56 OS
<< " NUM_TARGET_SUBREGS = " << SubRegIndices
.size()+1 << "\n";
58 if (!Namespace
.empty())
61 OS
<< "} // End llvm namespace \n";
64 void RegisterInfoEmitter::runHeader(raw_ostream
&OS
) {
65 EmitSourceFileHeader("Register Information Header Fragment", OS
);
66 CodeGenTarget
Target(Records
);
67 const std::string
&TargetName
= Target
.getName();
68 std::string ClassName
= TargetName
+ "GenRegisterInfo";
70 OS
<< "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
71 OS
<< "#include <string>\n\n";
73 OS
<< "namespace llvm {\n\n";
75 OS
<< "struct " << ClassName
<< " : public TargetRegisterInfo {\n"
76 << " explicit " << ClassName
77 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
78 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
79 << "unsigned Flavour) const;\n"
80 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
81 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
82 << " { return false; }\n"
83 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
84 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
85 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
88 const std::vector
<CodeGenRegisterClass
> &RegisterClasses
=
89 Target
.getRegisterClasses();
91 if (!RegisterClasses
.empty()) {
92 OS
<< "namespace " << RegisterClasses
[0].Namespace
93 << " { // Register classes\n";
96 for (unsigned i
= 0, e
= RegisterClasses
.size(); i
!= e
; ++i
) {
98 OS
<< " " << RegisterClasses
[i
].getName() << "RegClassID";
103 for (unsigned i
= 0, e
= RegisterClasses
.size(); i
!= e
; ++i
) {
104 const std::string
&Name
= RegisterClasses
[i
].getName();
106 // Output the register class definition.
107 OS
<< " struct " << Name
<< "Class : public TargetRegisterClass {\n"
108 << " " << Name
<< "Class();\n"
109 << RegisterClasses
[i
].MethodProtos
<< " };\n";
111 // Output the extern for the instance.
112 OS
<< " extern " << Name
<< "Class\t" << Name
<< "RegClass;\n";
113 // Output the extern for the pointer to the instance (should remove).
114 OS
<< " static TargetRegisterClass * const "<< Name
<<"RegisterClass = &"
115 << Name
<< "RegClass;\n";
117 OS
<< "} // end of namespace " << TargetName
<< "\n\n";
119 OS
<< "} // End llvm namespace \n";
122 static void addSuperReg(Record
*R
, Record
*S
,
123 std::map
<Record
*, std::set
<Record
*>, LessRecord
> &SubRegs
,
124 std::map
<Record
*, std::set
<Record
*>, LessRecord
> &SuperRegs
,
125 std::map
<Record
*, std::set
<Record
*>, LessRecord
> &Aliases
) {
127 errs() << "Error: recursive sub-register relationship between"
128 << " register " << getQualifiedName(R
)
129 << " and its sub-registers?\n";
132 if (!SuperRegs
[R
].insert(S
).second
)
134 SubRegs
[S
].insert(R
);
135 Aliases
[R
].insert(S
);
136 Aliases
[S
].insert(R
);
137 if (SuperRegs
.count(S
))
138 for (std::set
<Record
*>::iterator I
= SuperRegs
[S
].begin(),
139 E
= SuperRegs
[S
].end(); I
!= E
; ++I
)
140 addSuperReg(R
, *I
, SubRegs
, SuperRegs
, Aliases
);
143 static void addSubSuperReg(Record
*R
, Record
*S
,
144 std::map
<Record
*, std::set
<Record
*>, LessRecord
> &SubRegs
,
145 std::map
<Record
*, std::set
<Record
*>, LessRecord
> &SuperRegs
,
146 std::map
<Record
*, std::set
<Record
*>, LessRecord
> &Aliases
) {
148 errs() << "Error: recursive sub-register relationship between"
149 << " register " << getQualifiedName(R
)
150 << " and its sub-registers?\n";
154 if (!SubRegs
[R
].insert(S
).second
)
156 addSuperReg(S
, R
, SubRegs
, SuperRegs
, Aliases
);
157 Aliases
[R
].insert(S
);
158 Aliases
[S
].insert(R
);
159 if (SubRegs
.count(S
))
160 for (std::set
<Record
*>::iterator I
= SubRegs
[S
].begin(),
161 E
= SubRegs
[S
].end(); I
!= E
; ++I
)
162 addSubSuperReg(R
, *I
, SubRegs
, SuperRegs
, Aliases
);
165 struct RegisterMaps
{
166 // Map SubRegIndex -> Register
167 typedef std::map
<Record
*, Record
*, LessRecord
> SubRegMap
;
168 // Map Register -> SubRegMap
169 typedef std::map
<Record
*, SubRegMap
> SubRegMaps
;
172 SubRegMap
&inferSubRegIndices(Record
*Reg
);
174 // Composite SubRegIndex instances.
175 // Map (SubRegIndex,SubRegIndex) -> SubRegIndex
176 typedef DenseMap
<std::pair
<Record
*,Record
*>,Record
*> CompositeMap
;
177 CompositeMap Composite
;
179 // Compute SubRegIndex compositions after inferSubRegIndices has run on all
181 void computeComposites();
184 // Calculate all subregindices for Reg. Loopy subregs cause infinite recursion.
185 RegisterMaps::SubRegMap
&RegisterMaps::inferSubRegIndices(Record
*Reg
) {
186 SubRegMap
&SRM
= SubReg
[Reg
];
189 std::vector
<Record
*> SubRegs
= Reg
->getValueAsListOfDefs("SubRegs");
190 std::vector
<Record
*> Indices
= Reg
->getValueAsListOfDefs("SubRegIndices");
191 if (SubRegs
.size() != Indices
.size())
192 throw "Register " + Reg
->getName() + " SubRegIndices doesn't match SubRegs";
194 // First insert the direct subregs and make sure they are fully indexed.
195 for (unsigned i
= 0, e
= SubRegs
.size(); i
!= e
; ++i
) {
196 if (!SRM
.insert(std::make_pair(Indices
[i
], SubRegs
[i
])).second
)
197 throw "SubRegIndex " + Indices
[i
]->getName()
198 + " appears twice in Register " + Reg
->getName();
199 inferSubRegIndices(SubRegs
[i
]);
202 // Keep track of inherited subregs and how they can be reached.
203 // Register -> (SubRegIndex, SubRegIndex)
204 typedef std::map
<Record
*, std::pair
<Record
*,Record
*>, LessRecord
> OrphanMap
;
207 // Clone inherited subregs. Here the order is important - earlier subregs take
209 for (unsigned i
= 0, e
= SubRegs
.size(); i
!= e
; ++i
) {
210 SubRegMap
&M
= SubReg
[SubRegs
[i
]];
211 for (SubRegMap::iterator si
= M
.begin(), se
= M
.end(); si
!= se
; ++si
)
212 if (!SRM
.insert(*si
).second
)
213 Orphans
[si
->second
] = std::make_pair(Indices
[i
], si
->first
);
216 // Finally process the composites.
217 ListInit
*Comps
= Reg
->getValueAsListInit("CompositeIndices");
218 for (unsigned i
= 0, e
= Comps
->size(); i
!= e
; ++i
) {
219 DagInit
*Pat
= dynamic_cast<DagInit
*>(Comps
->getElement(i
));
221 throw "Invalid dag '" + Comps
->getElement(i
)->getAsString()
222 + "' in CompositeIndices";
223 DefInit
*BaseIdxInit
= dynamic_cast<DefInit
*>(Pat
->getOperator());
224 if (!BaseIdxInit
|| !BaseIdxInit
->getDef()->isSubClassOf("SubRegIndex"))
225 throw "Invalid SubClassIndex in " + Pat
->getAsString();
227 // Resolve list of subreg indices into R2.
229 for (DagInit::const_arg_iterator di
= Pat
->arg_begin(),
230 de
= Pat
->arg_end(); di
!= de
; ++di
) {
231 DefInit
*IdxInit
= dynamic_cast<DefInit
*>(*di
);
232 if (!IdxInit
|| !IdxInit
->getDef()->isSubClassOf("SubRegIndex"))
233 throw "Invalid SubClassIndex in " + Pat
->getAsString();
234 SubRegMap::const_iterator ni
= SubReg
[R2
].find(IdxInit
->getDef());
235 if (ni
== SubReg
[R2
].end())
236 throw "Composite " + Pat
->getAsString() + " refers to bad index in "
241 // Insert composite index. Allow overriding inherited indices etc.
242 SRM
[BaseIdxInit
->getDef()] = R2
;
244 // R2 is now directly addressable, no longer an orphan.
248 // Now, Orphans contains the inherited subregisters without a direct index.
249 if (!Orphans
.empty()) {
250 errs() << "Error: Register " << getQualifiedName(Reg
)
251 << " inherited subregisters without an index:\n";
252 for (OrphanMap::iterator i
= Orphans
.begin(), e
= Orphans
.end(); i
!= e
;
254 errs() << " " << getQualifiedName(i
->first
)
255 << " = " << i
->second
.first
->getName()
256 << ", " << i
->second
.second
->getName() << "\n";
263 void RegisterMaps::computeComposites() {
264 for (SubRegMaps::const_iterator sri
= SubReg
.begin(), sre
= SubReg
.end();
266 Record
*Reg1
= sri
->first
;
267 const SubRegMap
&SRM1
= sri
->second
;
268 for (SubRegMap::const_iterator i1
= SRM1
.begin(), e1
= SRM1
.end();
270 Record
*Idx1
= i1
->first
;
271 Record
*Reg2
= i1
->second
;
272 // Ignore identity compositions.
275 // If Reg2 has no subregs, Idx1 doesn't compose.
276 if (!SubReg
.count(Reg2
))
278 const SubRegMap
&SRM2
= SubReg
[Reg2
];
279 // Try composing Idx1 with another SubRegIndex.
280 for (SubRegMap::const_iterator i2
= SRM2
.begin(), e2
= SRM2
.end();
282 std::pair
<Record
*,Record
*> IdxPair(Idx1
, i2
->first
);
283 Record
*Reg3
= i2
->second
;
284 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
285 for (SubRegMap::const_iterator i1d
= SRM1
.begin(), e1d
= SRM1
.end();
287 // Ignore identity compositions.
290 if (i1d
->second
== Reg3
) {
291 std::pair
<CompositeMap::iterator
,bool> Ins
=
292 Composite
.insert(std::make_pair(IdxPair
, i1d
->first
));
293 // Conflicting composition?
294 if (!Ins
.second
&& Ins
.first
->second
!= i1d
->first
) {
295 errs() << "Error: SubRegIndex " << getQualifiedName(Idx1
)
296 << " and " << getQualifiedName(IdxPair
.second
)
297 << " compose ambiguously as "
298 << getQualifiedName(Ins
.first
->second
) << " or "
299 << getQualifiedName(i1d
->first
) << "\n";
308 // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
309 // compositions, so remove any mappings of that form.
310 for (CompositeMap::iterator i
= Composite
.begin(), e
= Composite
.end();
312 CompositeMap::iterator j
= i
;
314 if (j
->first
.second
== j
->second
)
319 class RegisterSorter
{
321 std::map
<Record
*, std::set
<Record
*>, LessRecord
> &RegisterSubRegs
;
324 RegisterSorter(std::map
<Record
*, std::set
<Record
*>, LessRecord
> &RS
)
325 : RegisterSubRegs(RS
) {}
327 bool operator()(Record
*RegA
, Record
*RegB
) {
328 // B is sub-register of A.
329 return RegisterSubRegs
.count(RegA
) && RegisterSubRegs
[RegA
].count(RegB
);
333 // RegisterInfoEmitter::run - Main register file description emitter.
335 void RegisterInfoEmitter::run(raw_ostream
&OS
) {
336 CodeGenTarget
Target(Records
);
337 EmitSourceFileHeader("Register Information Source Fragment", OS
);
339 OS
<< "namespace llvm {\n\n";
341 // Start out by emitting each of the register classes... to do this, we build
342 // a set of registers which belong to a register class, this is to ensure that
343 // each register is only in a single register class.
345 const std::vector
<CodeGenRegisterClass
> &RegisterClasses
=
346 Target
.getRegisterClasses();
348 // Loop over all of the register classes... emitting each one.
349 OS
<< "namespace { // Register classes...\n";
351 // RegClassesBelongedTo - Keep track of which register classes each reg
353 std::multimap
<Record
*, const CodeGenRegisterClass
*> RegClassesBelongedTo
;
355 // Emit the register enum value arrays for each RegisterClass
356 for (unsigned rc
= 0, e
= RegisterClasses
.size(); rc
!= e
; ++rc
) {
357 const CodeGenRegisterClass
&RC
= RegisterClasses
[rc
];
359 // Give the register class a legal C name if it's anonymous.
360 std::string Name
= RC
.TheDef
->getName();
362 // Emit the register list now.
363 OS
<< " // " << Name
<< " Register Class...\n"
364 << " static const unsigned " << Name
366 for (unsigned i
= 0, e
= RC
.Elements
.size(); i
!= e
; ++i
) {
367 Record
*Reg
= RC
.Elements
[i
];
368 OS
<< getQualifiedName(Reg
) << ", ";
370 // Keep track of which regclasses this register is in.
371 RegClassesBelongedTo
.insert(std::make_pair(Reg
, &RC
));
376 // Emit the ValueType arrays for each RegisterClass
377 for (unsigned rc
= 0, e
= RegisterClasses
.size(); rc
!= e
; ++rc
) {
378 const CodeGenRegisterClass
&RC
= RegisterClasses
[rc
];
380 // Give the register class a legal C name if it's anonymous.
381 std::string Name
= RC
.TheDef
->getName() + "VTs";
383 // Emit the register list now.
385 << " Register Class Value Types...\n"
386 << " static const EVT " << Name
388 for (unsigned i
= 0, e
= RC
.VTs
.size(); i
!= e
; ++i
)
389 OS
<< getEnumName(RC
.VTs
[i
]) << ", ";
390 OS
<< "MVT::Other\n };\n\n";
392 OS
<< "} // end anonymous namespace\n\n";
394 // Now that all of the structs have been emitted, emit the instances.
395 if (!RegisterClasses
.empty()) {
396 OS
<< "namespace " << RegisterClasses
[0].Namespace
397 << " { // Register class instances\n";
398 for (unsigned i
= 0, e
= RegisterClasses
.size(); i
!= e
; ++i
)
399 OS
<< " " << RegisterClasses
[i
].getName() << "Class\t"
400 << RegisterClasses
[i
].getName() << "RegClass;\n";
402 std::map
<unsigned, std::set
<unsigned> > SuperClassMap
;
403 std::map
<unsigned, std::set
<unsigned> > SuperRegClassMap
;
406 unsigned NumSubRegIndices
= Target
.getSubRegIndices().size();
408 if (NumSubRegIndices
) {
409 // Emit the sub-register classes for each RegisterClass
410 for (unsigned rc
= 0, e
= RegisterClasses
.size(); rc
!= e
; ++rc
) {
411 const CodeGenRegisterClass
&RC
= RegisterClasses
[rc
];
412 std::vector
<Record
*> SRC(NumSubRegIndices
);
413 for (DenseMap
<Record
*,Record
*>::const_iterator
414 i
= RC
.SubRegClasses
.begin(),
415 e
= RC
.SubRegClasses
.end(); i
!= e
; ++i
) {
417 unsigned idx
= Target
.getSubRegIndexNo(i
->first
);
418 SRC
.at(idx
-1) = i
->second
;
420 // Find the register class number of i->second for SuperRegClassMap.
421 for (unsigned rc2
= 0, e2
= RegisterClasses
.size(); rc2
!= e2
; ++rc2
) {
422 const CodeGenRegisterClass
&RC2
= RegisterClasses
[rc2
];
423 if (RC2
.TheDef
== i
->second
) {
424 SuperRegClassMap
[rc2
].insert(rc
);
430 // Give the register class a legal C name if it's anonymous.
431 std::string Name
= RC
.TheDef
->getName();
434 << " Sub-register Classes...\n"
435 << " static const TargetRegisterClass* const "
436 << Name
<< "SubRegClasses[] = {\n ";
438 for (unsigned idx
= 0; idx
!= NumSubRegIndices
; ++idx
) {
442 OS
<< "&" << getQualifiedName(SRC
[idx
]) << "RegClass";
449 // Emit the super-register classes for each RegisterClass
450 for (unsigned rc
= 0, e
= RegisterClasses
.size(); rc
!= e
; ++rc
) {
451 const CodeGenRegisterClass
&RC
= RegisterClasses
[rc
];
453 // Give the register class a legal C name if it's anonymous.
454 std::string Name
= RC
.TheDef
->getName();
457 << " Super-register Classes...\n"
458 << " static const TargetRegisterClass* const "
459 << Name
<< "SuperRegClasses[] = {\n ";
462 std::map
<unsigned, std::set
<unsigned> >::iterator I
=
463 SuperRegClassMap
.find(rc
);
464 if (I
!= SuperRegClassMap
.end()) {
465 for (std::set
<unsigned>::iterator II
= I
->second
.begin(),
466 EE
= I
->second
.end(); II
!= EE
; ++II
) {
467 const CodeGenRegisterClass
&RC2
= RegisterClasses
[*II
];
470 OS
<< "&" << getQualifiedName(RC2
.TheDef
) << "RegClass";
475 OS
<< (!Empty
? ", " : "") << "NULL";
479 // No subregindices in this target
480 OS
<< " static const TargetRegisterClass* const "
481 << "NullRegClasses[] = { NULL };\n\n";
484 // Emit the sub-classes array for each RegisterClass
485 for (unsigned rc
= 0, e
= RegisterClasses
.size(); rc
!= e
; ++rc
) {
486 const CodeGenRegisterClass
&RC
= RegisterClasses
[rc
];
488 // Give the register class a legal C name if it's anonymous.
489 std::string Name
= RC
.TheDef
->getName();
492 << " Register Class sub-classes...\n"
493 << " static const TargetRegisterClass* const "
494 << Name
<< "Subclasses[] = {\n ";
497 for (unsigned rc2
= 0, e2
= RegisterClasses
.size(); rc2
!= e2
; ++rc2
) {
498 const CodeGenRegisterClass
&RC2
= RegisterClasses
[rc2
];
500 // Sub-classes are used to determine if a virtual register can be used
501 // as an instruction operand, or if it must be copied first.
502 if (rc
== rc2
|| !RC
.hasSubClass(&RC2
)) continue;
504 if (!Empty
) OS
<< ", ";
505 OS
<< "&" << getQualifiedName(RC2
.TheDef
) << "RegClass";
508 std::map
<unsigned, std::set
<unsigned> >::iterator SCMI
=
509 SuperClassMap
.find(rc2
);
510 if (SCMI
== SuperClassMap
.end()) {
511 SuperClassMap
.insert(std::make_pair(rc2
, std::set
<unsigned>()));
512 SCMI
= SuperClassMap
.find(rc2
);
514 SCMI
->second
.insert(rc
);
517 OS
<< (!Empty
? ", " : "") << "NULL";
521 for (unsigned rc
= 0, e
= RegisterClasses
.size(); rc
!= e
; ++rc
) {
522 const CodeGenRegisterClass
&RC
= RegisterClasses
[rc
];
524 // Give the register class a legal C name if it's anonymous.
525 std::string Name
= RC
.TheDef
->getName();
528 << " Register Class super-classes...\n"
529 << " static const TargetRegisterClass* const "
530 << Name
<< "Superclasses[] = {\n ";
533 std::map
<unsigned, std::set
<unsigned> >::iterator I
=
534 SuperClassMap
.find(rc
);
535 if (I
!= SuperClassMap
.end()) {
536 for (std::set
<unsigned>::iterator II
= I
->second
.begin(),
537 EE
= I
->second
.end(); II
!= EE
; ++II
) {
538 const CodeGenRegisterClass
&RC2
= RegisterClasses
[*II
];
539 if (!Empty
) OS
<< ", ";
540 OS
<< "&" << getQualifiedName(RC2
.TheDef
) << "RegClass";
545 OS
<< (!Empty
? ", " : "") << "NULL";
550 for (unsigned i
= 0, e
= RegisterClasses
.size(); i
!= e
; ++i
) {
551 const CodeGenRegisterClass
&RC
= RegisterClasses
[i
];
552 OS
<< RC
.MethodBodies
<< "\n";
553 OS
<< RC
.getName() << "Class::" << RC
.getName()
554 << "Class() : TargetRegisterClass("
555 << RC
.getName() + "RegClassID" << ", "
556 << '\"' << RC
.getName() << "\", "
557 << RC
.getName() + "VTs" << ", "
558 << RC
.getName() + "Subclasses" << ", "
559 << RC
.getName() + "Superclasses" << ", "
560 << (NumSubRegIndices
? RC
.getName() + "Sub" : std::string("Null"))
562 << (NumSubRegIndices
? RC
.getName() + "Super" : std::string("Null"))
564 << RC
.SpillSize
/8 << ", "
565 << RC
.SpillAlignment
/8 << ", "
566 << RC
.CopyCost
<< ", "
567 << RC
.getName() << ", " << RC
.getName() << " + " << RC
.Elements
.size()
574 OS
<< "\nnamespace {\n";
575 OS
<< " const TargetRegisterClass* const RegisterClasses[] = {\n";
576 for (unsigned i
= 0, e
= RegisterClasses
.size(); i
!= e
; ++i
)
577 OS
<< " &" << getQualifiedName(RegisterClasses
[i
].TheDef
)
581 // Emit register sub-registers / super-registers, aliases...
582 std::map
<Record
*, std::set
<Record
*>, LessRecord
> RegisterSubRegs
;
583 std::map
<Record
*, std::set
<Record
*>, LessRecord
> RegisterSuperRegs
;
584 std::map
<Record
*, std::set
<Record
*>, LessRecord
> RegisterAliases
;
585 typedef std::map
<Record
*, std::vector
<int64_t>, LessRecord
> DwarfRegNumsMapTy
;
586 DwarfRegNumsMapTy DwarfRegNums
;
588 const std::vector
<CodeGenRegister
> &Regs
= Target
.getRegisters();
590 for (unsigned i
= 0, e
= Regs
.size(); i
!= e
; ++i
) {
591 Record
*R
= Regs
[i
].TheDef
;
592 std::vector
<Record
*> LI
= Regs
[i
].TheDef
->getValueAsListOfDefs("Aliases");
593 // Add information that R aliases all of the elements in the list... and
594 // that everything in the list aliases R.
595 for (unsigned j
= 0, e
= LI
.size(); j
!= e
; ++j
) {
597 if (RegisterAliases
[R
].count(Reg
))
598 errs() << "Warning: register alias between " << getQualifiedName(R
)
599 << " and " << getQualifiedName(Reg
)
600 << " specified multiple times!\n";
601 RegisterAliases
[R
].insert(Reg
);
603 if (RegisterAliases
[Reg
].count(R
))
604 errs() << "Warning: register alias between " << getQualifiedName(R
)
605 << " and " << getQualifiedName(Reg
)
606 << " specified multiple times!\n";
607 RegisterAliases
[Reg
].insert(R
);
611 // Process sub-register sets.
612 for (unsigned i
= 0, e
= Regs
.size(); i
!= e
; ++i
) {
613 Record
*R
= Regs
[i
].TheDef
;
614 std::vector
<Record
*> LI
= Regs
[i
].TheDef
->getValueAsListOfDefs("SubRegs");
615 // Process sub-register set and add aliases information.
616 for (unsigned j
= 0, e
= LI
.size(); j
!= e
; ++j
) {
617 Record
*SubReg
= LI
[j
];
618 if (RegisterSubRegs
[R
].count(SubReg
))
619 errs() << "Warning: register " << getQualifiedName(SubReg
)
620 << " specified as a sub-register of " << getQualifiedName(R
)
621 << " multiple times!\n";
622 addSubSuperReg(R
, SubReg
, RegisterSubRegs
, RegisterSuperRegs
,
627 // Print the SubregHashTable, a simple quadratically probed
628 // hash table for determining if a register is a subregister
629 // of another register.
630 unsigned NumSubRegs
= 0;
631 std::map
<Record
*, unsigned> RegNo
;
632 for (unsigned i
= 0, e
= Regs
.size(); i
!= e
; ++i
) {
633 RegNo
[Regs
[i
].TheDef
] = i
;
634 NumSubRegs
+= RegisterSubRegs
[Regs
[i
].TheDef
].size();
637 unsigned SubregHashTableSize
= 2 * NextPowerOf2(2 * NumSubRegs
);
638 unsigned* SubregHashTable
= new unsigned[2 * SubregHashTableSize
];
639 std::fill(SubregHashTable
, SubregHashTable
+ 2 * SubregHashTableSize
, ~0U);
641 unsigned hashMisses
= 0;
643 for (unsigned i
= 0, e
= Regs
.size(); i
!= e
; ++i
) {
644 Record
* R
= Regs
[i
].TheDef
;
645 for (std::set
<Record
*>::iterator I
= RegisterSubRegs
[R
].begin(),
646 E
= RegisterSubRegs
[R
].end(); I
!= E
; ++I
) {
648 // We have to increase the indices of both registers by one when
649 // computing the hash because, in the generated code, there
650 // will be an extra empty slot at register 0.
651 size_t index
= ((i
+1) + (RegNo
[RJ
]+1) * 37) & (SubregHashTableSize
-1);
652 unsigned ProbeAmt
= 2;
653 while (SubregHashTable
[index
*2] != ~0U &&
654 SubregHashTable
[index
*2+1] != ~0U) {
655 index
= (index
+ ProbeAmt
) & (SubregHashTableSize
-1);
661 SubregHashTable
[index
*2] = i
;
662 SubregHashTable
[index
*2+1] = RegNo
[RJ
];
666 OS
<< "\n\n // Number of hash collisions: " << hashMisses
<< "\n";
668 if (SubregHashTableSize
) {
669 std::string Namespace
= Regs
[0].TheDef
->getValueAsString("Namespace");
671 OS
<< " const unsigned SubregHashTable[] = { ";
672 for (unsigned i
= 0; i
< SubregHashTableSize
- 1; ++i
) {
674 // Insert spaces for nice formatting.
677 if (SubregHashTable
[2*i
] != ~0U) {
678 OS
<< getQualifiedName(Regs
[SubregHashTable
[2*i
]].TheDef
) << ", "
679 << getQualifiedName(Regs
[SubregHashTable
[2*i
+1]].TheDef
) << ", \n";
681 OS
<< Namespace
<< "::NoRegister, " << Namespace
<< "::NoRegister, \n";
685 unsigned Idx
= SubregHashTableSize
*2-2;
686 if (SubregHashTable
[Idx
] != ~0U) {
688 << getQualifiedName(Regs
[SubregHashTable
[Idx
]].TheDef
) << ", "
689 << getQualifiedName(Regs
[SubregHashTable
[Idx
+1]].TheDef
) << " };\n";
691 OS
<< Namespace
<< "::NoRegister, " << Namespace
<< "::NoRegister };\n";
694 OS
<< " const unsigned SubregHashTableSize = "
695 << SubregHashTableSize
<< ";\n";
697 OS
<< " const unsigned SubregHashTable[] = { ~0U, ~0U };\n"
698 << " const unsigned SubregHashTableSize = 1;\n";
701 delete [] SubregHashTable
;
704 // Print the AliasHashTable, a simple quadratically probed
705 // hash table for determining if a register aliases another register.
706 unsigned NumAliases
= 0;
708 for (unsigned i
= 0, e
= Regs
.size(); i
!= e
; ++i
) {
709 RegNo
[Regs
[i
].TheDef
] = i
;
710 NumAliases
+= RegisterAliases
[Regs
[i
].TheDef
].size();
713 unsigned AliasesHashTableSize
= 2 * NextPowerOf2(2 * NumAliases
);
714 unsigned* AliasesHashTable
= new unsigned[2 * AliasesHashTableSize
];
715 std::fill(AliasesHashTable
, AliasesHashTable
+ 2 * AliasesHashTableSize
, ~0U);
719 for (unsigned i
= 0, e
= Regs
.size(); i
!= e
; ++i
) {
720 Record
* R
= Regs
[i
].TheDef
;
721 for (std::set
<Record
*>::iterator I
= RegisterAliases
[R
].begin(),
722 E
= RegisterAliases
[R
].end(); I
!= E
; ++I
) {
724 // We have to increase the indices of both registers by one when
725 // computing the hash because, in the generated code, there
726 // will be an extra empty slot at register 0.
727 size_t index
= ((i
+1) + (RegNo
[RJ
]+1) * 37) & (AliasesHashTableSize
-1);
728 unsigned ProbeAmt
= 2;
729 while (AliasesHashTable
[index
*2] != ~0U &&
730 AliasesHashTable
[index
*2+1] != ~0U) {
731 index
= (index
+ ProbeAmt
) & (AliasesHashTableSize
-1);
737 AliasesHashTable
[index
*2] = i
;
738 AliasesHashTable
[index
*2+1] = RegNo
[RJ
];
742 OS
<< "\n\n // Number of hash collisions: " << hashMisses
<< "\n";
744 if (AliasesHashTableSize
) {
745 std::string Namespace
= Regs
[0].TheDef
->getValueAsString("Namespace");
747 OS
<< " const unsigned AliasesHashTable[] = { ";
748 for (unsigned i
= 0; i
< AliasesHashTableSize
- 1; ++i
) {
750 // Insert spaces for nice formatting.
753 if (AliasesHashTable
[2*i
] != ~0U) {
754 OS
<< getQualifiedName(Regs
[AliasesHashTable
[2*i
]].TheDef
) << ", "
755 << getQualifiedName(Regs
[AliasesHashTable
[2*i
+1]].TheDef
) << ", \n";
757 OS
<< Namespace
<< "::NoRegister, " << Namespace
<< "::NoRegister, \n";
761 unsigned Idx
= AliasesHashTableSize
*2-2;
762 if (AliasesHashTable
[Idx
] != ~0U) {
764 << getQualifiedName(Regs
[AliasesHashTable
[Idx
]].TheDef
) << ", "
765 << getQualifiedName(Regs
[AliasesHashTable
[Idx
+1]].TheDef
) << " };\n";
767 OS
<< Namespace
<< "::NoRegister, " << Namespace
<< "::NoRegister };\n";
770 OS
<< " const unsigned AliasesHashTableSize = "
771 << AliasesHashTableSize
<< ";\n";
773 OS
<< " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n"
774 << " const unsigned AliasesHashTableSize = 1;\n";
777 delete [] AliasesHashTable
;
779 if (!RegisterAliases
.empty())
780 OS
<< "\n\n // Register Overlap Lists...\n";
782 // Emit an overlap list for all registers.
783 for (std::map
<Record
*, std::set
<Record
*>, LessRecord
>::iterator
784 I
= RegisterAliases
.begin(), E
= RegisterAliases
.end(); I
!= E
; ++I
) {
785 OS
<< " const unsigned " << I
->first
->getName() << "_Overlaps[] = { "
786 << getQualifiedName(I
->first
) << ", ";
787 for (std::set
<Record
*>::iterator ASI
= I
->second
.begin(),
788 E
= I
->second
.end(); ASI
!= E
; ++ASI
)
789 OS
<< getQualifiedName(*ASI
) << ", ";
793 if (!RegisterSubRegs
.empty())
794 OS
<< "\n\n // Register Sub-registers Sets...\n";
796 // Emit the empty sub-registers list
797 OS
<< " const unsigned Empty_SubRegsSet[] = { 0 };\n";
798 // Loop over all of the registers which have sub-registers, emitting the
799 // sub-registers list to memory.
800 for (std::map
<Record
*, std::set
<Record
*>, LessRecord
>::iterator
801 I
= RegisterSubRegs
.begin(), E
= RegisterSubRegs
.end(); I
!= E
; ++I
) {
802 if (I
->second
.empty())
804 OS
<< " const unsigned " << I
->first
->getName() << "_SubRegsSet[] = { ";
805 std::vector
<Record
*> SubRegsVector
;
806 for (std::set
<Record
*>::iterator ASI
= I
->second
.begin(),
807 E
= I
->second
.end(); ASI
!= E
; ++ASI
)
808 SubRegsVector
.push_back(*ASI
);
809 RegisterSorter
RS(RegisterSubRegs
);
810 std::stable_sort(SubRegsVector
.begin(), SubRegsVector
.end(), RS
);
811 for (unsigned i
= 0, e
= SubRegsVector
.size(); i
!= e
; ++i
)
812 OS
<< getQualifiedName(SubRegsVector
[i
]) << ", ";
816 if (!RegisterSuperRegs
.empty())
817 OS
<< "\n\n // Register Super-registers Sets...\n";
819 // Emit the empty super-registers list
820 OS
<< " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
821 // Loop over all of the registers which have super-registers, emitting the
822 // super-registers list to memory.
823 for (std::map
<Record
*, std::set
<Record
*>, LessRecord
>::iterator
824 I
= RegisterSuperRegs
.begin(), E
= RegisterSuperRegs
.end(); I
!= E
; ++I
) {
825 if (I
->second
.empty())
827 OS
<< " const unsigned " << I
->first
->getName() << "_SuperRegsSet[] = { ";
829 std::vector
<Record
*> SuperRegsVector
;
830 for (std::set
<Record
*>::iterator ASI
= I
->second
.begin(),
831 E
= I
->second
.end(); ASI
!= E
; ++ASI
)
832 SuperRegsVector
.push_back(*ASI
);
833 RegisterSorter
RS(RegisterSubRegs
);
834 std::stable_sort(SuperRegsVector
.begin(), SuperRegsVector
.end(), RS
);
835 for (unsigned i
= 0, e
= SuperRegsVector
.size(); i
!= e
; ++i
)
836 OS
<< getQualifiedName(SuperRegsVector
[i
]) << ", ";
840 OS
<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
841 OS
<< " { \"NOREG\",\t0,\t0,\t0 },\n";
843 // Now that register alias and sub-registers sets have been emitted, emit the
844 // register descriptors now.
845 for (unsigned i
= 0, e
= Regs
.size(); i
!= e
; ++i
) {
846 const CodeGenRegister
&Reg
= Regs
[i
];
848 OS
<< Reg
.getName() << "\",\t" << Reg
.getName() << "_Overlaps,\t";
849 if (!RegisterSubRegs
[Reg
.TheDef
].empty())
850 OS
<< Reg
.getName() << "_SubRegsSet,\t";
852 OS
<< "Empty_SubRegsSet,\t";
853 if (!RegisterSuperRegs
[Reg
.TheDef
].empty())
854 OS
<< Reg
.getName() << "_SuperRegsSet },\n";
856 OS
<< "Empty_SuperRegsSet },\n";
858 OS
<< " };\n"; // End of register descriptors...
860 // Emit SubRegIndex names, skipping 0
861 const std::vector
<Record
*> SubRegIndices
= Target
.getSubRegIndices();
862 OS
<< "\n const char *const SubRegIndexTable[] = { \"";
863 for (unsigned i
= 0, e
= SubRegIndices
.size(); i
!= e
; ++i
) {
864 OS
<< SubRegIndices
[i
]->getName();
869 OS
<< "}\n\n"; // End of anonymous namespace...
871 std::string ClassName
= Target
.getName() + "GenRegisterInfo";
873 // Calculate the mapping of subregister+index pairs to physical registers.
874 RegisterMaps RegMaps
;
876 // Emit the subregister + index mapping function based on the information
878 OS
<< "unsigned " << ClassName
879 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
880 << " switch (RegNo) {\n"
881 << " default:\n return 0;\n";
882 for (unsigned i
= 0, e
= Regs
.size(); i
!= e
; ++i
) {
883 RegisterMaps::SubRegMap
&SRM
= RegMaps
.inferSubRegIndices(Regs
[i
].TheDef
);
886 OS
<< " case " << getQualifiedName(Regs
[i
].TheDef
) << ":\n";
887 OS
<< " switch (Index) {\n";
888 OS
<< " default: return 0;\n";
889 for (RegisterMaps::SubRegMap::const_iterator ii
= SRM
.begin(),
890 ie
= SRM
.end(); ii
!= ie
; ++ii
)
891 OS
<< " case " << getQualifiedName(ii
->first
)
892 << ": return " << getQualifiedName(ii
->second
) << ";\n";
893 OS
<< " };\n" << " break;\n";
896 OS
<< " return 0;\n";
899 OS
<< "unsigned " << ClassName
900 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
901 << " switch (RegNo) {\n"
902 << " default:\n return 0;\n";
903 for (unsigned i
= 0, e
= Regs
.size(); i
!= e
; ++i
) {
904 RegisterMaps::SubRegMap
&SRM
= RegMaps
.SubReg
[Regs
[i
].TheDef
];
907 OS
<< " case " << getQualifiedName(Regs
[i
].TheDef
) << ":\n";
908 for (RegisterMaps::SubRegMap::const_iterator ii
= SRM
.begin(),
909 ie
= SRM
.end(); ii
!= ie
; ++ii
)
910 OS
<< " if (SubRegNo == " << getQualifiedName(ii
->second
)
911 << ") return " << getQualifiedName(ii
->first
) << ";\n";
912 OS
<< " return 0;\n";
915 OS
<< " return 0;\n";
918 // Emit composeSubRegIndices
919 RegMaps
.computeComposites();
920 OS
<< "unsigned " << ClassName
921 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
922 << " switch (IdxA) {\n"
923 << " default:\n return IdxB;\n";
924 for (unsigned i
= 0, e
= SubRegIndices
.size(); i
!= e
; ++i
) {
926 for (unsigned j
= 0; j
!= e
; ++j
) {
927 if (Record
*Comp
= RegMaps
.Composite
.lookup(
928 std::make_pair(SubRegIndices
[i
], SubRegIndices
[j
]))) {
930 OS
<< " case " << getQualifiedName(SubRegIndices
[i
])
931 << ": switch(IdxB) {\n default: return IdxB;\n";
934 OS
<< " case " << getQualifiedName(SubRegIndices
[j
])
935 << ": return " << getQualifiedName(Comp
) << ";\n";
943 // Emit the constructor of the class...
944 OS
<< ClassName
<< "::" << ClassName
945 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
946 << " : TargetRegisterInfo(RegisterDescriptors, " << Regs
.size()+1
947 << ", RegisterClasses, RegisterClasses+" << RegisterClasses
.size() <<",\n"
948 << " SubRegIndexTable,\n"
949 << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
950 << " SubregHashTable, SubregHashTableSize,\n"
951 << " AliasesHashTable, AliasesHashTableSize) {\n"
954 // Collect all information about dwarf register numbers
956 // First, just pull all provided information to the map
957 unsigned maxLength
= 0;
958 for (unsigned i
= 0, e
= Regs
.size(); i
!= e
; ++i
) {
959 Record
*Reg
= Regs
[i
].TheDef
;
960 std::vector
<int64_t> RegNums
= Reg
->getValueAsListOfInts("DwarfNumbers");
961 maxLength
= std::max((size_t)maxLength
, RegNums
.size());
962 if (DwarfRegNums
.count(Reg
))
963 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg
)
964 << "specified multiple times\n";
965 DwarfRegNums
[Reg
] = RegNums
;
968 // Now we know maximal length of number list. Append -1's, where needed
969 for (DwarfRegNumsMapTy::iterator
970 I
= DwarfRegNums
.begin(), E
= DwarfRegNums
.end(); I
!= E
; ++I
)
971 for (unsigned i
= I
->second
.size(), e
= maxLength
; i
!= e
; ++i
)
972 I
->second
.push_back(-1);
974 // Emit information about the dwarf register numbers.
975 OS
<< "int " << ClassName
<< "::getDwarfRegNumFull(unsigned RegNum, "
976 << "unsigned Flavour) const {\n"
977 << " switch (Flavour) {\n"
979 << " assert(0 && \"Unknown DWARF flavour\");\n"
982 for (unsigned i
= 0, e
= maxLength
; i
!= e
; ++i
) {
983 OS
<< " case " << i
<< ":\n"
984 << " switch (RegNum) {\n"
986 << " assert(0 && \"Invalid RegNum\");\n"
989 // Sort by name to get a stable order.
992 for (DwarfRegNumsMapTy::iterator
993 I
= DwarfRegNums
.begin(), E
= DwarfRegNums
.end(); I
!= E
; ++I
) {
994 int RegNo
= I
->second
[i
];
996 OS
<< " case " << getQualifiedName(I
->first
) << ":\n"
997 << " return " << RegNo
<< ";\n";
999 OS
<< " case " << getQualifiedName(I
->first
) << ":\n"
1000 << " assert(0 && \"Invalid register for this mode\");\n"
1008 OS
<< "} // End llvm namespace \n";