utils/TableGen/EDEmitter.cpp

   1 //===- EDEmitter.cpp - Generate instruction descriptions for ED -*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This tablegen backend is responsible for emitting a description of each
  11 // instruction in a format that the enhanced disassembler can use to tokenize
  12 // and parse instructions.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #include "EDEmitter.h"
  17
  18 #include "AsmWriterInst.h"
  19 #include "CodeGenTarget.h"
  20 #include "Record.h"
  21
  22 #include "llvm/MC/EDInstInfo.h"
  23 #include "llvm/Support/ErrorHandling.h"
  24 #include "llvm/Support/Format.h"
  25 #include "llvm/Support/raw_ostream.h"
  26
  27 #include <map>
  28 #include <string>
  29 #include <vector>
  30
  31 using namespace llvm;
  32
  33 ///////////////////////////////////////////////////////////
  34 // Support classes for emitting nested C data structures //
  35 ///////////////////////////////////////////////////////////
  36
  37 namespace {
  38
  39   class EnumEmitter {
  40   private:
  41     std::string Name;
  42     std::vector<std::string> Entries;
  43   public:
  44     EnumEmitter(const char *N) : Name(N) {
  45     }
  46     int addEntry(const char *e) {
  47       Entries.push_back(std::string(e));
  48       return Entries.size() - 1;
  49     }
  50     void emit(raw_ostream &o, unsigned int &i) {
  51       o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
  52       i += 2;
  53
  54       unsigned int index = 0;
  55       unsigned int numEntries = Entries.size();
  56       for (index = 0; index < numEntries; ++index) {
  57         o.indent(i) << Entries[index];
  58         if (index < (numEntries - 1))
  59           o << ",";
  60         o << "\n";
  61       }
  62
  63       i -= 2;
  64       o.indent(i) << "};" << "\n";
  65     }
  66
  67     void emitAsFlags(raw_ostream &o, unsigned int &i) {
  68       o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
  69       i += 2;
  70
  71       unsigned int index = 0;
  72       unsigned int numEntries = Entries.size();
  73       unsigned int flag = 1;
  74       for (index = 0; index < numEntries; ++index) {
  75         o.indent(i) << Entries[index] << " = " << format("0x%x", flag);
  76         if (index < (numEntries - 1))
  77           o << ",";
  78         o << "\n";
  79         flag <<= 1;
  80       }
  81
  82       i -= 2;
  83       o.indent(i) << "};" << "\n";
  84     }
  85   };
  86
  87   class ConstantEmitter {
  88   public:
  89     virtual ~ConstantEmitter() { }
  90     virtual void emit(raw_ostream &o, unsigned int &i) = 0;
  91   };
  92
  93   class LiteralConstantEmitter : public ConstantEmitter {
  94   private:
  95     bool IsNumber;
  96     union {
  97       int Number;
  98       const char* String;
  99     };
 100   public:
 101     LiteralConstantEmitter(int number = 0) :
 102       IsNumber(true),
 103       Number(number) {
 104     }
 105     void set(const char *string) {
 106       IsNumber = false;
 107       Number = 0;
 108       String = string;
 109     }
 110     bool is(const char *string) {
 111       return !strcmp(String, string);
 112     }
 113     void emit(raw_ostream &o, unsigned int &i) {
 114       if (IsNumber)
 115         o << Number;
 116       else
 117         o << String;
 118     }
 119   };
 120
 121   class CompoundConstantEmitter : public ConstantEmitter {
 122   private:
 123     unsigned int Padding;
 124     std::vector<ConstantEmitter *> Entries;
 125   public:
 126     CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) {
 127     }
 128     CompoundConstantEmitter &addEntry(ConstantEmitter *e) {
 129       Entries.push_back(e);
 130
 131       return *this;
 132     }
 133     ~CompoundConstantEmitter() {
 134       while (Entries.size()) {
 135         ConstantEmitter *entry = Entries.back();
 136         Entries.pop_back();
 137         delete entry;
 138       }
 139     }
 140     void emit(raw_ostream &o, unsigned int &i) {
 141       o << "{" << "\n";
 142       i += 2;
 143
 144       unsigned int index;
 145       unsigned int numEntries = Entries.size();
 146
 147       unsigned int numToPrint;
 148
 149       if (Padding) {
 150         if (numEntries > Padding) {
 151           fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding);
 152           llvm_unreachable("More entries than padding");
 153         }
 154         numToPrint = Padding;
 155       } else {
 156         numToPrint = numEntries;
 157       }
 158
 159       for (index = 0; index < numToPrint; ++index) {
 160         o.indent(i);
 161         if (index < numEntries)
 162           Entries[index]->emit(o, i);
 163         else
 164           o << "-1";
 165
 166         if (index < (numToPrint - 1))
 167           o << ",";
 168         o << "\n";
 169       }
 170
 171       i -= 2;
 172       o.indent(i) << "}";
 173     }
 174   };
 175
 176   class FlagsConstantEmitter : public ConstantEmitter {
 177   private:
 178     std::vector<std::string> Flags;
 179   public:
 180     FlagsConstantEmitter() {
 181     }
 182     FlagsConstantEmitter &addEntry(const char *f) {
 183       Flags.push_back(std::string(f));
 184       return *this;
 185     }
 186     void emit(raw_ostream &o, unsigned int &i) {
 187       unsigned int index;
 188       unsigned int numFlags = Flags.size();
 189       if (numFlags == 0)
 190         o << "0";
 191
 192       for (index = 0; index < numFlags; ++index) {
 193         o << Flags[index].c_str();
 194         if (index < (numFlags - 1))
 195           o << " | ";
 196       }
 197     }
 198   };
 199 }
 200
 201 EDEmitter::EDEmitter(RecordKeeper &R) : Records(R) {
 202 }
 203
 204 /// populateOperandOrder - Accepts a CodeGenInstruction and generates its
 205 ///   AsmWriterInst for the desired assembly syntax, giving an ordered list of
 206 ///   operands in the order they appear in the printed instruction.  Then, for
 207 ///   each entry in that list, determines the index of the same operand in the
 208 ///   CodeGenInstruction, and emits the resulting mapping into an array, filling
 209 ///   in unused slots with -1.
 210 ///
 211 /// @arg operandOrder - The array that will be populated with the operand
 212 ///                     mapping.  Each entry will contain -1 (invalid index
 213 ///                     into the operands present in the AsmString) or a number
 214 ///                     representing an index in the operand descriptor array.
 215 /// @arg inst         - The instruction to use when looking up the operands
 216 /// @arg syntax       - The syntax to use, according to LLVM's enumeration
 217 void populateOperandOrder(CompoundConstantEmitter *operandOrder,
 218                           const CodeGenInstruction &inst,
 219                           unsigned syntax) {
 220   unsigned int numArgs = 0;
 221
 222   AsmWriterInst awInst(inst, syntax, -1, -1);
 223
 224   std::vector<AsmWriterOperand>::iterator operandIterator;
 225
 226   for (operandIterator = awInst.Operands.begin();
 227        operandIterator != awInst.Operands.end();
 228        ++operandIterator) {
 229     if (operandIterator->OperandType ==
 230         AsmWriterOperand::isMachineInstrOperand) {
 231       operandOrder->addEntry(
 232         new LiteralConstantEmitter(operandIterator->CGIOpNo));
 233       numArgs++;
 234     }
 235   }
 236 }
 237
 238 /////////////////////////////////////////////////////
 239 // Support functions for handling X86 instructions //
 240 /////////////////////////////////////////////////////
 241
 242 #define SET(flag) { type->set(flag); return 0; }
 243
 244 #define REG(str) if (name == str) SET("kOperandTypeRegister");
 245 #define MEM(str) if (name == str) SET("kOperandTypeX86Memory");
 246 #define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress");
 247 #define IMM(str) if (name == str) SET("kOperandTypeImmediate");
 248 #define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative");
 249
 250 /// X86TypeFromOpName - Processes the name of a single X86 operand (which is
 251 ///   actually its type) and translates it into an operand type
 252 ///
 253 /// @arg flags    - The type object to set
 254 /// @arg name     - The name of the operand
 255 static int X86TypeFromOpName(LiteralConstantEmitter *type,
 256                              const std::string &name) {
 257   REG("GR8");
 258   REG("GR8_NOREX");
 259   REG("GR16");
 260   REG("GR32");
 261   REG("GR32_NOREX");
 262   REG("GR32_TC");
 263   REG("FR32");
 264   REG("RFP32");
 265   REG("GR64");
 266   REG("GR64_TC");
 267   REG("FR64");
 268   REG("VR64");
 269   REG("RFP64");
 270   REG("RFP80");
 271   REG("VR128");
 272   REG("VR256");
 273   REG("RST");
 274   REG("SEGMENT_REG");
 275   REG("DEBUG_REG");
 276   REG("CONTROL_REG");
 277
 278   IMM("i8imm");
 279   IMM("i16imm");
 280   IMM("i16i8imm");
 281   IMM("i32imm");
 282   IMM("i32i8imm");
 283   IMM("i64imm");
 284   IMM("i64i8imm");
 285   IMM("i64i32imm");
 286   IMM("SSECC");
 287
 288   // all R, I, R, I, R
 289   MEM("i8mem");
 290   MEM("i8mem_NOREX");
 291   MEM("i16mem");
 292   MEM("i32mem");
 293   MEM("i32mem_TC");
 294   MEM("f32mem");
 295   MEM("ssmem");
 296   MEM("opaque32mem");
 297   MEM("opaque48mem");
 298   MEM("i64mem");
 299   MEM("i64mem_TC");
 300   MEM("f64mem");
 301   MEM("sdmem");
 302   MEM("f80mem");
 303   MEM("opaque80mem");
 304   MEM("i128mem");
 305   MEM("i256mem");
 306   MEM("f128mem");
 307   MEM("f256mem");
 308   MEM("opaque512mem");
 309
 310   // all R, I, R, I
 311   LEA("lea32mem");
 312   LEA("lea64_32mem");
 313   LEA("lea64mem");
 314
 315   // all I
 316   PCR("i16imm_pcrel");
 317   PCR("i32imm_pcrel");
 318   PCR("i64i32imm_pcrel");
 319   PCR("brtarget8");
 320   PCR("offset8");
 321   PCR("offset16");
 322   PCR("offset32");
 323   PCR("offset64");
 324   PCR("brtarget");
 325   PCR("uncondbrtarget");
 326   PCR("bltarget");
 327
 328   // all I, ARM mode only, conditional/unconditional
 329   PCR("br_target");
 330   PCR("bl_target");
 331   return 1;
 332 }
 333
 334 #undef REG
 335 #undef MEM
 336 #undef LEA
 337 #undef IMM
 338 #undef PCR
 339
 340 #undef SET
 341
 342 /// X86PopulateOperands - Handles all the operands in an X86 instruction, adding
 343 ///   the appropriate flags to their descriptors
 344 ///
 345 /// @operandFlags - A reference the array of operand flag objects
 346 /// @inst         - The instruction to use as a source of information
 347 static void X86PopulateOperands(
 348   LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
 349   const CodeGenInstruction &inst) {
 350   if (!inst.TheDef->isSubClassOf("X86Inst"))
 351     return;
 352
 353   unsigned int index;
 354   unsigned int numOperands = inst.Operands.size();
 355
 356   for (index = 0; index < numOperands; ++index) {
 357     const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
 358     Record &rec = *operandInfo.Rec;
 359
 360     if (X86TypeFromOpName(operandTypes[index], rec.getName()) &&
 361         !rec.isSubClassOf("PointerLikeRegClass")) {
 362       errs() << "Operand type: " << rec.getName().c_str() << "\n";
 363       errs() << "Operand name: " << operandInfo.Name.c_str() << "\n";
 364       errs() << "Instruction name: " << inst.TheDef->getName().c_str() << "\n";
 365       llvm_unreachable("Unhandled type");
 366     }
 367   }
 368 }
 369
 370 /// decorate1 - Decorates a named operand with a new flag
 371 ///
 372 /// @operandFlags - The array of operand flag objects, which don't have names
 373 /// @inst         - The CodeGenInstruction, which provides a way to translate
 374 ///                 between names and operand indices
 375 /// @opName       - The name of the operand
 376 /// @flag         - The name of the flag to add
 377 static inline void decorate1(
 378   FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
 379   const CodeGenInstruction &inst,
 380   const char *opName,
 381   const char *opFlag) {
 382   unsigned opIndex;
 383
 384   opIndex = inst.Operands.getOperandNamed(std::string(opName));
 385
 386   operandFlags[opIndex]->addEntry(opFlag);
 387 }
 388
 389 #define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag)
 390
 391 #define MOV(source, target) {               \
 392   instType.set("kInstructionTypeMove");     \
 393   DECORATE1(source, "kOperandFlagSource");  \
 394   DECORATE1(target, "kOperandFlagTarget");  \
 395 }
 396
 397 #define BRANCH(target) {                    \
 398   instType.set("kInstructionTypeBranch");   \
 399   DECORATE1(target, "kOperandFlagTarget");  \
 400 }
 401
 402 #define PUSH(source) {                      \
 403   instType.set("kInstructionTypePush");     \
 404   DECORATE1(source, "kOperandFlagSource");  \
 405 }
 406
 407 #define POP(target) {                       \
 408   instType.set("kInstructionTypePop");      \
 409   DECORATE1(target, "kOperandFlagTarget");  \
 410 }
 411
 412 #define CALL(target) {                      \
 413   instType.set("kInstructionTypeCall");     \
 414   DECORATE1(target, "kOperandFlagTarget");  \
 415 }
 416
 417 #define RETURN() {                          \
 418   instType.set("kInstructionTypeReturn");   \
 419 }
 420
 421 /// X86ExtractSemantics - Performs various checks on the name of an X86
 422 ///   instruction to determine what sort of an instruction it is and then adds
 423 ///   the appropriate flags to the instruction and its operands
 424 ///
 425 /// @arg instType     - A reference to the type for the instruction as a whole
 426 /// @arg operandFlags - A reference to the array of operand flag object pointers
 427 /// @arg inst         - A reference to the original instruction
 428 static void X86ExtractSemantics(
 429   LiteralConstantEmitter &instType,
 430   FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
 431   const CodeGenInstruction &inst) {
 432   const std::string &name = inst.TheDef->getName();
 433
 434   if (name.find("MOV") != name.npos) {
 435     if (name.find("MOV_V") != name.npos) {
 436       // ignore (this is a pseudoinstruction)
 437     } else if (name.find("MASK") != name.npos) {
 438       // ignore (this is a masking move)
 439     } else if (name.find("r0") != name.npos) {
 440       // ignore (this is a pseudoinstruction)
 441     } else if (name.find("PS") != name.npos ||
 442              name.find("PD") != name.npos) {
 443       // ignore (this is a shuffling move)
 444     } else if (name.find("MOVS") != name.npos) {
 445       // ignore (this is a string move)
 446     } else if (name.find("_F") != name.npos) {
 447       // TODO handle _F moves to ST(0)
 448     } else if (name.find("a") != name.npos) {
 449       // TODO handle moves to/from %ax
 450     } else if (name.find("CMOV") != name.npos) {
 451       MOV("src2", "dst");
 452     } else if (name.find("PC") != name.npos) {
 453       MOV("label", "reg")
 454     } else {
 455       MOV("src", "dst");
 456     }
 457   }
 458
 459   if (name.find("JMP") != name.npos ||
 460       name.find("J") == 0) {
 461     if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
 462       BRANCH("off");
 463     } else {
 464       BRANCH("dst");
 465     }
 466   }
 467
 468   if (name.find("PUSH") != name.npos) {
 469     if (name.find("CS") != name.npos ||
 470         name.find("DS") != name.npos ||
 471         name.find("ES") != name.npos ||
 472         name.find("FS") != name.npos ||
 473         name.find("GS") != name.npos ||
 474         name.find("SS") != name.npos) {
 475       instType.set("kInstructionTypePush");
 476       // TODO add support for fixed operands
 477     } else if (name.find("F") != name.npos) {
 478       // ignore (this pushes onto the FP stack)
 479     } else if (name.find("A") != name.npos) {
 480       // ignore (pushes all GP registoers onto the stack)
 481     } else if (name[name.length() - 1] == 'm') {
 482       PUSH("src");
 483     } else if (name.find("i") != name.npos) {
 484       PUSH("imm");
 485     } else {
 486       PUSH("reg");
 487     }
 488   }
 489
 490   if (name.find("POP") != name.npos) {
 491     if (name.find("POPCNT") != name.npos) {
 492       // ignore (not a real pop)
 493     } else if (name.find("CS") != name.npos ||
 494                name.find("DS") != name.npos ||
 495                name.find("ES") != name.npos ||
 496                name.find("FS") != name.npos ||
 497                name.find("GS") != name.npos ||
 498                name.find("SS") != name.npos) {
 499       instType.set("kInstructionTypePop");
 500       // TODO add support for fixed operands
 501     } else if (name.find("F") != name.npos) {
 502       // ignore (this pops from the FP stack)
 503     } else if (name.find("A") != name.npos) {
 504       // ignore (pushes all GP registoers onto the stack)
 505     } else if (name[name.length() - 1] == 'm') {
 506       POP("dst");
 507     } else {
 508       POP("reg");
 509     }
 510   }
 511
 512   if (name.find("CALL") != name.npos) {
 513     if (name.find("ADJ") != name.npos) {
 514       // ignore (not a call)
 515     } else if (name.find("SYSCALL") != name.npos) {
 516       // ignore (doesn't go anywhere we know about)
 517     } else if (name.find("VMCALL") != name.npos) {
 518       // ignore (rather different semantics than a regular call)
 519     } else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
 520       CALL("off");
 521     } else {
 522       CALL("dst");
 523     }
 524   }
 525
 526   if (name.find("RET") != name.npos) {
 527     RETURN();
 528   }
 529 }
 530
 531 #undef MOV
 532 #undef BRANCH
 533 #undef PUSH
 534 #undef POP
 535 #undef CALL
 536 #undef RETURN
 537
 538 /////////////////////////////////////////////////////
 539 // Support functions for handling ARM instructions //
 540 /////////////////////////////////////////////////////
 541
 542 #define SET(flag) { type->set(flag); return 0; }
 543
 544 #define REG(str)    if (name == str) SET("kOperandTypeRegister");
 545 #define IMM(str)    if (name == str) SET("kOperandTypeImmediate");
 546
 547 #define MISC(str, type)   if (name == str) SET(type);
 548
 549 /// ARMFlagFromOpName - Processes the name of a single ARM operand (which is
 550 ///   actually its type) and translates it into an operand type
 551 ///
 552 /// @arg type     - The type object to set
 553 /// @arg name     - The name of the operand
 554 static int ARMFlagFromOpName(LiteralConstantEmitter *type,
 555                              const std::string &name) {
 556   REG("GPR");
 557   REG("rGPR");
 558   REG("tcGPR");
 559   REG("cc_out");
 560   REG("s_cc_out");
 561   REG("tGPR");
 562   REG("DPR");
 563   REG("DPR_VFP2");
 564   REG("DPR_8");
 565   REG("SPR");
 566   REG("QPR");
 567   REG("QQPR");
 568   REG("QQQQPR");
 569
 570   IMM("i32imm");
 571   IMM("i32imm_hilo16");
 572   IMM("bf_inv_mask_imm");
 573   IMM("lsb_pos_imm");
 574   IMM("width_imm");
 575   IMM("jtblock_operand");
 576   IMM("nohash_imm");
 577   IMM("p_imm");
 578   IMM("c_imm");
 579   IMM("imod_op");
 580   IMM("iflags_op");
 581   IMM("cpinst_operand");
 582   IMM("setend_op");
 583   IMM("cps_opt");
 584   IMM("vfp_f64imm");
 585   IMM("vfp_f32imm");
 586   IMM("memb_opt");
 587   IMM("msr_mask");
 588   IMM("neg_zero");
 589   IMM("imm0_31");
 590   IMM("imm0_31_m1");
 591   IMM("nModImm");
 592   IMM("imm0_4095");
 593   IMM("jt2block_operand");
 594   IMM("t_imm_s4");
 595   IMM("pclabel");
 596   IMM("adrlabel");
 597   IMM("t_adrlabel");
 598   IMM("t2adrlabel");
 599   IMM("shift_imm");
 600   IMM("neon_vcvt_imm32");
 601
 602   MISC("brtarget", "kOperandTypeARMBranchTarget");                // ?
 603   MISC("uncondbrtarget", "kOperandTypeARMBranchTarget");           // ?
 604   MISC("t_brtarget", "kOperandTypeARMBranchTarget");              // ?
 605   MISC("t_bcctarget", "kOperandTypeARMBranchTarget");             // ?
 606   MISC("t_cbtarget", "kOperandTypeARMBranchTarget");              // ?
 607   MISC("bltarget", "kOperandTypeARMBranchTarget");                // ?
 608
 609   MISC("br_target", "kOperandTypeARMBranchTarget");                // ?
 610   MISC("bl_target", "kOperandTypeARMBranchTarget");                // ?
 611
 612   MISC("t_bltarget", "kOperandTypeARMBranchTarget");              // ?
 613   MISC("t_blxtarget", "kOperandTypeARMBranchTarget");             // ?
 614   MISC("so_reg", "kOperandTypeARMSoReg");                         // R, R, I
 615   MISC("shift_so_reg", "kOperandTypeARMSoReg");                   // R, R, I
 616   MISC("t2_so_reg", "kOperandTypeThumb2SoReg");                   // R, I
 617   MISC("so_imm", "kOperandTypeARMSoImm");                         // I
 618   MISC("rot_imm", "kOperandTypeARMRotImm");                       // I
 619   MISC("t2_so_imm", "kOperandTypeThumb2SoImm");                   // I
 620   MISC("so_imm2part", "kOperandTypeARMSoImm2Part");               // I
 621   MISC("pred", "kOperandTypeARMPredicate");                       // I, R
 622   MISC("it_pred", "kOperandTypeARMPredicate");                    // I
 623   MISC("addrmode_imm12", "kOperandTypeAddrModeImm12");            // R, I
 624   MISC("ldst_so_reg", "kOperandTypeLdStSOReg");                   // R, R, I
 625   MISC("addrmode2", "kOperandTypeARMAddrMode2");                  // R, R, I
 626   MISC("am2offset", "kOperandTypeARMAddrMode2Offset");            // R, I
 627   MISC("addrmode3", "kOperandTypeARMAddrMode3");                  // R, R, I
 628   MISC("am3offset", "kOperandTypeARMAddrMode3Offset");            // R, I
 629   MISC("ldstm_mode", "kOperandTypeARMLdStmMode");                 // I
 630   MISC("addrmode5", "kOperandTypeARMAddrMode5");                  // R, I
 631   MISC("addrmode6", "kOperandTypeARMAddrMode6");                  // R, R, I, I
 632   MISC("am6offset", "kOperandTypeARMAddrMode6Offset");            // R, I, I
 633   MISC("addrmode6dup", "kOperandTypeARMAddrMode6");               // R, R, I, I
 634   MISC("addrmodepc", "kOperandTypeARMAddrModePC");                // R, I
 635   MISC("reglist", "kOperandTypeARMRegisterList");                 // I, R, ...
 636   MISC("dpr_reglist", "kOperandTypeARMDPRRegisterList");          // I, R, ...
 637   MISC("spr_reglist", "kOperandTypeARMSPRRegisterList");          // I, R, ...
 638   MISC("it_mask", "kOperandTypeThumbITMask");                     // I
 639   MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8");      // R, I
 640   MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
 641   MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12");    // R, I
 642   MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg");   // R, R, I
 643   MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4");  // R, I
 644   MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
 645                                                                   // R, I
 646   MISC("tb_addrmode", "kOperandTypeARMTBAddrMode");               // I
 647   MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS");       // R, R
 648   MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS");       // R, R
 649   MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS");       // R, R
 650   MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS");        // R, I
 651   MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS");        // R, I
 652   MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS");        // R, I
 653   MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR");           // R, R
 654   MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP");           // R, I
 655   MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC");           // R, I
 656
 657   return 1;
 658 }
 659
 660 #undef SOREG
 661 #undef SOIMM
 662 #undef PRED
 663 #undef REG
 664 #undef MEM
 665 #undef LEA
 666 #undef IMM
 667 #undef PCR
 668
 669 #undef SET
 670
 671 /// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding
 672 ///   the appropriate flags to their descriptors
 673 ///
 674 /// @operandFlags - A reference the array of operand flag objects
 675 /// @inst         - The instruction to use as a source of information
 676 static void ARMPopulateOperands(
 677   LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
 678   const CodeGenInstruction &inst) {
 679   if (!inst.TheDef->isSubClassOf("InstARM") &&
 680       !inst.TheDef->isSubClassOf("InstThumb"))
 681     return;
 682
 683   unsigned int index;
 684   unsigned int numOperands = inst.Operands.size();
 685
 686   if (numOperands > EDIS_MAX_OPERANDS) {
 687     errs() << "numOperands == " << numOperands << " > " <<
 688       EDIS_MAX_OPERANDS << '\n';
 689     llvm_unreachable("Too many operands");
 690   }
 691
 692   for (index = 0; index < numOperands; ++index) {
 693     const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
 694     Record &rec = *operandInfo.Rec;
 695
 696     if (ARMFlagFromOpName(operandTypes[index], rec.getName())) {
 697       errs() << "Operand type: " << rec.getName() << '\n';
 698       errs() << "Operand name: " << operandInfo.Name << '\n';
 699       errs() << "Instruction name: " << inst.TheDef->getName() << '\n';
 700       llvm_unreachable("Unhandled type");
 701     }
 702   }
 703 }
 704
 705 #define BRANCH(target) {                    \
 706   instType.set("kInstructionTypeBranch");   \
 707   DECORATE1(target, "kOperandFlagTarget");  \
 708 }
 709
 710 /// ARMExtractSemantics - Performs various checks on the name of an ARM
 711 ///   instruction to determine what sort of an instruction it is and then adds
 712 ///   the appropriate flags to the instruction and its operands
 713 ///
 714 /// @arg instType     - A reference to the type for the instruction as a whole
 715 /// @arg operandTypes - A reference to the array of operand type object pointers
 716 /// @arg operandFlags - A reference to the array of operand flag object pointers
 717 /// @arg inst         - A reference to the original instruction
 718 static void ARMExtractSemantics(
 719   LiteralConstantEmitter &instType,
 720   LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
 721   FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
 722   const CodeGenInstruction &inst) {
 723   const std::string &name = inst.TheDef->getName();
 724
 725   if (name == "tBcc"   ||
 726       name == "tB"     ||
 727       name == "t2Bcc"  ||
 728       name == "Bcc"    ||
 729       name == "tCBZ"   ||
 730       name == "tCBNZ") {
 731     BRANCH("target");
 732   }
 733
 734   if (name == "tBLr9"      ||
 735       name == "BLr9_pred"  ||
 736       name == "tBLXi_r9"   ||
 737       name == "tBLXr_r9"   ||
 738       name == "BLXr9"      ||
 739       name == "t2BXJ"      ||
 740       name == "BXJ") {
 741     BRANCH("func");
 742
 743     unsigned opIndex;
 744     opIndex = inst.Operands.getOperandNamed("func");
 745     if (operandTypes[opIndex]->is("kOperandTypeImmediate"))
 746       operandTypes[opIndex]->set("kOperandTypeARMBranchTarget");
 747   }
 748 }
 749
 750 #undef BRANCH
 751
 752 /// populateInstInfo - Fills an array of InstInfos with information about each
 753 ///   instruction in a target
 754 ///
 755 /// @arg infoArray  - The array of InstInfo objects to populate
 756 /// @arg target     - The CodeGenTarget to use as a source of instructions
 757 static void populateInstInfo(CompoundConstantEmitter &infoArray,
 758                              CodeGenTarget &target) {
 759   const std::vector<const CodeGenInstruction*> &numberedInstructions =
 760     target.getInstructionsByEnumValue();
 761
 762   unsigned int index;
 763   unsigned int numInstructions = numberedInstructions.size();
 764
 765   for (index = 0; index < numInstructions; ++index) {
 766     const CodeGenInstruction& inst = *numberedInstructions[index];
 767
 768     CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
 769     infoArray.addEntry(infoStruct);
 770
 771     LiteralConstantEmitter *instType = new LiteralConstantEmitter;
 772     infoStruct->addEntry(instType);
 773
 774     LiteralConstantEmitter *numOperandsEmitter =
 775       new LiteralConstantEmitter(inst.Operands.size());
 776     infoStruct->addEntry(numOperandsEmitter);
 777
 778     CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter;
 779     infoStruct->addEntry(operandTypeArray);
 780
 781     LiteralConstantEmitter *operandTypes[EDIS_MAX_OPERANDS];
 782
 783     CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter;
 784     infoStruct->addEntry(operandFlagArray);
 785
 786     FlagsConstantEmitter *operandFlags[EDIS_MAX_OPERANDS];
 787
 788     for (unsigned operandIndex = 0;
 789          operandIndex < EDIS_MAX_OPERANDS;
 790          ++operandIndex) {
 791       operandTypes[operandIndex] = new LiteralConstantEmitter;
 792       operandTypeArray->addEntry(operandTypes[operandIndex]);
 793
 794       operandFlags[operandIndex] = new FlagsConstantEmitter;
 795       operandFlagArray->addEntry(operandFlags[operandIndex]);
 796     }
 797
 798     unsigned numSyntaxes = 0;
 799
 800     if (target.getName() == "X86") {
 801       X86PopulateOperands(operandTypes, inst);
 802       X86ExtractSemantics(*instType, operandFlags, inst);
 803       numSyntaxes = 2;
 804     }
 805     else if (target.getName() == "ARM") {
 806       ARMPopulateOperands(operandTypes, inst);
 807       ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
 808       numSyntaxes = 1;
 809     }
 810
 811     CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
 812
 813     infoStruct->addEntry(operandOrderArray);
 814
 815     for (unsigned syntaxIndex = 0;
 816          syntaxIndex < EDIS_MAX_SYNTAXES;
 817          ++syntaxIndex) {
 818       CompoundConstantEmitter *operandOrder =
 819         new CompoundConstantEmitter(EDIS_MAX_OPERANDS);
 820
 821       operandOrderArray->addEntry(operandOrder);
 822
 823       if (syntaxIndex < numSyntaxes) {
 824         populateOperandOrder(operandOrder, inst, syntaxIndex);
 825       }
 826     }
 827
 828     infoStruct = NULL;
 829   }
 830 }
 831
 832 static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
 833   EnumEmitter operandTypes("OperandTypes");
 834   operandTypes.addEntry("kOperandTypeNone");
 835   operandTypes.addEntry("kOperandTypeImmediate");
 836   operandTypes.addEntry("kOperandTypeRegister");
 837   operandTypes.addEntry("kOperandTypeX86Memory");
 838   operandTypes.addEntry("kOperandTypeX86EffectiveAddress");
 839   operandTypes.addEntry("kOperandTypeX86PCRelative");
 840   operandTypes.addEntry("kOperandTypeARMBranchTarget");
 841   operandTypes.addEntry("kOperandTypeARMSoReg");
 842   operandTypes.addEntry("kOperandTypeARMSoImm");
 843   operandTypes.addEntry("kOperandTypeARMRotImm");
 844   operandTypes.addEntry("kOperandTypeARMSoImm2Part");
 845   operandTypes.addEntry("kOperandTypeARMPredicate");
 846   operandTypes.addEntry("kOperandTypeAddrModeImm12");
 847   operandTypes.addEntry("kOperandTypeLdStSOReg");
 848   operandTypes.addEntry("kOperandTypeARMAddrMode2");
 849   operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
 850   operandTypes.addEntry("kOperandTypeARMAddrMode3");
 851   operandTypes.addEntry("kOperandTypeARMAddrMode3Offset");
 852   operandTypes.addEntry("kOperandTypeARMLdStmMode");
 853   operandTypes.addEntry("kOperandTypeARMAddrMode5");
 854   operandTypes.addEntry("kOperandTypeARMAddrMode6");
 855   operandTypes.addEntry("kOperandTypeARMAddrMode6Offset");
 856   operandTypes.addEntry("kOperandTypeARMAddrModePC");
 857   operandTypes.addEntry("kOperandTypeARMRegisterList");
 858   operandTypes.addEntry("kOperandTypeARMDPRRegisterList");
 859   operandTypes.addEntry("kOperandTypeARMSPRRegisterList");
 860   operandTypes.addEntry("kOperandTypeARMTBAddrMode");
 861   operandTypes.addEntry("kOperandTypeThumbITMask");
 862   operandTypes.addEntry("kOperandTypeThumbAddrModeRegS");
 863   operandTypes.addEntry("kOperandTypeThumbAddrModeImmS");
 864   operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
 865   operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
 866   operandTypes.addEntry("kOperandTypeThumbAddrModePC");
 867   operandTypes.addEntry("kOperandTypeThumb2SoReg");
 868   operandTypes.addEntry("kOperandTypeThumb2SoImm");
 869   operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
 870   operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
 871   operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
 872   operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
 873   operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
 874   operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset");
 875   operandTypes.emit(o, i);
 876
 877   o << "\n";
 878
 879   EnumEmitter operandFlags("OperandFlags");
 880   operandFlags.addEntry("kOperandFlagSource");
 881   operandFlags.addEntry("kOperandFlagTarget");
 882   operandFlags.emitAsFlags(o, i);
 883
 884   o << "\n";
 885
 886   EnumEmitter instructionTypes("InstructionTypes");
 887   instructionTypes.addEntry("kInstructionTypeNone");
 888   instructionTypes.addEntry("kInstructionTypeMove");
 889   instructionTypes.addEntry("kInstructionTypeBranch");
 890   instructionTypes.addEntry("kInstructionTypePush");
 891   instructionTypes.addEntry("kInstructionTypePop");
 892   instructionTypes.addEntry("kInstructionTypeCall");
 893   instructionTypes.addEntry("kInstructionTypeReturn");
 894   instructionTypes.emit(o, i);
 895
 896   o << "\n";
 897 }
 898
 899 void EDEmitter::run(raw_ostream &o) {
 900   unsigned int i = 0;
 901
 902   CompoundConstantEmitter infoArray;
 903   CodeGenTarget target(Records);
 904
 905   populateInstInfo(infoArray, target);
 906
 907   emitCommonEnums(o, i);
 908
 909   o << "namespace {\n";
 910
 911   o << "llvm::EDInstInfo instInfo" << target.getName().c_str() << "[] = ";
 912   infoArray.emit(o, i);
 913   o << ";" << "\n";
 914
 915   o << "}\n";
 916 }