lib/Support/Host.cpp

   1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //  This header file implements the operating system Host concept.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/Support/Host.h"
  15 #include "llvm/Config/config.h"
  16 #include <string.h>
  17
  18 // Include the platform-specific parts of this class.
  19 #ifdef LLVM_ON_UNIX
  20 #include "Unix/Host.inc"
  21 #endif
  22 #ifdef LLVM_ON_WIN32
  23 #include "Windows/Host.inc"
  24 #endif
  25 #ifdef _MSC_VER
  26 #include <intrin.h>
  27 #endif
  28
  29 //===----------------------------------------------------------------------===//
  30 //
  31 //  Implementations of the CPU detection routines
  32 //
  33 //===----------------------------------------------------------------------===//
  34
  35 using namespace llvm;
  36
  37 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
  38  || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
  39
  40 /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
  41 /// specified arguments.  If we can't run cpuid on the host, return true.
  42 static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX,
  43                             unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
  44 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
  45   #if defined(__GNUC__)
  46     // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
  47     asm ("movq\t%%rbx, %%rsi\n\t"
  48          "cpuid\n\t"
  49          "xchgq\t%%rbx, %%rsi\n\t"
  50          : "=a" (*rEAX),
  51            "=S" (*rEBX),
  52            "=c" (*rECX),
  53            "=d" (*rEDX)
  54          :  "a" (value));
  55     return false;
  56   #elif defined(_MSC_VER)
  57     int registers[4];
  58     __cpuid(registers, value);
  59     *rEAX = registers[0];
  60     *rEBX = registers[1];
  61     *rECX = registers[2];
  62     *rEDX = registers[3];
  63     return false;
  64   #endif
  65 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
  66   #if defined(__GNUC__)
  67     asm ("movl\t%%ebx, %%esi\n\t"
  68          "cpuid\n\t"
  69          "xchgl\t%%ebx, %%esi\n\t"
  70          : "=a" (*rEAX),
  71            "=S" (*rEBX),
  72            "=c" (*rECX),
  73            "=d" (*rEDX)
  74          :  "a" (value));
  75     return false;
  76   #elif defined(_MSC_VER)
  77     __asm {
  78       mov   eax,value
  79       cpuid
  80       mov   esi,rEAX
  81       mov   dword ptr [esi],eax
  82       mov   esi,rEBX
  83       mov   dword ptr [esi],ebx
  84       mov   esi,rECX
  85       mov   dword ptr [esi],ecx
  86       mov   esi,rEDX
  87       mov   dword ptr [esi],edx
  88     }
  89     return false;
  90   #endif
  91 #endif
  92   return true;
  93 }
  94
  95 static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
  96                                  unsigned &Model) {
  97   Family = (EAX >> 8) & 0xf; // Bits 8 - 11
  98   Model  = (EAX >> 4) & 0xf; // Bits 4 - 7
  99   if (Family == 6 || Family == 0xf) {
 100     if (Family == 0xf)
 101       // Examine extended family ID if family ID is F.
 102       Family += (EAX >> 20) & 0xff;    // Bits 20 - 27
 103     // Examine extended model ID if family ID is 6 or F.
 104     Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
 105   }
 106 }
 107
 108 std::string sys::getHostCPUName() {
 109   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
 110   if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
 111     return "generic";
 112   unsigned Family = 0;
 113   unsigned Model  = 0;
 114   DetectX86FamilyModel(EAX, Family, Model);
 115
 116   bool HasSSE3 = (ECX & 0x1);
 117   GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
 118   bool Em64T = (EDX >> 29) & 0x1;
 119
 120   union {
 121     unsigned u[3];
 122     char     c[12];
 123   } text;
 124
 125   GetX86CpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
 126   if (memcmp(text.c, "GenuineIntel", 12) == 0) {
 127     switch (Family) {
 128     case 3:
 129       return "i386";
 130     case 4:
 131       switch (Model) {
 132       case 0: // Intel486 DX processors
 133       case 1: // Intel486 DX processors
 134       case 2: // Intel486 SX processors
 135       case 3: // Intel487 processors, IntelDX2 OverDrive processors,
 136               // IntelDX2 processors
 137       case 4: // Intel486 SL processor
 138       case 5: // IntelSX2 processors
 139       case 7: // Write-Back Enhanced IntelDX2 processors
 140       case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
 141       default: return "i486";
 142       }
 143     case 5:
 144       switch (Model) {
 145       case  1: // Pentium OverDrive processor for Pentium processor (60, 66),
 146                // Pentium processors (60, 66)
 147       case  2: // Pentium OverDrive processor for Pentium processor (75, 90,
 148                // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
 149                // 150, 166, 200)
 150       case  3: // Pentium OverDrive processors for Intel486 processor-based
 151                // systems
 152         return "pentium";
 153
 154       case  4: // Pentium OverDrive processor with MMX technology for Pentium
 155                // processor (75, 90, 100, 120, 133), Pentium processor with
 156                // MMX technology (166, 200)
 157         return "pentium-mmx";
 158
 159       default: return "pentium";
 160       }
 161     case 6:
 162       switch (Model) {
 163       case  1: // Pentium Pro processor
 164         return "pentiumpro";
 165
 166       case  3: // Intel Pentium II OverDrive processor, Pentium II processor,
 167                // model 03
 168       case  5: // Pentium II processor, model 05, Pentium II Xeon processor,
 169                // model 05, and Intel Celeron processor, model 05
 170       case  6: // Celeron processor, model 06
 171         return "pentium2";
 172
 173       case  7: // Pentium III processor, model 07, and Pentium III Xeon
 174                // processor, model 07
 175       case  8: // Pentium III processor, model 08, Pentium III Xeon processor,
 176                // model 08, and Celeron processor, model 08
 177       case 10: // Pentium III Xeon processor, model 0Ah
 178       case 11: // Pentium III processor, model 0Bh
 179         return "pentium3";
 180
 181       case  9: // Intel Pentium M processor, Intel Celeron M processor model 09.
 182       case 13: // Intel Pentium M processor, Intel Celeron M processor, model
 183                // 0Dh. All processors are manufactured using the 90 nm process.
 184         return "pentium-m";
 185
 186       case 14: // Intel Core Duo processor, Intel Core Solo processor, model
 187                // 0Eh. All processors are manufactured using the 65 nm process.
 188         return "yonah";
 189
 190       case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
 191                // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
 192                // mobile processor, Intel Core 2 Extreme processor, Intel
 193                // Pentium Dual-Core processor, Intel Xeon processor, model
 194                // 0Fh. All processors are manufactured using the 65 nm process.
 195       case 22: // Intel Celeron processor model 16h. All processors are
 196                // manufactured using the 65 nm process
 197         return "core2";
 198
 199       case 21: // Intel EP80579 Integrated Processor and Intel EP80579
 200                // Integrated Processor with Intel QuickAssist Technology
 201         return "i686"; // FIXME: ???
 202
 203       case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model
 204                // 17h. All processors are manufactured using the 45 nm process.
 205                //
 206                // 45nm: Penryn , Wolfdale, Yorkfield (XE)
 207         return "penryn";
 208
 209       case 26: // Intel Core i7 processor and Intel Xeon processor. All
 210                // processors are manufactured using the 45 nm process.
 211       case 29: // Intel Xeon processor MP. All processors are manufactured using
 212                // the 45 nm process.
 213       case 30: // Intel(R) Core(TM) i7 CPU         870  @ 2.93GHz.
 214                // As found in a Summer 2010 model iMac.
 215       case 37: // Intel Core i7, laptop version.
 216         return "corei7";
 217
 218       // SandyBridge:
 219       case 42: // Intel Core i7 processor. All processors are manufactured
 220                // using the 32 nm process.
 221       case 44: // Intel Core i7 processor and Intel Xeon processor. All
 222                // processors are manufactured using the 32 nm process.
 223       case 45:
 224         return "corei7-avx";
 225
 226       case 28: // Intel Atom processor. All processors are manufactured using
 227                // the 45 nm process
 228         return "atom";
 229
 230       default: return "i686";
 231       }
 232     case 15: {
 233       switch (Model) {
 234       case  0: // Pentium 4 processor, Intel Xeon processor. All processors are
 235                // model 00h and manufactured using the 0.18 micron process.
 236       case  1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
 237                // processor MP, and Intel Celeron processor. All processors are
 238                // model 01h and manufactured using the 0.18 micron process.
 239       case  2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
 240                // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
 241                // processor, and Mobile Intel Celeron processor. All processors
 242                // are model 02h and manufactured using the 0.13 micron process.
 243         return (Em64T) ? "x86-64" : "pentium4";
 244
 245       case  3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
 246                // processor. All processors are model 03h and manufactured using
 247                // the 90 nm process.
 248       case  4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
 249                // Pentium D processor, Intel Xeon processor, Intel Xeon
 250                // processor MP, Intel Celeron D processor. All processors are
 251                // model 04h and manufactured using the 90 nm process.
 252       case  6: // Pentium 4 processor, Pentium D processor, Pentium processor
 253                // Extreme Edition, Intel Xeon processor, Intel Xeon processor
 254                // MP, Intel Celeron D processor. All processors are model 06h
 255                // and manufactured using the 65 nm process.
 256         return (Em64T) ? "nocona" : "prescott";
 257
 258       default:
 259         return (Em64T) ? "x86-64" : "pentium4";
 260       }
 261     }
 262
 263     default:
 264       return "generic";
 265     }
 266   } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
 267     // FIXME: this poorly matches the generated SubtargetFeatureKV table.  There
 268     // appears to be no way to generate the wide variety of AMD-specific targets
 269     // from the information returned from CPUID.
 270     switch (Family) {
 271       case 4:
 272         return "i486";
 273       case 5:
 274         switch (Model) {
 275         case 6:
 276         case 7:  return "k6";
 277         case 8:  return "k6-2";
 278         case 9:
 279         case 13: return "k6-3";
 280         default: return "pentium";
 281         }
 282       case 6:
 283         switch (Model) {
 284         case 4:  return "athlon-tbird";
 285         case 6:
 286         case 7:
 287         case 8:  return "athlon-mp";
 288         case 10: return "athlon-xp";
 289         default: return "athlon";
 290         }
 291       case 15:
 292         if (HasSSE3)
 293           return "k8-sse3";
 294         switch (Model) {
 295         case 1:  return "opteron";
 296         case 5:  return "athlon-fx"; // also opteron
 297         default: return "athlon64";
 298         }
 299       case 16:
 300         return "amdfam10";
 301     default:
 302       return "generic";
 303     }
 304   }
 305   return "generic";
 306 }
 307 #else
 308 std::string sys::getHostCPUName() {
 309   return "generic";
 310 }
 311 #endif
 312
 313 bool sys::getHostCPUFeatures(StringMap<bool> &Features){
 314   return false;
 315 }