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Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not proper...
[llvm/stm8.git] / lib / Target / ARM / Disassembler / ThumbDisassemblerCore.h
blobf80c92a683c608d6d308e92f078fe5ae653ece3e
1 //===- ThumbDisassemblerCore.h - Thumb disassembler helpers -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the ARM Disassembler.
11 // It contains code for disassembling a Thumb instr. It is to be included by
12 // ARMDisassemblerCore.cpp because it contains the static DisassembleThumbFrm()
13 // function which acts as the dispatcher to disassemble a Thumb instruction.
14 //
15 //===----------------------------------------------------------------------===//
16
17 ///////////////////////////////
18 // //
19 // Utility Functions //
20 // //
21 ///////////////////////////////
22
23 // Utilities for 16-bit Thumb instructions.
24 /*
25 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
26 [ tRt ]
27 [ tRm ] [ tRn ] [ tRd ]
28 D [ Rm ] [ Rd ]
29
30 [ imm3]
31 [ imm5 ]
32 i [ imm5 ]
33 [ imm7 ]
34 [ imm8 ]
35 [ imm11 ]
36
37 [ cond ]
38 */
39
40 // Extract tRt: Inst{10-8}.
41 static inline unsigned getT1tRt(uint32_t insn) {
42 return slice(insn, 10, 8);
43 }
44
45 // Extract tRm: Inst{8-6}.
46 static inline unsigned getT1tRm(uint32_t insn) {
47 return slice(insn, 8, 6);
48 }
49
50 // Extract tRn: Inst{5-3}.
51 static inline unsigned getT1tRn(uint32_t insn) {
52 return slice(insn, 5, 3);
53 }
54
55 // Extract tRd: Inst{2-0}.
56 static inline unsigned getT1tRd(uint32_t insn) {
57 return slice(insn, 2, 0);
58 }
59
60 // Extract [D:Rd]: Inst{7:2-0}.
61 static inline unsigned getT1Rd(uint32_t insn) {
62 return slice(insn, 7, 7) << 3 | slice(insn, 2, 0);
63 }
64
65 // Extract Rm: Inst{6-3}.
66 static inline unsigned getT1Rm(uint32_t insn) {
67 return slice(insn, 6, 3);
68 }
69
70 // Extract imm3: Inst{8-6}.
71 static inline unsigned getT1Imm3(uint32_t insn) {
72 return slice(insn, 8, 6);
73 }
74
75 // Extract imm5: Inst{10-6}.
76 static inline unsigned getT1Imm5(uint32_t insn) {
77 return slice(insn, 10, 6);
78 }
79
80 // Extract i:imm5: Inst{9:7-3}.
81 static inline unsigned getT1Imm6(uint32_t insn) {
82 return slice(insn, 9, 9) << 5 | slice(insn, 7, 3);
83 }
84
85 // Extract imm7: Inst{6-0}.
86 static inline unsigned getT1Imm7(uint32_t insn) {
87 return slice(insn, 6, 0);
88 }
89
90 // Extract imm8: Inst{7-0}.
91 static inline unsigned getT1Imm8(uint32_t insn) {
92 return slice(insn, 7, 0);
93 }
94
95 // Extract imm11: Inst{10-0}.
96 static inline unsigned getT1Imm11(uint32_t insn) {
97 return slice(insn, 10, 0);
98 }
99
100 // Extract cond: Inst{11-8}.
101 static inline unsigned getT1Cond(uint32_t insn) {
102 return slice(insn, 11, 8);
103 }
104
105 static inline bool IsGPR(unsigned RegClass) {
106 return RegClass == ARM::GPRRegClassID || RegClass == ARM::rGPRRegClassID;
107 }
108
109 // Utilities for 32-bit Thumb instructions.
110
111 static inline bool BadReg(uint32_t n) { return n == 13 || n == 15; }
112
113 // Extract imm4: Inst{19-16}.
114 static inline unsigned getImm4(uint32_t insn) {
115 return slice(insn, 19, 16);
116 }
117
118 // Extract imm3: Inst{14-12}.
119 static inline unsigned getImm3(uint32_t insn) {
120 return slice(insn, 14, 12);
121 }
122
123 // Extract imm8: Inst{7-0}.
124 static inline unsigned getImm8(uint32_t insn) {
125 return slice(insn, 7, 0);
126 }
127
128 // A8.6.61 LDRB (immediate, Thumb) and friends
129 // +/-: Inst{9}
130 // imm8: Inst{7-0}
131 static inline int decodeImm8(uint32_t insn) {
132 int Offset = getImm8(insn);
133 return slice(insn, 9, 9) ? Offset : -Offset;
134 }
135
136 // Extract imm12: Inst{11-0}.
137 static inline unsigned getImm12(uint32_t insn) {
138 return slice(insn, 11, 0);
139 }
140
141 // A8.6.63 LDRB (literal) and friends
142 // +/-: Inst{23}
143 // imm12: Inst{11-0}
144 static inline int decodeImm12(uint32_t insn) {
145 int Offset = getImm12(insn);
146 return slice(insn, 23, 23) ? Offset : -Offset;
147 }
148
149 // Extract imm2: Inst{7-6}.
150 static inline unsigned getImm2(uint32_t insn) {
151 return slice(insn, 7, 6);
152 }
153
154 // For BFI, BFC, t2SBFX, and t2UBFX.
155 // Extract lsb: Inst{14-12:7-6}.
156 static inline unsigned getLsb(uint32_t insn) {
157 return getImm3(insn) << 2 | getImm2(insn);
158 }
159
160 // For BFI and BFC.
161 // Extract msb: Inst{4-0}.
162 static inline unsigned getMsb(uint32_t insn) {
163 return slice(insn, 4, 0);
164 }
165
166 // For t2SBFX and t2UBFX.
167 // Extract widthminus1: Inst{4-0}.
168 static inline unsigned getWidthMinus1(uint32_t insn) {
169 return slice(insn, 4, 0);
170 }
171
172 // For t2ADDri12 and t2SUBri12.
173 // imm12 = i:imm3:imm8;
174 static inline unsigned getIImm3Imm8(uint32_t insn) {
175 return slice(insn, 26, 26) << 11 | getImm3(insn) << 8 | getImm8(insn);
176 }
177
178 // For t2MOVi16 and t2MOVTi16.
179 // imm16 = imm4:i:imm3:imm8;
180 static inline unsigned getImm16(uint32_t insn) {
181 return getImm4(insn) << 12 | slice(insn, 26, 26) << 11 |
182 getImm3(insn) << 8 | getImm8(insn);
183 }
184
185 // Inst{5-4} encodes the shift type.
186 static inline unsigned getShiftTypeBits(uint32_t insn) {
187 return slice(insn, 5, 4);
188 }
189
190 // Inst{14-12}:Inst{7-6} encodes the imm5 shift amount.
191 static inline unsigned getShiftAmtBits(uint32_t insn) {
192 return getImm3(insn) << 2 | getImm2(insn);
193 }
194
195 // A8.6.17 BFC
196 // Encoding T1 ARMv6T2, ARMv7
197 // LLVM-specific encoding for #<lsb> and #<width>
198 static inline bool getBitfieldInvMask(uint32_t insn, uint32_t &mask) {
199 uint32_t lsb = getImm3(insn) << 2 | getImm2(insn);
200 uint32_t msb = getMsb(insn);
201 uint32_t Val = 0;
202 if (msb < lsb) {
203 DEBUG(errs() << "Encoding error: msb < lsb\n");
204 return false;
205 }
206 for (uint32_t i = lsb; i <= msb; ++i)
207 Val |= (1 << i);
208 mask = ~Val;
209 return true;
210 }
211
212 // A8.4 Shifts applied to a register
213 // A8.4.1 Constant shifts
214 // A8.4.3 Pseudocode details of instruction-specified shifts and rotates
215 //
216 // decodeImmShift() returns the shift amount and the the shift opcode.
217 // Note that, as of Jan-06-2010, LLVM does not support rrx shifted operands yet.
218 static inline unsigned decodeImmShift(unsigned bits2, unsigned imm5,
219 ARM_AM::ShiftOpc &ShOp) {
220
221 assert(imm5 < 32 && "Invalid imm5 argument");
222 switch (bits2) {
223 default: assert(0 && "No such value");
224 case 0:
225 ShOp = (imm5 == 0 ? ARM_AM::no_shift : ARM_AM::lsl);
226 return imm5;
227 case 1:
228 ShOp = ARM_AM::lsr;
229 return (imm5 == 0 ? 32 : imm5);
230 case 2:
231 ShOp = ARM_AM::asr;
232 return (imm5 == 0 ? 32 : imm5);
233 case 3:
234 ShOp = (imm5 == 0 ? ARM_AM::rrx : ARM_AM::ror);
235 return (imm5 == 0 ? 1 : imm5);
236 }
237 }
238
239 // A6.3.2 Modified immediate constants in Thumb instructions
240 //
241 // ThumbExpandImm() returns the modified immediate constant given an imm12 for
242 // Thumb data-processing instructions with modified immediate.
243 // See also A6.3.1 Data-processing (modified immediate).
244 static inline unsigned ThumbExpandImm(unsigned imm12) {
245 assert(imm12 <= 0xFFF && "Invalid imm12 argument");
246
247 // If the leading two bits is 0b00, the modified immediate constant is
248 // obtained by splatting the low 8 bits into the first byte, every other byte,
249 // or every byte of a 32-bit value.
250 //
251 // Otherwise, a rotate right of '1':imm12<6:0> by the amount imm12<11:7> is
252 // performed.
253
254 if (slice(imm12, 11, 10) == 0) {
255 unsigned short control = slice(imm12, 9, 8);
256 unsigned imm8 = slice(imm12, 7, 0);
257 switch (control) {
258 default:
259 assert(0 && "No such value");
260 return 0;
261 case 0:
262 return imm8;
263 case 1:
264 return imm8 << 16 | imm8;
265 case 2:
266 return imm8 << 24 | imm8 << 8;
267 case 3:
268 return imm8 << 24 | imm8 << 16 | imm8 << 8 | imm8;
269 }
270 } else {
271 // A rotate is required.
272 unsigned Val = 1 << 7 | slice(imm12, 6, 0);
273 unsigned Amt = slice(imm12, 11, 7);
274 return ARM_AM::rotr32(Val, Amt);
275 }
276 }
277
278 static inline int decodeImm32_B_EncodingT3(uint32_t insn) {
279 bool S = slice(insn, 26, 26);
280 bool J1 = slice(insn, 13, 13);
281 bool J2 = slice(insn, 11, 11);
282 unsigned Imm21 = slice(insn, 21, 16) << 12 | slice(insn, 10, 0) << 1;
283 if (S) Imm21 |= 1 << 20;
284 if (J2) Imm21 |= 1 << 19;
285 if (J1) Imm21 |= 1 << 18;
286
287 return SignExtend32<21>(Imm21);
288 }
289
290 static inline int decodeImm32_B_EncodingT4(uint32_t insn) {
291 unsigned S = slice(insn, 26, 26);
292 bool I1 = slice(insn, 13, 13) == S;
293 bool I2 = slice(insn, 11, 11) == S;
294 unsigned Imm25 = slice(insn, 25, 16) << 12 | slice(insn, 10, 0) << 1;
295 if (S) Imm25 |= 1 << 24;
296 if (I1) Imm25 |= 1 << 23;
297 if (I2) Imm25 |= 1 << 22;
298
299 return SignExtend32<25>(Imm25);
300 }
301
302 static inline int decodeImm32_BL(uint32_t insn) {
303 unsigned S = slice(insn, 26, 26);
304 bool I1 = slice(insn, 13, 13) == S;
305 bool I2 = slice(insn, 11, 11) == S;
306 unsigned Imm25 = slice(insn, 25, 16) << 12 | slice(insn, 10, 0) << 1;
307 if (S) Imm25 |= 1 << 24;
308 if (I1) Imm25 |= 1 << 23;
309 if (I2) Imm25 |= 1 << 22;
310
311 return SignExtend32<25>(Imm25);
312 }
313
314 static inline int decodeImm32_BLX(uint32_t insn) {
315 unsigned S = slice(insn, 26, 26);
316 bool I1 = slice(insn, 13, 13) == S;
317 bool I2 = slice(insn, 11, 11) == S;
318 unsigned Imm25 = slice(insn, 25, 16) << 12 | slice(insn, 10, 1) << 2;
319 if (S) Imm25 |= 1 << 24;
320 if (I1) Imm25 |= 1 << 23;
321 if (I2) Imm25 |= 1 << 22;
322
323 return SignExtend32<25>(Imm25);
324 }
325
326 // See, for example, A8.6.221 SXTAB16.
327 static inline unsigned decodeRotate(uint32_t insn) {
328 unsigned rotate = slice(insn, 5, 4);
329 return rotate << 3;
330 }
331
332 ///////////////////////////////////////////////
333 // //
334 // Thumb1 instruction disassembly functions. //
335 // //
336 ///////////////////////////////////////////////
337
338 // See "Utilities for 16-bit Thumb instructions" for register naming convention.
339
340 // A6.2.1 Shift (immediate), add, subtract, move, and compare
341 //
342 // shift immediate: tRd CPSR tRn imm5
343 // add/sub register: tRd CPSR tRn tRm
344 // add/sub 3-bit immediate: tRd CPSR tRn imm3
345 // add/sub 8-bit immediate: tRt CPSR tRt(TIED_TO) imm8
346 // mov/cmp immediate: tRt [CPSR] imm8 (CPSR present for mov)
347 //
348 // Special case:
349 // tMOVSr: tRd tRn
350 static bool DisassembleThumb1General(MCInst &MI, unsigned Opcode, uint32_t insn,
351 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
352
353 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
354 unsigned &OpIdx = NumOpsAdded;
355
356 OpIdx = 0;
357
358 assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID
359 && "Invalid arguments");
360
361 bool Imm3 = (Opcode == ARM::tADDi3 || Opcode == ARM::tSUBi3);
362
363 // Use Rt implies use imm8.
364 bool UseRt = (Opcode == ARM::tADDi8 || Opcode == ARM::tSUBi8 ||
365 Opcode == ARM::tMOVi8 || Opcode == ARM::tCMPi8);
366
367 // Add the destination operand.
368 MI.addOperand(MCOperand::CreateReg(
369 getRegisterEnum(B, ARM::tGPRRegClassID,
370 UseRt ? getT1tRt(insn) : getT1tRd(insn))));
371 ++OpIdx;
372
373 // Check whether the next operand to be added is a CCR Register.
374 if (OpInfo[OpIdx].RegClass == ARM::CCRRegClassID) {
375 assert(OpInfo[OpIdx].isOptionalDef() && "Optional def operand expected");
376 MI.addOperand(MCOperand::CreateReg(B->InITBlock() ? 0 : ARM::CPSR));
377 ++OpIdx;
378 }
379
380 // Check whether the next operand to be added is a Thumb1 Register.
381 assert(OpIdx < NumOps && "More operands expected");
382 if (OpInfo[OpIdx].RegClass == ARM::tGPRRegClassID) {
383 // For UseRt, the reg operand is tied to the first reg operand.
384 MI.addOperand(MCOperand::CreateReg(
385 getRegisterEnum(B, ARM::tGPRRegClassID,
386 UseRt ? getT1tRt(insn) : getT1tRn(insn))));
387 ++OpIdx;
388 }
389
390 // Special case for tMOVSr.
391 if (OpIdx == NumOps)
392 return true;
393
394 // The next available operand is either a reg operand or an imm operand.
395 if (OpInfo[OpIdx].RegClass == ARM::tGPRRegClassID) {
396 // Three register operand instructions.
397 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
398 getT1tRm(insn))));
399 } else {
400 assert(OpInfo[OpIdx].RegClass < 0 &&
401 !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()
402 && "Pure imm operand expected");
403 unsigned Imm = 0;
404 if (UseRt)
405 Imm = getT1Imm8(insn);
406 else if (Imm3)
407 Imm = getT1Imm3(insn);
408 else {
409 Imm = getT1Imm5(insn);
410 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 12, 11));
411 getImmShiftSE(ShOp, Imm);
412 }
413 MI.addOperand(MCOperand::CreateImm(Imm));
414 }
415 ++OpIdx;
416
417 return true;
418 }
419
420 // A6.2.2 Data-processing
421 //
422 // tCMPr, tTST, tCMN: tRd tRn
423 // tMVN, tRSB: tRd CPSR tRn
424 // Others: tRd CPSR tRd(TIED_TO) tRn
425 static bool DisassembleThumb1DP(MCInst &MI, unsigned Opcode, uint32_t insn,
426 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
427
428 const TargetInstrDesc &TID = ARMInsts[Opcode];
429 const TargetOperandInfo *OpInfo = TID.OpInfo;
430 unsigned &OpIdx = NumOpsAdded;
431
432 OpIdx = 0;
433
434 assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
435 (OpInfo[1].RegClass == ARM::CCRRegClassID
436 || OpInfo[1].RegClass == ARM::tGPRRegClassID)
437 && "Invalid arguments");
438
439 // Add the destination operand.
440 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
441 getT1tRd(insn))));
442 ++OpIdx;
443
444 // Check whether the next operand to be added is a CCR Register.
445 if (OpInfo[OpIdx].RegClass == ARM::CCRRegClassID) {
446 assert(OpInfo[OpIdx].isOptionalDef() && "Optional def operand expected");
447 MI.addOperand(MCOperand::CreateReg(B->InITBlock() ? 0 : ARM::CPSR));
448 ++OpIdx;
449 }
450
451 // We have either { tRd(TIED_TO), tRn } or { tRn } remaining.
452 // Process the TIED_TO operand first.
453
454 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::tGPRRegClassID
455 && "Thumb reg operand expected");
456 int Idx;
457 if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
458 // The reg operand is tied to the first reg operand.
459 MI.addOperand(MI.getOperand(Idx));
460 ++OpIdx;
461 }
462
463 // Process possible next reg operand.
464 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::tGPRRegClassID) {
465 // Add tRn operand.
466 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
467 getT1tRn(insn))));
468 ++OpIdx;
469 }
470
471 return true;
472 }
473
474 // A6.2.3 Special data instructions and branch and exchange
475 //
476 // tADDhirr: Rd Rd(TIED_TO) Rm
477 // tCMPhir: Rd Rm
478 // tMOVr, tMOVgpr2gpr, tMOVgpr2tgpr, tMOVtgpr2gpr: Rd|tRd Rm|tRn
479 // tBX_RET: 0 operand
480 // tBX_RET_vararg: Rm
481 // tBLXr_r9: Rm
482 static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
483 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
484
485 // tBX_RET has 0 operand.
486 if (NumOps == 0)
487 return true;
488
489 // BX/BLX has 1 reg operand: Rm.
490 if (Opcode == ARM::tBLXr_r9 || Opcode == ARM::tBX_Rm) {
491 // Handling the two predicate operands before the reg operand.
492 if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps))
493 return false;
494 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
495 getT1Rm(insn))));
496 NumOpsAdded = 3;
497 return true;
498 }
499
500 const TargetInstrDesc &TID = ARMInsts[Opcode];
501 const TargetOperandInfo *OpInfo = TID.OpInfo;
502 unsigned &OpIdx = NumOpsAdded;
503
504 OpIdx = 0;
505
506 // Add the destination operand.
507 unsigned RegClass = OpInfo[OpIdx].RegClass;
508 MI.addOperand(MCOperand::CreateReg(
509 getRegisterEnum(B, RegClass,
510 IsGPR(RegClass) ? getT1Rd(insn)
511 : getT1tRd(insn))));
512 ++OpIdx;
513
514 // We have either { Rd(TIED_TO), Rm } or { Rm|tRn } remaining.
515 // Process the TIED_TO operand first.
516
517 assert(OpIdx < NumOps && "More operands expected");
518 int Idx;
519 if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
520 // The reg operand is tied to the first reg operand.
521 MI.addOperand(MI.getOperand(Idx));
522 ++OpIdx;
523 }
524
525 // The next reg operand is either Rm or tRn.
526 assert(OpIdx < NumOps && "More operands expected");
527 RegClass = OpInfo[OpIdx].RegClass;
528 MI.addOperand(MCOperand::CreateReg(
529 getRegisterEnum(B, RegClass,
530 IsGPR(RegClass) ? getT1Rm(insn)
531 : getT1tRn(insn))));
532 ++OpIdx;
533
534 return true;
535 }
536
537 // A8.6.59 LDR (literal)
538 //
539 // tLDRpci: tRt imm8*4
540 static bool DisassembleThumb1LdPC(MCInst &MI, unsigned Opcode, uint32_t insn,
541 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
542
543 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
544 if (!OpInfo) return false;
545
546 assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
547 (OpInfo[1].RegClass < 0 &&
548 !OpInfo[1].isPredicate() &&
549 !OpInfo[1].isOptionalDef())
550 && "Invalid arguments");
551
552 // Add the destination operand.
553 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
554 getT1tRt(insn))));
555
556 // And the (imm8 << 2) operand.
557 MI.addOperand(MCOperand::CreateImm(getT1Imm8(insn) << 2));
558
559 NumOpsAdded = 2;
560
561 return true;
562 }
563
564 // Thumb specific addressing modes (see ARMInstrThumb.td):
565 //
566 // t_addrmode_rr := reg + reg
567 //
568 // t_addrmode_s4 := reg + reg
569 // reg + imm5 * 4
570 //
571 // t_addrmode_s2 := reg + reg
572 // reg + imm5 * 2
573 //
574 // t_addrmode_s1 := reg + reg
575 // reg + imm5
576 //
577 // t_addrmode_sp := sp + imm8 * 4
578 //
579
580 // A8.6.63 LDRB (literal)
581 // A8.6.79 LDRSB (literal)
582 // A8.6.75 LDRH (literal)
583 // A8.6.83 LDRSH (literal)
584 // A8.6.59 LDR (literal)
585 //
586 // These instrs calculate an address from the PC value and an immediate offset.
587 // Rd Rn=PC (+/-)imm12 (+ if Inst{23} == 0b1)
588 static bool DisassembleThumb2Ldpci(MCInst &MI, unsigned Opcode,
589 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
590
591 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
592 if (!OpInfo) return false;
593
594 assert(NumOps >= 2 &&
595 OpInfo[0].RegClass == ARM::GPRRegClassID &&
596 OpInfo[1].RegClass < 0 &&
597 "Expect >= 2 operands, first as reg, and second as imm operand");
598
599 // Build the register operand, followed by the (+/-)imm12 immediate.
600
601 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
602 decodeRd(insn))));
603
604 MI.addOperand(MCOperand::CreateImm(decodeImm12(insn)));
605
606 NumOpsAdded = 2;
607
608 return true;
609 }
610
611
612 // A6.2.4 Load/store single data item
613 //
614 // Load/Store Register (reg|imm): tRd tRn imm5|tRm
615 // Load Register Signed Byte|Halfword: tRd tRn tRm
616 static bool DisassembleThumb1LdSt(unsigned opA, MCInst &MI, unsigned Opcode,
617 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
618
619 const TargetInstrDesc &TID = ARMInsts[Opcode];
620 const TargetOperandInfo *OpInfo = TID.OpInfo;
621 unsigned &OpIdx = NumOpsAdded;
622
623 assert(NumOps >= 2
624 && OpInfo[0].RegClass == ARM::tGPRRegClassID
625 && OpInfo[1].RegClass == ARM::tGPRRegClassID
626 && "Expect >= 2 operands and first two as thumb reg operands");
627
628 // Add the destination reg and the base reg.
629 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
630 getT1tRd(insn))));
631 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
632 getT1tRn(insn))));
633 OpIdx = 2;
634
635 // We have either { imm5 } or { tRm } remaining.
636 // Note that STR/LDR (register) should skip the imm5 offset operand for
637 // t_addrmode_s[1|2|4].
638
639 assert(OpIdx < NumOps && "More operands expected");
640
641 if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() &&
642 !OpInfo[OpIdx].isOptionalDef()) {
643 // Table A6-5 16-bit Thumb Load/store instructions
644 // opA = 0b0101 for STR/LDR (register) and friends.
645 // Otherwise, we have STR/LDR (immediate) and friends.
646 assert(opA != 5 && "Immediate operand expected for this opcode");
647 MI.addOperand(MCOperand::CreateImm(getT1Imm5(insn)));
648 ++OpIdx;
649 } else {
650 // The next reg operand is tRm, the offset.
651 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::tGPRRegClassID
652 && "Thumb reg operand expected");
653 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
654 getT1tRm(insn))));
655 ++OpIdx;
656 }
657 return true;
658 }
659
660 // A6.2.4 Load/store single data item
661 //
662 // Load/Store Register SP relative: tRt ARM::SP imm8
663 static bool DisassembleThumb1LdStSP(MCInst &MI, unsigned Opcode, uint32_t insn,
664 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
665
666 assert((Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi)
667 && "Unexpected opcode");
668
669 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
670 if (!OpInfo) return false;
671
672 assert(NumOps >= 3 &&
673 OpInfo[0].RegClass == ARM::tGPRRegClassID &&
674 OpInfo[1].RegClass == ARM::GPRRegClassID &&
675 (OpInfo[2].RegClass < 0 &&
676 !OpInfo[2].isPredicate() &&
677 !OpInfo[2].isOptionalDef())
678 && "Invalid arguments");
679
680 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
681 getT1tRt(insn))));
682 MI.addOperand(MCOperand::CreateReg(ARM::SP));
683 MI.addOperand(MCOperand::CreateImm(getT1Imm8(insn)));
684 NumOpsAdded = 3;
685 return true;
686 }
687
688 // Table A6-1 16-bit Thumb instruction encoding
689 // A8.6.10 ADR
690 //
691 // tADDrPCi: tRt imm8
692 static bool DisassembleThumb1AddPCi(MCInst &MI, unsigned Opcode, uint32_t insn,
693 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
694
695 assert(Opcode == ARM::tADDrPCi && "Unexpected opcode");
696
697 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
698 if (!OpInfo) return false;
699
700 assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
701 (OpInfo[1].RegClass < 0 &&
702 !OpInfo[1].isPredicate() &&
703 !OpInfo[1].isOptionalDef())
704 && "Invalid arguments");
705
706 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
707 getT1tRt(insn))));
708 MI.addOperand(MCOperand::CreateImm(getT1Imm8(insn)));
709 NumOpsAdded = 2;
710 return true;
711 }
712
713 // Table A6-1 16-bit Thumb instruction encoding
714 // A8.6.8 ADD (SP plus immediate)
715 //
716 // tADDrSPi: tRt ARM::SP imm8
717 static bool DisassembleThumb1AddSPi(MCInst &MI, unsigned Opcode, uint32_t insn,
718 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
719
720 assert(Opcode == ARM::tADDrSPi && "Unexpected opcode");
721
722 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
723 if (!OpInfo) return false;
724
725 assert(NumOps >= 3 &&
726 OpInfo[0].RegClass == ARM::tGPRRegClassID &&
727 OpInfo[1].RegClass == ARM::GPRRegClassID &&
728 (OpInfo[2].RegClass < 0 &&
729 !OpInfo[2].isPredicate() &&
730 !OpInfo[2].isOptionalDef())
731 && "Invalid arguments");
732
733 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
734 getT1tRt(insn))));
735 MI.addOperand(MCOperand::CreateReg(ARM::SP));
736 MI.addOperand(MCOperand::CreateImm(getT1Imm8(insn)));
737 NumOpsAdded = 3;
738 return true;
739 }
740
741 // tPUSH, tPOP: Pred-Imm Pred-CCR register_list
742 //
743 // where register_list = low registers + [lr] for PUSH or
744 // low registers + [pc] for POP
745 //
746 // "low registers" is specified by Inst{7-0}
747 // lr|pc is specified by Inst{8}
748 static bool DisassembleThumb1PushPop(MCInst &MI, unsigned Opcode, uint32_t insn,
749 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
750
751 assert((Opcode == ARM::tPUSH || Opcode == ARM::tPOP) && "Unexpected opcode");
752
753 unsigned &OpIdx = NumOpsAdded;
754
755 // Handling the two predicate operands before the reglist.
756 if (B->DoPredicateOperands(MI, Opcode, insn, NumOps))
757 OpIdx += 2;
758 else {
759 DEBUG(errs() << "Expected predicate operands not found.\n");
760 return false;
761 }
762
763 unsigned RegListBits = slice(insn, 8, 8) << (Opcode == ARM::tPUSH ? 14 : 15)
764 | slice(insn, 7, 0);
765
766 // Fill the variadic part of reglist.
767 for (unsigned i = 0; i < 16; ++i) {
768 if ((RegListBits >> i) & 1) {
769 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
770 i)));
771 ++OpIdx;
772 }
773 }
774
775 return true;
776 }
777
778 // A6.2.5 Miscellaneous 16-bit instructions
779 // Delegate to DisassembleThumb1PushPop() for tPUSH & tPOP.
780 //
781 // tADDspi, tSUBspi: ARM::SP ARM::SP(TIED_TO) imm7
782 // t2IT: firstcond=Inst{7-4} mask=Inst{3-0}
783 // tCBNZ, tCBZ: tRd imm6*2
784 // tBKPT: imm8
785 // tNOP, tSEV, tYIELD, tWFE, tWFI:
786 // no operand (except predicate pair)
787 // tSETENDBE, tSETENDLE, :
788 // no operand
789 // Others: tRd tRn
790 static bool DisassembleThumb1Misc(MCInst &MI, unsigned Opcode, uint32_t insn,
791 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
792
793 if (NumOps == 0)
794 return true;
795
796 if (Opcode == ARM::tPUSH || Opcode == ARM::tPOP)
797 return DisassembleThumb1PushPop(MI, Opcode, insn, NumOps, NumOpsAdded, B);
798
799 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
800
801 // Predicate operands are handled elsewhere.
802 if (NumOps == 2 &&
803 OpInfo[0].isPredicate() && OpInfo[1].isPredicate() &&
804 OpInfo[0].RegClass < 0 && OpInfo[1].RegClass == ARM::CCRRegClassID) {
805 return true;
806 }
807
808 if (Opcode == ARM::tADDspi || Opcode == ARM::tSUBspi) {
809 // Special case handling for tADDspi and tSUBspi.
810 // A8.6.8 ADD (SP plus immediate) & A8.6.215 SUB (SP minus immediate)
811 MI.addOperand(MCOperand::CreateReg(ARM::SP));
812 MI.addOperand(MCOperand::CreateReg(ARM::SP));
813 MI.addOperand(MCOperand::CreateImm(getT1Imm7(insn)));
814 NumOpsAdded = 3;
815 return true;
816 }
817
818 if (Opcode == ARM::t2IT) {
819 // Special case handling for If-Then.
820 // A8.6.50 IT
821 // Tag the (firstcond[0] bit << 4) along with mask.
822
823 // firstcond
824 MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 4)));
825
826 // firstcond[0] and mask
827 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0)));
828 NumOpsAdded = 2;
829 return true;
830 }
831
832 if (Opcode == ARM::tBKPT) {
833 MI.addOperand(MCOperand::CreateImm(getT1Imm8(insn))); // breakpoint value
834 NumOpsAdded = 1;
835 return true;
836 }
837
838 // CPS has a singleton $opt operand that contains the following information:
839 // The first op would be 0b10 as enable and 0b11 as disable in regular ARM,
840 // but in Thumb it's is 0 as enable and 1 as disable. So map it to ARM's
841 // default one. The second get the AIF flags from Inst{2-0}.
842 if (Opcode == ARM::tCPS) {
843 MI.addOperand(MCOperand::CreateImm(2 + slice(insn, 4, 4)));
844 MI.addOperand(MCOperand::CreateImm(slice(insn, 2, 0)));
845 NumOpsAdded = 2;
846 return true;
847 }
848
849 assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
850 (OpInfo[1].RegClass < 0 || OpInfo[1].RegClass==ARM::tGPRRegClassID)
851 && "Expect >=2 operands");
852
853 // Add the destination operand.
854 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
855 getT1tRd(insn))));
856
857 if (OpInfo[1].RegClass == ARM::tGPRRegClassID) {
858 // Two register instructions.
859 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
860 getT1tRn(insn))));
861 } else {
862 // CBNZ, CBZ
863 assert((Opcode == ARM::tCBNZ || Opcode == ARM::tCBZ) &&"Unexpected opcode");
864 MI.addOperand(MCOperand::CreateImm(getT1Imm6(insn) * 2));
865 }
866
867 NumOpsAdded = 2;
868
869 return true;
870 }
871
872 // A8.6.53 LDM / LDMIA
873 // A8.6.189 STM / STMIA
874 //
875 // tLDMIA_UPD/tSTMIA_UPD: tRt tRt AM4ModeImm Pred-Imm Pred-CCR register_list
876 // tLDMIA: tRt AM4ModeImm Pred-Imm Pred-CCR register_list
877 static bool DisassembleThumb1LdStMul(bool Ld, MCInst &MI, unsigned Opcode,
878 uint32_t insn, unsigned short NumOps,
879 unsigned &NumOpsAdded, BO B) {
880 assert((Opcode == ARM::tLDMIA || Opcode == ARM::tLDMIA_UPD ||
881 Opcode == ARM::tSTMIA_UPD) && "Unexpected opcode");
882
883 unsigned tRt = getT1tRt(insn);
884 NumOpsAdded = 0;
885
886 // WB register, if necessary.
887 if (Opcode == ARM::tLDMIA_UPD || Opcode == ARM::tSTMIA_UPD) {
888 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
889 tRt)));
890 ++NumOpsAdded;
891 }
892
893 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
894 tRt)));
895 ++NumOpsAdded;
896
897 // Handling the two predicate operands before the reglist.
898 if (B->DoPredicateOperands(MI, Opcode, insn, NumOps)) {
899 NumOpsAdded += 2;
900 } else {
901 DEBUG(errs() << "Expected predicate operands not found.\n");
902 return false;
903 }
904
905 unsigned RegListBits = slice(insn, 7, 0);
906 if (BitCount(RegListBits) < 1) {
907 DEBUG(errs() << "if BitCount(registers) < 1 then UNPREDICTABLE\n");
908 return false;
909 }
910
911 // Fill the variadic part of reglist.
912 for (unsigned i = 0; i < 8; ++i)
913 if ((RegListBits >> i) & 1) {
914 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
915 i)));
916 ++NumOpsAdded;
917 }
918
919 return true;
920 }
921
922 static bool DisassembleThumb1LdMul(MCInst &MI, unsigned Opcode, uint32_t insn,
923 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
924 return DisassembleThumb1LdStMul(true, MI, Opcode, insn, NumOps, NumOpsAdded,
925 B);
926 }
927
928 static bool DisassembleThumb1StMul(MCInst &MI, unsigned Opcode, uint32_t insn,
929 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
930 return DisassembleThumb1LdStMul(false, MI, Opcode, insn, NumOps, NumOpsAdded,
931 B);
932 }
933
934 // A8.6.16 B Encoding T1
935 // cond = Inst{11-8} & imm8 = Inst{7-0}
936 // imm32 = SignExtend(imm8:'0', 32)
937 //
938 // tBcc: offset Pred-Imm Pred-CCR
939 // tSVC: imm8 Pred-Imm Pred-CCR
940 // tTRAP: 0 operand (early return)
941 static bool DisassembleThumb1CondBr(MCInst &MI, unsigned Opcode, uint32_t insn,
942 unsigned short NumOps, unsigned &NumOpsAdded, BO) {
943
944 if (Opcode == ARM::tTRAP)
945 return true;
946
947 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
948 if (!OpInfo) return false;
949
950 assert(NumOps == 3 && OpInfo[0].RegClass < 0 &&
951 OpInfo[1].isPredicate() && OpInfo[2].RegClass == ARM::CCRRegClassID
952 && "Exactly 3 operands expected");
953
954 unsigned Imm8 = getT1Imm8(insn);
955 MI.addOperand(MCOperand::CreateImm(
956 Opcode == ARM::tBcc ? SignExtend32<9>(Imm8 << 1) + 4
957 : (int)Imm8));
958
959 // Predicate operands by ARMBasicMCBuilder::TryPredicateAndSBitModifier().
960 // But note that for tBcc, if cond = '1110' then UNDEFINED.
961 if (Opcode == ARM::tBcc && slice(insn, 11, 8) == 14) {
962 DEBUG(errs() << "if cond = '1110' then UNDEFINED\n");
963 return false;
964 }
965 NumOpsAdded = 1;
966
967 return true;
968 }
969
970 // A8.6.16 B Encoding T2
971 // imm11 = Inst{10-0}
972 // imm32 = SignExtend(imm11:'0', 32)
973 //
974 // tB: offset
975 static bool DisassembleThumb1Br(MCInst &MI, unsigned Opcode, uint32_t insn,
976 unsigned short NumOps, unsigned &NumOpsAdded, BO) {
977
978 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
979 if (!OpInfo) return false;
980
981 assert(NumOps == 1 && OpInfo[0].RegClass < 0 && "1 imm operand expected");
982
983 unsigned Imm11 = getT1Imm11(insn);
984
985 MI.addOperand(MCOperand::CreateImm(SignExtend32<12>(Imm11 << 1)));
986
987 NumOpsAdded = 1;
988
989 return true;
990
991 }
992
993 // See A6.2 16-bit Thumb instruction encoding for instruction classes
994 // corresponding to op.
995 //
996 // Table A6-1 16-bit Thumb instruction encoding (abridged)
997 // op Instruction or instruction class
998 // ------ --------------------------------------------------------------------
999 // 00xxxx Shift (immediate), add, subtract, move, and compare on page A6-7
1000 // 010000 Data-processing on page A6-8
1001 // 010001 Special data instructions and branch and exchange on page A6-9
1002 // 01001x Load from Literal Pool, see LDR (literal) on page A8-122
1003 // 0101xx Load/store single data item on page A6-10
1004 // 011xxx
1005 // 100xxx
1006 // 10100x Generate PC-relative address, see ADR on page A8-32
1007 // 10101x Generate SP-relative address, see ADD (SP plus immediate) on
1008 // page A8-28
1009 // 1011xx Miscellaneous 16-bit instructions on page A6-11
1010 // 11000x Store multiple registers, see STM / STMIA / STMEA on page A8-374
1011 // 11001x Load multiple registers, see LDM / LDMIA / LDMFD on page A8-110 a
1012 // 1101xx Conditional branch, and Supervisor Call on page A6-13
1013 // 11100x Unconditional Branch, see B on page A8-44
1014 //
1015 static bool DisassembleThumb1(uint16_t op, MCInst &MI, unsigned Opcode,
1016 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1017
1018 unsigned op1 = slice(op, 5, 4);
1019 unsigned op2 = slice(op, 3, 2);
1020 unsigned op3 = slice(op, 1, 0);
1021 unsigned opA = slice(op, 5, 2);
1022 switch (op1) {
1023 case 0:
1024 // A6.2.1 Shift (immediate), add, subtract, move, and compare
1025 return DisassembleThumb1General(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1026 case 1:
1027 switch (op2) {
1028 case 0:
1029 switch (op3) {
1030 case 0:
1031 // A6.2.2 Data-processing
1032 return DisassembleThumb1DP(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1033 case 1:
1034 // A6.2.3 Special data instructions and branch and exchange
1035 return DisassembleThumb1Special(MI, Opcode, insn, NumOps, NumOpsAdded,
1036 B);
1037 default:
1038 // A8.6.59 LDR (literal)
1039 return DisassembleThumb1LdPC(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1040 }
1041 break;
1042 default:
1043 // A6.2.4 Load/store single data item
1044 return DisassembleThumb1LdSt(opA, MI, Opcode, insn, NumOps, NumOpsAdded,
1045 B);
1046 break;
1047 }
1048 break;
1049 case 2:
1050 switch (op2) {
1051 case 0:
1052 // A6.2.4 Load/store single data item
1053 return DisassembleThumb1LdSt(opA, MI, Opcode, insn, NumOps, NumOpsAdded,
1054 B);
1055 case 1:
1056 // A6.2.4 Load/store single data item
1057 return DisassembleThumb1LdStSP(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1058 case 2:
1059 if (op3 <= 1) {
1060 // A8.6.10 ADR
1061 return DisassembleThumb1AddPCi(MI, Opcode, insn, NumOps, NumOpsAdded,
1062 B);
1063 } else {
1064 // A8.6.8 ADD (SP plus immediate)
1065 return DisassembleThumb1AddSPi(MI, Opcode, insn, NumOps, NumOpsAdded,
1066 B);
1067 }
1068 default:
1069 // A6.2.5 Miscellaneous 16-bit instructions
1070 return DisassembleThumb1Misc(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1071 }
1072 break;
1073 case 3:
1074 switch (op2) {
1075 case 0:
1076 if (op3 <= 1) {
1077 // A8.6.189 STM / STMIA / STMEA
1078 return DisassembleThumb1StMul(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1079 } else {
1080 // A8.6.53 LDM / LDMIA / LDMFD
1081 return DisassembleThumb1LdMul(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1082 }
1083 case 1:
1084 // A6.2.6 Conditional branch, and Supervisor Call
1085 return DisassembleThumb1CondBr(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1086 case 2:
1087 // Unconditional Branch, see B on page A8-44
1088 return DisassembleThumb1Br(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1089 default:
1090 assert(0 && "Unreachable code");
1091 break;
1092 }
1093 break;
1094 default:
1095 assert(0 && "Unreachable code");
1096 break;
1097 }
1098
1099 return false;
1100 }
1101
1102 ///////////////////////////////////////////////
1103 // //
1104 // Thumb2 instruction disassembly functions. //
1105 // //
1106 ///////////////////////////////////////////////
1107
1108 ///////////////////////////////////////////////////////////
1109 // //
1110 // Note: the register naming follows the ARM convention! //
1111 // //
1112 ///////////////////////////////////////////////////////////
1113
1114 static inline bool Thumb2SRSOpcode(unsigned Opcode) {
1115 switch (Opcode) {
1116 default:
1117 return false;
1118 case ARM::t2SRSDBW: case ARM::t2SRSDB:
1119 case ARM::t2SRSIAW: case ARM::t2SRSIA:
1120 return true;
1121 }
1122 }
1123
1124 static inline bool Thumb2RFEOpcode(unsigned Opcode) {
1125 switch (Opcode) {
1126 default:
1127 return false;
1128 case ARM::t2RFEDBW: case ARM::t2RFEDB:
1129 case ARM::t2RFEIAW: case ARM::t2RFEIA:
1130 return true;
1131 }
1132 }
1133
1134 // t2SRS[IA|DB]W/t2SRS[IA|DB]: mode_imm = Inst{4-0}
1135 static bool DisassembleThumb2SRS(MCInst &MI, unsigned Opcode, uint32_t insn,
1136 unsigned short NumOps, unsigned &NumOpsAdded) {
1137 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0)));
1138 NumOpsAdded = 1;
1139 return true;
1140 }
1141
1142 // t2RFE[IA|DB]W/t2RFE[IA|DB]: Rn
1143 static bool DisassembleThumb2RFE(MCInst &MI, unsigned Opcode, uint32_t insn,
1144 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1145 unsigned Rn = decodeRn(insn);
1146 if (Rn == 15) {
1147 DEBUG(errs() << "if n == 15 then UNPREDICTABLE\n");
1148 return false;
1149 }
1150 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B,ARM::GPRRegClassID,Rn)));
1151 NumOpsAdded = 1;
1152 return true;
1153 }
1154
1155 static bool DisassembleThumb2LdStMul(MCInst &MI, unsigned Opcode, uint32_t insn,
1156 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1157
1158 if (Thumb2SRSOpcode(Opcode))
1159 return DisassembleThumb2SRS(MI, Opcode, insn, NumOps, NumOpsAdded);
1160
1161 if (Thumb2RFEOpcode(Opcode))
1162 return DisassembleThumb2RFE(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1163
1164 assert((Opcode == ARM::t2LDMIA || Opcode == ARM::t2LDMIA_UPD ||
1165 Opcode == ARM::t2LDMDB || Opcode == ARM::t2LDMDB_UPD ||
1166 Opcode == ARM::t2STMIA || Opcode == ARM::t2STMIA_UPD ||
1167 Opcode == ARM::t2STMDB || Opcode == ARM::t2STMDB_UPD)
1168 && "Unexpected opcode");
1169 assert(NumOps >= 4 && "Thumb2 LdStMul expects NumOps >= 4");
1170
1171 NumOpsAdded = 0;
1172
1173 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1174
1175 // Writeback to base.
1176 if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD ||
1177 Opcode == ARM::t2STMIA_UPD || Opcode == ARM::t2STMDB_UPD) {
1178 MI.addOperand(MCOperand::CreateReg(Base));
1179 ++NumOpsAdded;
1180 }
1181
1182 MI.addOperand(MCOperand::CreateReg(Base));
1183 ++NumOpsAdded;
1184
1185 // Handling the two predicate operands before the reglist.
1186 if (B->DoPredicateOperands(MI, Opcode, insn, NumOps)) {
1187 NumOpsAdded += 2;
1188 } else {
1189 DEBUG(errs() << "Expected predicate operands not found.\n");
1190 return false;
1191 }
1192
1193 unsigned RegListBits = insn & ((1 << 16) - 1);
1194
1195 // Fill the variadic part of reglist.
1196 for (unsigned i = 0; i < 16; ++i)
1197 if ((RegListBits >> i) & 1) {
1198 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1199 i)));
1200 ++NumOpsAdded;
1201 }
1202
1203 return true;
1204 }
1205
1206 // t2LDREX: Rd Rn
1207 // t2LDREXD: Rd Rs Rn
1208 // t2LDREXB, t2LDREXH: Rd Rn
1209 // t2STREX: Rs Rd Rn
1210 // t2STREXD: Rm Rd Rs Rn
1211 // t2STREXB, t2STREXH: Rm Rd Rn
1212 static bool DisassembleThumb2LdStEx(MCInst &MI, unsigned Opcode, uint32_t insn,
1213 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1214
1215 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1216 if (!OpInfo) return false;
1217
1218 unsigned &OpIdx = NumOpsAdded;
1219
1220 OpIdx = 0;
1221
1222 assert(NumOps >= 2
1223 && OpInfo[0].RegClass > 0
1224 && OpInfo[1].RegClass > 0
1225 && "Expect >=2 operands and first two as reg operands");
1226
1227 bool isStore = (ARM::t2STREX <= Opcode && Opcode <= ARM::t2STREXH);
1228 bool isSW = (Opcode == ARM::t2LDREX || Opcode == ARM::t2STREX);
1229 bool isDW = (Opcode == ARM::t2LDREXD || Opcode == ARM::t2STREXD);
1230
1231 // Add the destination operand for store.
1232 if (isStore) {
1233 MI.addOperand(MCOperand::CreateReg(
1234 getRegisterEnum(B, OpInfo[OpIdx].RegClass,
1235 isSW ? decodeRs(insn) : decodeRm(insn))));
1236 ++OpIdx;
1237 }
1238
1239 // Source operand for store and destination operand for load.
1240 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
1241 decodeRd(insn))));
1242 ++OpIdx;
1243
1244 // Thumb2 doubleword complication: with an extra source/destination operand.
1245 if (isDW) {
1246 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B,OpInfo[OpIdx].RegClass,
1247 decodeRs(insn))));
1248 ++OpIdx;
1249 }
1250
1251 // Finally add the pointer operand.
1252 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
1253 decodeRn(insn))));
1254 ++OpIdx;
1255
1256 return true;
1257 }
1258
1259 // t2LDRDi8: Rd Rs Rn imm8s4 (offset mode)
1260 // t2LDRDpci: Rd Rs imm8s4 (Not decoded, prefer the generic t2LDRDi8 version)
1261 // t2STRDi8: Rd Rs Rn imm8s4 (offset mode)
1262 //
1263 // Ditto for t2LDRD_PRE, t2LDRD_POST, t2STRD_PRE, t2STRD_POST, which are for
1264 // disassembly only and do not have a tied_to writeback base register operand.
1265 static bool DisassembleThumb2LdStDual(MCInst &MI, unsigned Opcode,
1266 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1267
1268 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1269 if (!OpInfo) return false;
1270
1271 assert(NumOps >= 4
1272 && OpInfo[0].RegClass > 0
1273 && OpInfo[0].RegClass == OpInfo[1].RegClass
1274 && OpInfo[2].RegClass > 0
1275 && OpInfo[3].RegClass < 0
1276 && "Expect >= 4 operands and first 3 as reg operands");
1277
1278 // Thumnb allows for specifying Rt and Rt2, unlike ARM (which has Rt2==Rt+1).
1279 unsigned Rt = decodeRd(insn);
1280 unsigned Rt2 = decodeRs(insn);
1281 unsigned Rn = decodeRn(insn);
1282
1283 // Some sanity checking first.
1284
1285 // A8.6.67 LDRD (literal) has its W bit as (0).
1286 if (Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2LDRD_PRE || Opcode == ARM::t2LDRD_POST) {
1287 if (Rn == 15 && slice(insn, 21, 21) != 0)
1288 return false;
1289 } else {
1290 // For Dual Store, PC cannot be used as the base register.
1291 if (Rn == 15) {
1292 DEBUG(errs() << "if n == 15 then UNPREDICTABLE\n");
1293 return false;
1294 }
1295 }
1296 if (Rt == Rt2) {
1297 DEBUG(errs() << "if t == t2 then UNPREDICTABLE\n");
1298 return false;
1299 }
1300 if (Opcode != ARM::t2LDRDi8 && Opcode != ARM::t2STRDi8) {
1301 if (Rn == Rt || Rn == Rt2) {
1302 DEBUG(errs() << "if wback && (n == t || n == t2) then UNPREDICTABLE\n");
1303 return false;
1304 }
1305 }
1306
1307 // Add the <Rt> <Rt2> operands.
1308 unsigned RegClassPair = OpInfo[0].RegClass;
1309 unsigned RegClassBase = OpInfo[2].RegClass;
1310
1311 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassPair,
1312 decodeRd(insn))));
1313 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassPair,
1314 decodeRs(insn))));
1315 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassBase,
1316 decodeRn(insn))));
1317
1318 // Finally add (+/-)imm8*4, depending on the U bit.
1319 int Offset = getImm8(insn) * 4;
1320 if (getUBit(insn) == 0)
1321 Offset = -Offset;
1322 MI.addOperand(MCOperand::CreateImm(Offset));
1323 NumOpsAdded = 4;
1324
1325 return true;
1326 }
1327
1328 // t2TBB, t2TBH: Rn Rm Pred-Imm Pred-CCR
1329 static bool DisassembleThumb2TB(MCInst &MI, unsigned Opcode,
1330 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1331
1332 assert(NumOps >= 2 && "Expect >= 2 operands");
1333
1334 // The generic version of TBB/TBH needs a base register.
1335 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1336 decodeRn(insn))));
1337 // Add the index register.
1338 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1339 decodeRm(insn))));
1340 NumOpsAdded = 2;
1341
1342 return true;
1343 }
1344
1345 static inline bool Thumb2ShiftOpcode(unsigned Opcode) {
1346 switch (Opcode) {
1347 default:
1348 return false;
1349 case ARM::t2MOVCClsl: case ARM::t2MOVCClsr:
1350 case ARM::t2MOVCCasr: case ARM::t2MOVCCror:
1351 case ARM::t2LSLri: case ARM::t2LSRri:
1352 case ARM::t2ASRri: case ARM::t2RORri:
1353 return true;
1354 }
1355 }
1356
1357 // A6.3.11 Data-processing (shifted register)
1358 //
1359 // Two register operands (Rn=0b1111 no 1st operand reg): Rs Rm
1360 // Two register operands (Rs=0b1111 no dst operand reg): Rn Rm
1361 // Three register operands: Rs Rn Rm
1362 // Three register operands: (Rn=0b1111 Conditional Move) Rs Ro(TIED_TO) Rm
1363 //
1364 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1365 // register with shift forms: (Rm, ConstantShiftSpecifier).
1366 // Constant shift specifier: Imm = (ShOp | ShAmt<<3).
1367 //
1368 // There are special instructions, like t2MOVsra_flag and t2MOVsrl_flag, which
1369 // only require two register operands: Rd, Rm in ARM Reference Manual terms, and
1370 // nothing else, because the shift amount is already specified.
1371 // Similar case holds for t2MOVrx, t2ADDrr, ..., etc.
1372 static bool DisassembleThumb2DPSoReg(MCInst &MI, unsigned Opcode, uint32_t insn,
1373 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1374
1375 const TargetInstrDesc &TID = ARMInsts[Opcode];
1376 const TargetOperandInfo *OpInfo = TID.OpInfo;
1377 unsigned &OpIdx = NumOpsAdded;
1378
1379 // Special case handling.
1380 if (Opcode == ARM::t2BR_JT) {
1381 assert(NumOps == 4
1382 && OpInfo[0].RegClass == ARM::GPRRegClassID
1383 && OpInfo[1].RegClass == ARM::GPRRegClassID
1384 && OpInfo[2].RegClass < 0
1385 && OpInfo[3].RegClass < 0
1386 && "Exactly 4 operands expect and first two as reg operands");
1387 // Only need to populate the src reg operand.
1388 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1389 decodeRm(insn))));
1390 MI.addOperand(MCOperand::CreateReg(0));
1391 MI.addOperand(MCOperand::CreateImm(0));
1392 MI.addOperand(MCOperand::CreateImm(0));
1393 NumOpsAdded = 4;
1394 return true;
1395 }
1396
1397 OpIdx = 0;
1398
1399 assert(NumOps >= 2
1400 && (OpInfo[0].RegClass == ARM::GPRRegClassID ||
1401 OpInfo[0].RegClass == ARM::rGPRRegClassID)
1402 && (OpInfo[1].RegClass == ARM::GPRRegClassID ||
1403 OpInfo[1].RegClass == ARM::rGPRRegClassID)
1404 && "Expect >= 2 operands and first two as reg operands");
1405
1406 bool ThreeReg = (NumOps > 2 && (OpInfo[2].RegClass == ARM::GPRRegClassID ||
1407 OpInfo[2].RegClass == ARM::rGPRRegClassID));
1408 bool NoDstReg = (decodeRs(insn) == 0xF);
1409
1410 // Build the register operands, followed by the constant shift specifier.
1411
1412 MI.addOperand(MCOperand::CreateReg(
1413 getRegisterEnum(B, OpInfo[0].RegClass,
1414 NoDstReg ? decodeRn(insn) : decodeRs(insn))));
1415 ++OpIdx;
1416
1417 if (ThreeReg) {
1418 int Idx;
1419 if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
1420 // Process tied_to operand constraint.
1421 MI.addOperand(MI.getOperand(Idx));
1422 ++OpIdx;
1423 } else if (!NoDstReg) {
1424 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[1].RegClass,
1425 decodeRn(insn))));
1426 ++OpIdx;
1427 } else {
1428 DEBUG(errs() << "Thumb2 encoding error: d==15 for three-reg operands.\n");
1429 return false;
1430 }
1431 }
1432
1433 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
1434 decodeRm(insn))));
1435 ++OpIdx;
1436
1437 if (NumOps == OpIdx)
1438 return true;
1439
1440 if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate()
1441 && !OpInfo[OpIdx].isOptionalDef()) {
1442
1443 if (Thumb2ShiftOpcode(Opcode)) {
1444 unsigned Imm = getShiftAmtBits(insn);
1445 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 5, 4));
1446 getImmShiftSE(ShOp, Imm);
1447 MI.addOperand(MCOperand::CreateImm(Imm));
1448 } else {
1449 // Build the constant shift specifier operand.
1450 unsigned bits2 = getShiftTypeBits(insn);
1451 unsigned imm5 = getShiftAmtBits(insn);
1452 ARM_AM::ShiftOpc ShOp = ARM_AM::no_shift;
1453 unsigned ShAmt = decodeImmShift(bits2, imm5, ShOp);
1454 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShAmt)));
1455 }
1456 ++OpIdx;
1457 }
1458
1459 return true;
1460 }
1461
1462 // A6.3.1 Data-processing (modified immediate)
1463 //
1464 // Two register operands: Rs Rn ModImm
1465 // One register operands (Rs=0b1111 no explicit dest reg): Rn ModImm
1466 // One register operands (Rn=0b1111 no explicit src reg): Rs ModImm -
1467 // {t2MOVi, t2MVNi}
1468 //
1469 // ModImm = ThumbExpandImm(i:imm3:imm8)
1470 static bool DisassembleThumb2DPModImm(MCInst &MI, unsigned Opcode,
1471 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1472
1473 const TargetInstrDesc &TID = ARMInsts[Opcode];
1474 const TargetOperandInfo *OpInfo = TID.OpInfo;
1475 unsigned &OpIdx = NumOpsAdded;
1476
1477 OpIdx = 0;
1478
1479 unsigned RdRegClassID = OpInfo[0].RegClass;
1480 assert(NumOps >= 2 && (RdRegClassID == ARM::GPRRegClassID ||
1481 RdRegClassID == ARM::rGPRRegClassID)
1482 && "Expect >= 2 operands and first one as reg operand");
1483
1484 unsigned RnRegClassID = OpInfo[1].RegClass;
1485 bool TwoReg = (RnRegClassID == ARM::GPRRegClassID
1486 || RnRegClassID == ARM::rGPRRegClassID);
1487 bool NoDstReg = (decodeRs(insn) == 0xF);
1488
1489 // Build the register operands, followed by the modified immediate.
1490
1491 MI.addOperand(MCOperand::CreateReg(
1492 getRegisterEnum(B, RdRegClassID,
1493 NoDstReg ? decodeRn(insn) : decodeRs(insn))));
1494 ++OpIdx;
1495
1496 if (TwoReg) {
1497 if (NoDstReg) {
1498 DEBUG(errs()<<"Thumb2 encoding error: d==15 for DPModImm 2-reg instr.\n");
1499 return false;
1500 }
1501 int Idx;
1502 if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
1503 // The reg operand is tied to the first reg operand.
1504 MI.addOperand(MI.getOperand(Idx));
1505 } else {
1506 // Add second reg operand.
1507 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RnRegClassID,
1508 decodeRn(insn))));
1509 }
1510 ++OpIdx;
1511 }
1512
1513 // The modified immediate operand should come next.
1514 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 &&
1515 !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()
1516 && "Pure imm operand expected");
1517
1518 // i:imm3:imm8
1519 // A6.3.2 Modified immediate constants in Thumb instructions
1520 unsigned imm12 = getIImm3Imm8(insn);
1521 MI.addOperand(MCOperand::CreateImm(ThumbExpandImm(imm12)));
1522 ++OpIdx;
1523
1524 return true;
1525 }
1526
1527 static inline bool Thumb2SaturateOpcode(unsigned Opcode) {
1528 switch (Opcode) {
1529 case ARM::t2SSAT: case ARM::t2SSAT16:
1530 case ARM::t2USAT: case ARM::t2USAT16:
1531 return true;
1532 default:
1533 return false;
1534 }
1535 }
1536
1537 /// DisassembleThumb2Sat - Disassemble Thumb2 saturate instructions:
1538 /// o t2SSAT, t2USAT: Rs sat_pos Rn shamt
1539 /// o t2SSAT16, t2USAT16: Rs sat_pos Rn
1540 static bool DisassembleThumb2Sat(MCInst &MI, unsigned Opcode, uint32_t insn,
1541 unsigned &NumOpsAdded, BO B) {
1542 const TargetInstrDesc &TID = ARMInsts[Opcode];
1543 NumOpsAdded = TID.getNumOperands() - 2; // ignore predicate operands
1544
1545 // Disassemble the register def.
1546 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
1547 decodeRs(insn))));
1548
1549 unsigned Pos = slice(insn, 4, 0);
1550 if (Opcode == ARM::t2SSAT || Opcode == ARM::t2SSAT16)
1551 Pos += 1;
1552 MI.addOperand(MCOperand::CreateImm(Pos));
1553
1554 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
1555 decodeRn(insn))));
1556
1557 if (NumOpsAdded == 4) {
1558 ARM_AM::ShiftOpc Opc = (slice(insn, 21, 21) != 0 ?
1559 ARM_AM::asr : ARM_AM::lsl);
1560 // Inst{14-12:7-6} encodes the imm5 shift amount.
1561 unsigned ShAmt = slice(insn, 14, 12) << 2 | slice(insn, 7, 6);
1562 if (ShAmt == 0) {
1563 if (Opc == ARM_AM::asr)
1564 ShAmt = 32;
1565 else
1566 Opc = ARM_AM::no_shift;
1567 }
1568 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShAmt)));
1569 }
1570 return true;
1571 }
1572
1573 // A6.3.3 Data-processing (plain binary immediate)
1574 //
1575 // o t2ADDri12, t2SUBri12: Rs Rn imm12
1576 // o t2LEApcrel (ADR): Rs imm12
1577 // o t2BFC (BFC): Rs Ro(TIED_TO) bf_inv_mask_imm
1578 // o t2BFI (BFI) (Currently not defined in LLVM as of Jan-07-2010)
1579 // o t2MOVi16: Rs imm16
1580 // o t2MOVTi16: Rs imm16
1581 // o t2SBFX (SBFX): Rs Rn lsb width
1582 // o t2UBFX (UBFX): Rs Rn lsb width
1583 // o t2BFI (BFI): Rs Rn lsb width
1584 static bool DisassembleThumb2DPBinImm(MCInst &MI, unsigned Opcode,
1585 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1586
1587 const TargetInstrDesc &TID = ARMInsts[Opcode];
1588 const TargetOperandInfo *OpInfo = TID.OpInfo;
1589 unsigned &OpIdx = NumOpsAdded;
1590
1591 OpIdx = 0;
1592
1593 unsigned RdRegClassID = OpInfo[0].RegClass;
1594 assert(NumOps >= 2 && (RdRegClassID == ARM::GPRRegClassID ||
1595 RdRegClassID == ARM::rGPRRegClassID)
1596 && "Expect >= 2 operands and first one as reg operand");
1597
1598 unsigned RnRegClassID = OpInfo[1].RegClass;
1599 bool TwoReg = (RnRegClassID == ARM::GPRRegClassID
1600 || RnRegClassID == ARM::rGPRRegClassID);
1601
1602 // Build the register operand(s), followed by the immediate(s).
1603
1604 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RdRegClassID,
1605 decodeRs(insn))));
1606 ++OpIdx;
1607
1608 if (TwoReg) {
1609 assert(NumOps >= 3 && "Expect >= 3 operands");
1610 int Idx;
1611 if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
1612 // Process tied_to operand constraint.
1613 MI.addOperand(MI.getOperand(Idx));
1614 } else {
1615 // Add src reg operand.
1616 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RnRegClassID,
1617 decodeRn(insn))));
1618 }
1619 ++OpIdx;
1620 }
1621
1622 if (Opcode == ARM::t2BFI) {
1623 // Add val reg operand.
1624 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RnRegClassID,
1625 decodeRn(insn))));
1626 ++OpIdx;
1627 }
1628
1629 assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate()
1630 && !OpInfo[OpIdx].isOptionalDef()
1631 && "Pure imm operand expected");
1632
1633 // Pre-increment OpIdx.
1634 ++OpIdx;
1635
1636 if (Opcode == ARM::t2ADDri12 || Opcode == ARM::t2SUBri12
1637 || Opcode == ARM::t2LEApcrel)
1638 MI.addOperand(MCOperand::CreateImm(getIImm3Imm8(insn)));
1639 else if (Opcode == ARM::t2MOVi16 || Opcode == ARM::t2MOVTi16) {
1640 if (!B->tryAddingSymbolicOperand(getImm16(insn), 4, MI))
1641 MI.addOperand(MCOperand::CreateImm(getImm16(insn)));
1642 } else if (Opcode == ARM::t2BFC || Opcode == ARM::t2BFI) {
1643 uint32_t mask = 0;
1644 if (getBitfieldInvMask(insn, mask))
1645 MI.addOperand(MCOperand::CreateImm(mask));
1646 else
1647 return false;
1648 } else {
1649 // Handle the case of: lsb width
1650 assert((Opcode == ARM::t2SBFX || Opcode == ARM::t2UBFX)
1651 && "Unexpected opcode");
1652 MI.addOperand(MCOperand::CreateImm(getLsb(insn)));
1653 MI.addOperand(MCOperand::CreateImm(getWidthMinus1(insn) + 1));
1654
1655 ++OpIdx;
1656 }
1657
1658 return true;
1659 }
1660
1661 // A6.3.4 Table A6-15 Miscellaneous control instructions
1662 // A8.6.41 DMB
1663 // A8.6.42 DSB
1664 // A8.6.49 ISB
1665 static inline bool t2MiscCtrlInstr(uint32_t insn) {
1666 if (slice(insn, 31, 20) == 0xf3b && slice(insn, 15, 14) == 2 &&
1667 slice(insn, 12, 12) == 0)
1668 return true;
1669
1670 return false;
1671 }
1672
1673 // A6.3.4 Branches and miscellaneous control
1674 //
1675 // A8.6.16 B
1676 // Branches: t2B, t2Bcc -> imm operand
1677 //
1678 // Branches: t2TPsoft -> no operand
1679 //
1680 // A8.6.23 BL, BLX (immediate)
1681 // Branches (defined in ARMInstrThumb.td): tBLr9, tBLXi_r9 -> imm operand
1682 //
1683 // A8.6.26
1684 // t2BXJ -> Rn
1685 //
1686 // Miscellaneous control:
1687 // -> no operand (except pred-imm pred-ccr for CLREX, memory barrier variants)
1688 //
1689 // Hint: t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV
1690 // -> no operand (except pred-imm pred-ccr)
1691 //
1692 // t2DBG -> imm4 = Inst{3-0}
1693 //
1694 // t2MRS/t2MRSsys -> Rs
1695 // t2MSR/t2MSRsys -> Rn mask=Inst{11-8}
1696 // t2SMC -> imm4 = Inst{19-16}
1697 static bool DisassembleThumb2BrMiscCtrl(MCInst &MI, unsigned Opcode,
1698 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1699
1700 if (NumOps == 0)
1701 return true;
1702
1703 if (Opcode == ARM::t2DMB || Opcode == ARM::t2DSB) {
1704 // Inst{3-0} encodes the memory barrier option for the variants.
1705 unsigned opt = slice(insn, 3, 0);
1706 switch (opt) {
1707 case ARM_MB::SY: case ARM_MB::ST:
1708 case ARM_MB::ISH: case ARM_MB::ISHST:
1709 case ARM_MB::NSH: case ARM_MB::NSHST:
1710 case ARM_MB::OSH: case ARM_MB::OSHST:
1711 MI.addOperand(MCOperand::CreateImm(opt));
1712 NumOpsAdded = 1;
1713 return true;
1714 default:
1715 return false;
1716 }
1717 }
1718
1719 if (t2MiscCtrlInstr(insn))
1720 return true;
1721
1722 switch (Opcode) {
1723 case ARM::t2CLREX:
1724 case ARM::t2NOP:
1725 case ARM::t2YIELD:
1726 case ARM::t2WFE:
1727 case ARM::t2WFI:
1728 case ARM::t2SEV:
1729 return true;
1730 default:
1731 break;
1732 }
1733
1734 // FIXME: To enable correct asm parsing and disasm of CPS we need 3 different
1735 // opcodes which match the same real instruction. This is needed since there's
1736 // no current handling of optional arguments. Fix here when a better handling
1737 // of optional arguments is implemented.
1738 if (Opcode == ARM::t2CPS3p) {
1739 MI.addOperand(MCOperand::CreateImm(slice(insn, 10, 9))); // imod
1740 MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 5))); // iflags
1741 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0))); // mode
1742 NumOpsAdded = 3;
1743 return true;
1744 }
1745 if (Opcode == ARM::t2CPS2p) {
1746 MI.addOperand(MCOperand::CreateImm(slice(insn, 10, 9))); // imod
1747 MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 5))); // iflags
1748 NumOpsAdded = 2;
1749 return true;
1750 }
1751 if (Opcode == ARM::t2CPS1p) {
1752 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0))); // mode
1753 NumOpsAdded = 1;
1754 return true;
1755 }
1756
1757 // DBG has its option specified in Inst{3-0}.
1758 if (Opcode == ARM::t2DBG) {
1759 MI.addOperand(MCOperand::CreateImm(slice(insn, 3, 0)));
1760 NumOpsAdded = 1;
1761 return true;
1762 }
1763
1764 // MRS and MRSsys take one GPR reg Rs.
1765 if (Opcode == ARM::t2MRS || Opcode == ARM::t2MRSsys) {
1766 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1767 decodeRs(insn))));
1768 NumOpsAdded = 1;
1769 return true;
1770 }
1771 // BXJ takes one GPR reg Rn.
1772 if (Opcode == ARM::t2BXJ) {
1773 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1774 decodeRn(insn))));
1775 NumOpsAdded = 1;
1776 return true;
1777 }
1778 // MSR take a mask, followed by one GPR reg Rn. The mask contains the R Bit in
1779 // bit 4, and the special register fields in bits 3-0.
1780 if (Opcode == ARM::t2MSR) {
1781 MI.addOperand(MCOperand::CreateImm(slice(insn, 20, 20) << 4 /* R Bit */ |
1782 slice(insn, 11, 8) /* Special Reg */));
1783 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1784 decodeRn(insn))));
1785 NumOpsAdded = 2;
1786 return true;
1787 }
1788 // SMC take imm4.
1789 if (Opcode == ARM::t2SMC) {
1790 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 16)));
1791 NumOpsAdded = 1;
1792 return true;
1793 }
1794
1795 // Some instructions have predicate operands first before the immediate.
1796 if (Opcode == ARM::tBLXi_r9 || Opcode == ARM::tBLr9) {
1797 // Handling the two predicate operands before the imm operand.
1798 if (B->DoPredicateOperands(MI, Opcode, insn, NumOps))
1799 NumOpsAdded += 2;
1800 else {
1801 DEBUG(errs() << "Expected predicate operands not found.\n");
1802 return false;
1803 }
1804 }
1805
1806 // Add the imm operand.
1807 int Offset = 0;
1808
1809 switch (Opcode) {
1810 default:
1811 assert(0 && "Unexpected opcode");
1812 return false;
1813 case ARM::t2B:
1814 Offset = decodeImm32_B_EncodingT4(insn);
1815 break;
1816 case ARM::t2Bcc:
1817 Offset = decodeImm32_B_EncodingT3(insn);
1818 break;
1819 case ARM::tBLr9:
1820 Offset = decodeImm32_BL(insn);
1821 break;
1822 case ARM::tBLXi_r9:
1823 Offset = decodeImm32_BLX(insn);
1824 break;
1825 }
1826
1827 if (!B->tryAddingSymbolicOperand(Offset + B->getBuilderAddress() + 4, 4, MI))
1828 MI.addOperand(MCOperand::CreateImm(Offset));
1829
1830 // This is an increment as some predicate operands may have been added first.
1831 NumOpsAdded += 1;
1832
1833 return true;
1834 }
1835
1836 static inline bool Thumb2PreloadOpcode(unsigned Opcode) {
1837 switch (Opcode) {
1838 default:
1839 return false;
1840 case ARM::t2PLDi12: case ARM::t2PLDi8:
1841 case ARM::t2PLDs:
1842 case ARM::t2PLDWi12: case ARM::t2PLDWi8:
1843 case ARM::t2PLDWs:
1844 case ARM::t2PLIi12: case ARM::t2PLIi8:
1845 case ARM::t2PLIs:
1846 return true;
1847 }
1848 }
1849
1850 static bool DisassembleThumb2PreLoad(MCInst &MI, unsigned Opcode, uint32_t insn,
1851 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1852
1853 // Preload Data/Instruction requires either 2 or 3 operands.
1854 // t2PLDi12, t2PLDi8, t2PLDpci: Rn [+/-]imm12/imm8
1855 // t2PLDr: Rn Rm
1856 // t2PLDs: Rn Rm imm2=Inst{5-4}
1857 // Same pattern applies for t2PLDW* and t2PLI*.
1858
1859 const TargetInstrDesc &TID = ARMInsts[Opcode];
1860 const TargetOperandInfo *OpInfo = TID.OpInfo;
1861 unsigned &OpIdx = NumOpsAdded;
1862
1863 OpIdx = 0;
1864
1865 assert(NumOps >= 2 &&
1866 OpInfo[0].RegClass == ARM::GPRRegClassID &&
1867 "Expect >= 2 operands and first one as reg operand");
1868
1869 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1870 decodeRn(insn))));
1871 ++OpIdx;
1872
1873 if (OpInfo[OpIdx].RegClass == ARM::rGPRRegClassID) {
1874 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1875 decodeRm(insn))));
1876 } else {
1877 assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate()
1878 && !OpInfo[OpIdx].isOptionalDef()
1879 && "Pure imm operand expected");
1880 int Offset = 0;
1881 if (Opcode == ARM::t2PLDi8 || Opcode == ARM::t2PLDWi8 ||
1882 Opcode == ARM::t2PLIi8) {
1883 // A8.6.117 Encoding T2: add = FALSE
1884 unsigned Imm8 = getImm8(insn);
1885 Offset = -1 * Imm8;
1886 } else {
1887 // The i12 forms. See, for example, A8.6.117 Encoding T1.
1888 // Note that currently t2PLDi12 also handles the previously named t2PLDpci
1889 // opcode, that's why we use decodeImm12(insn) which returns +/- imm12.
1890 Offset = decodeImm12(insn);
1891 }
1892 MI.addOperand(MCOperand::CreateImm(Offset));
1893 }
1894 ++OpIdx;
1895
1896 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 &&
1897 !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1898 // Fills in the shift amount for t2PLDs, t2PLDWs, t2PLIs.
1899 MI.addOperand(MCOperand::CreateImm(slice(insn, 5, 4)));
1900 ++OpIdx;
1901 }
1902
1903 return true;
1904 }
1905
1906 static bool BadRegsThumb2LdSt(unsigned Opcode, uint32_t insn, bool Load,
1907 unsigned R0, unsigned R1, unsigned R2, bool UseRm, bool WB) {
1908
1909 // Inst{22-21} encodes the data item transferred for load/store.
1910 // For single word, it is encoded as ob10.
1911 bool Word = (slice(insn, 22, 21) == 2);
1912
1913 if (UseRm && BadReg(R2)) {
1914 DEBUG(errs() << "if BadReg(m) then UNPREDICTABLE\n");
1915 return true;
1916 }
1917
1918 if (Load) {
1919 if (!Word && R0 == 13) {
1920 DEBUG(errs() << "if t == 13 then UNPREDICTABLE\n");
1921 return true;
1922 }
1923 } else {
1924 if (WB && R0 == R1) {
1925 DEBUG(errs() << "if wback && n == t then UNPREDICTABLE\n");
1926 return true;
1927 }
1928 if ((WB && R0 == 15) || (!WB && R1 == 15)) {
1929 DEBUG(errs() << "if Rn == '1111' then UNDEFINED\n");
1930 return true;
1931 }
1932 if (Word) {
1933 if ((WB && R1 == 15) || (!WB && R0 == 15)) {
1934 DEBUG(errs() << "if t == 15 then UNPREDICTABLE\n");
1935 return true;
1936 }
1937 } else {
1938 if ((WB && BadReg(R1)) || (!WB && BadReg(R0))) {
1939 DEBUG(errs() << "if BadReg(t) then UNPREDICTABLE\n");
1940 return true;
1941 }
1942 }
1943 }
1944 return false;
1945 }
1946
1947 // A6.3.10 Store single data item
1948 // A6.3.9 Load byte, memory hints
1949 // A6.3.8 Load halfword, memory hints
1950 // A6.3.7 Load word
1951 //
1952 // For example,
1953 //
1954 // t2LDRi12: Rd Rn (+)imm12
1955 // t2LDRi8: Rd Rn (+/-)imm8 (+ if Inst{9} == 0b1)
1956 // t2LDRs: Rd Rn Rm ConstantShiftSpecifier (see also
1957 // DisassembleThumb2DPSoReg)
1958 // t2LDR_POST: Rd Rn Rn(TIED_TO) (+/-)imm8 (+ if Inst{9} == 0b1)
1959 // t2LDR_PRE: Rd Rn Rn(TIED_TO) (+/-)imm8 (+ if Inst{9} == 0b1)
1960 //
1961 // t2STRi12: Rd Rn (+)imm12
1962 // t2STRi8: Rd Rn (+/-)imm8 (+ if Inst{9} == 0b1)
1963 // t2STRs: Rd Rn Rm ConstantShiftSpecifier (see also
1964 // DisassembleThumb2DPSoReg)
1965 // t2STR_POST: Rn Rd Rn(TIED_TO) (+/-)imm8 (+ if Inst{9} == 0b1)
1966 // t2STR_PRE: Rn Rd Rn(TIED_TO) (+/-)imm8 (+ if Inst{9} == 0b1)
1967 //
1968 // Note that for indexed modes, the Rn(TIED_TO) operand needs to be populated
1969 // correctly, as LLVM AsmPrinter depends on it. For indexed stores, the first
1970 // operand is Rn; for all the other instructions, Rd is the first operand.
1971 //
1972 // Delegates to DisassembleThumb2PreLoad() for preload data/instruction.
1973 // Delegates to DisassembleThumb2Ldpci() for load * literal operations.
1974 static bool DisassembleThumb2LdSt(bool Load, MCInst &MI, unsigned Opcode,
1975 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1976
1977 unsigned Rn = decodeRn(insn);
1978
1979 if (Thumb2PreloadOpcode(Opcode))
1980 return DisassembleThumb2PreLoad(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1981
1982 // See, for example, A6.3.7 Load word: Table A6-18 Load word.
1983 if (Load && Rn == 15)
1984 return DisassembleThumb2Ldpci(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1985 const TargetInstrDesc &TID = ARMInsts[Opcode];
1986 const TargetOperandInfo *OpInfo = TID.OpInfo;
1987 unsigned &OpIdx = NumOpsAdded;
1988
1989 OpIdx = 0;
1990
1991 assert(NumOps >= 3 &&
1992 OpInfo[0].RegClass == ARM::GPRRegClassID &&
1993 OpInfo[1].RegClass == ARM::GPRRegClassID &&
1994 "Expect >= 3 operands and first two as reg operands");
1995
1996 bool ThreeReg = (OpInfo[2].RegClass > 0);
1997 bool TIED_TO = ThreeReg && TID.getOperandConstraint(2, TOI::TIED_TO) != -1;
1998 bool Imm12 = !ThreeReg && slice(insn, 23, 23) == 1; // ARMInstrThumb2.td
1999
2000 // Build the register operands, followed by the immediate.
2001 unsigned R0, R1, R2 = 0;
2002 unsigned Rd = decodeRd(insn);
2003 int Imm = 0;
2004
2005 if (!Load && TIED_TO) {
2006 R0 = Rn;
2007 R1 = Rd;
2008 } else {
2009 R0 = Rd;
2010 R1 = Rn;
2011 }
2012 if (ThreeReg) {
2013 if (TIED_TO) {
2014 R2 = Rn;
2015 Imm = decodeImm8(insn);
2016 } else {
2017 R2 = decodeRm(insn);
2018 // See, for example, A8.6.64 LDRB (register).
2019 // And ARMAsmPrinter::printT2AddrModeSoRegOperand().
2020 // LSL is the default shift opc, and LLVM does not expect it to be encoded
2021 // as part of the immediate operand.
2022 // Imm = ARM_AM::getSORegOpc(ARM_AM::lsl, slice(insn, 5, 4));
2023 Imm = slice(insn, 5, 4);
2024 }
2025 } else {
2026 if (Imm12)
2027 Imm = getImm12(insn);
2028 else
2029 Imm = decodeImm8(insn);
2030 }
2031
2032 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2033 R0)));
2034 ++OpIdx;
2035 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2036 R1)));
2037 ++OpIdx;
2038
2039 if (ThreeReg) {
2040 // This could be an offset register or a TIED_TO register.
2041 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B,OpInfo[OpIdx].RegClass,
2042 R2)));
2043 ++OpIdx;
2044 }
2045
2046 if (BadRegsThumb2LdSt(Opcode, insn, Load, R0, R1, R2, ThreeReg & !TIED_TO,
2047 TIED_TO))
2048 return false;
2049
2050 assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate()
2051 && !OpInfo[OpIdx].isOptionalDef()
2052 && "Pure imm operand expected");
2053
2054 MI.addOperand(MCOperand::CreateImm(Imm));
2055 ++OpIdx;
2056
2057 return true;
2058 }
2059
2060 // A6.3.12 Data-processing (register)
2061 //
2062 // Two register operands [rotate]: Rs Rm [rotation(= (rotate:'000'))]
2063 // Three register operands only: Rs Rn Rm
2064 // Three register operands [rotate]: Rs Rn Rm [rotation(= (rotate:'000'))]
2065 //
2066 // Parallel addition and subtraction 32-bit Thumb instructions: Rs Rn Rm
2067 //
2068 // Miscellaneous operations: Rs [Rn] Rm
2069 static bool DisassembleThumb2DPReg(MCInst &MI, unsigned Opcode, uint32_t insn,
2070 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2071
2072 const TargetInstrDesc &TID = ARMInsts[Opcode];
2073 const TargetOperandInfo *OpInfo = TID.OpInfo;
2074 unsigned &OpIdx = NumOpsAdded;
2075
2076 OpIdx = 0;
2077
2078 assert(NumOps >= 2 &&
2079 OpInfo[0].RegClass > 0 &&
2080 OpInfo[1].RegClass > 0 &&
2081 "Expect >= 2 operands and first two as reg operands");
2082
2083 // Build the register operands, followed by the optional rotation amount.
2084
2085 bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass > 0;
2086
2087 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2088 decodeRs(insn))));
2089 ++OpIdx;
2090
2091 if (ThreeReg) {
2092 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B,OpInfo[OpIdx].RegClass,
2093 decodeRn(insn))));
2094 ++OpIdx;
2095 }
2096
2097 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2098 decodeRm(insn))));
2099 ++OpIdx;
2100
2101 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2102 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2103 // Add the rotation amount immediate.
2104 MI.addOperand(MCOperand::CreateImm(decodeRotate(insn)));
2105 ++OpIdx;
2106 }
2107
2108 return true;
2109 }
2110
2111 // A6.3.16 Multiply, multiply accumulate, and absolute difference
2112 //
2113 // t2MLA, t2MLS, t2SMMLA, t2SMMLS: Rs Rn Rm Ra=Inst{15-12}
2114 // t2MUL, t2SMMUL: Rs Rn Rm
2115 // t2SMLA[BB|BT|TB|TT|WB|WT]: Rs Rn Rm Ra=Inst{15-12}
2116 // t2SMUL[BB|BT|TB|TT|WB|WT]: Rs Rn Rm
2117 //
2118 // Dual halfword multiply: t2SMUAD[X], t2SMUSD[X], t2SMLAD[X], t2SMLSD[X]:
2119 // Rs Rn Rm Ra=Inst{15-12}
2120 //
2121 // Unsigned Sum of Absolute Differences [and Accumulate]
2122 // Rs Rn Rm [Ra=Inst{15-12}]
2123 static bool DisassembleThumb2Mul(MCInst &MI, unsigned Opcode, uint32_t insn,
2124 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2125
2126 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
2127
2128 assert(NumOps >= 3 &&
2129 OpInfo[0].RegClass == ARM::rGPRRegClassID &&
2130 OpInfo[1].RegClass == ARM::rGPRRegClassID &&
2131 OpInfo[2].RegClass == ARM::rGPRRegClassID &&
2132 "Expect >= 3 operands and first three as reg operands");
2133
2134 // Build the register operands.
2135
2136 bool FourReg = NumOps > 3 && OpInfo[3].RegClass == ARM::rGPRRegClassID;
2137
2138 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
2139 decodeRs(insn))));
2140
2141 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
2142 decodeRn(insn))));
2143
2144 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
2145 decodeRm(insn))));
2146
2147 if (FourReg)
2148 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
2149 decodeRd(insn))));
2150
2151 NumOpsAdded = FourReg ? 4 : 3;
2152
2153 return true;
2154 }
2155
2156 // A6.3.17 Long multiply, long multiply accumulate, and divide
2157 //
2158 // t2SMULL, t2UMULL, t2SMLAL, t2UMLAL, t2UMAAL: RdLo RdHi Rn Rm
2159 // where RdLo = Inst{15-12} and RdHi = Inst{11-8}
2160 //
2161 // Halfword multiple accumulate long: t2SMLAL<x><y>: RdLo RdHi Rn Rm
2162 // where RdLo = Inst{15-12} and RdHi = Inst{11-8}
2163 //
2164 // Dual halfword multiple: t2SMLALD[X], t2SMLSLD[X]: RdLo RdHi Rn Rm
2165 // where RdLo = Inst{15-12} and RdHi = Inst{11-8}
2166 //
2167 // Signed/Unsigned divide: t2SDIV, t2UDIV: Rs Rn Rm
2168 static bool DisassembleThumb2LongMul(MCInst &MI, unsigned Opcode, uint32_t insn,
2169 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2170
2171 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
2172
2173 assert(NumOps >= 3 &&
2174 OpInfo[0].RegClass == ARM::rGPRRegClassID &&
2175 OpInfo[1].RegClass == ARM::rGPRRegClassID &&
2176 OpInfo[2].RegClass == ARM::rGPRRegClassID &&
2177 "Expect >= 3 operands and first three as reg operands");
2178
2179 bool FourReg = NumOps > 3 && OpInfo[3].RegClass == ARM::rGPRRegClassID;
2180
2181 // Build the register operands.
2182
2183 if (FourReg)
2184 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
2185 decodeRd(insn))));
2186
2187 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
2188 decodeRs(insn))));
2189
2190 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
2191 decodeRn(insn))));
2192
2193 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
2194 decodeRm(insn))));
2195
2196 if (FourReg)
2197 NumOpsAdded = 4;
2198 else
2199 NumOpsAdded = 3;
2200
2201 return true;
2202 }
2203
2204 // See A6.3 32-bit Thumb instruction encoding for instruction classes
2205 // corresponding to (op1, op2, op).
2206 //
2207 // Table A6-9 32-bit Thumb instruction encoding
2208 // op1 op2 op Instruction class, see
2209 // --- ------- -- -----------------------------------------------------------
2210 // 01 00xx0xx - Load/store multiple on page A6-23
2211 // 00xx1xx - Load/store dual, load/store exclusive, table branch on
2212 // page A6-24
2213 // 01xxxxx - Data-processing (shifted register) on page A6-31
2214 // 1xxxxxx - Coprocessor instructions on page A6-40
2215 // 10 x0xxxxx 0 Data-processing (modified immediate) on page A6-15
2216 // x1xxxxx 0 Data-processing (plain binary immediate) on page A6-19
2217 // - 1 Branches and miscellaneous control on page A6-20
2218 // 11 000xxx0 - Store single data item on page A6-30
2219 // 001xxx0 - Advanced SIMD element or structure load/store instructions
2220 // on page A7-27
2221 // 00xx001 - Load byte, memory hints on page A6-28
2222 // 00xx011 - Load halfword, memory hints on page A6-26
2223 // 00xx101 - Load word on page A6-25
2224 // 00xx111 - UNDEFINED
2225 // 010xxxx - Data-processing (register) on page A6-33
2226 // 0110xxx - Multiply, multiply accumulate, and absolute difference on
2227 // page A6-38
2228 // 0111xxx - Long multiply, long multiply accumulate, and divide on
2229 // page A6-39
2230 // 1xxxxxx - Coprocessor instructions on page A6-40
2231 //
2232 static bool DisassembleThumb2(uint16_t op1, uint16_t op2, uint16_t op,
2233 MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps,
2234 unsigned &NumOpsAdded, BO B) {
2235
2236 switch (op1) {
2237 case 1:
2238 if (slice(op2, 6, 5) == 0) {
2239 if (slice(op2, 2, 2) == 0) {
2240 // Load/store multiple.
2241 return DisassembleThumb2LdStMul(MI, Opcode, insn, NumOps, NumOpsAdded,
2242 B);
2243 }
2244
2245 // Load/store dual, load/store exclusive, table branch, otherwise.
2246 assert(slice(op2, 2, 2) == 1 && "Thumb2 encoding error!");
2247 if ((ARM::t2LDREX <= Opcode && Opcode <= ARM::t2LDREXH) ||
2248 (ARM::t2STREX <= Opcode && Opcode <= ARM::t2STREXH)) {
2249 // Load/store exclusive.
2250 return DisassembleThumb2LdStEx(MI, Opcode, insn, NumOps, NumOpsAdded,
2251 B);
2252 }
2253 if (Opcode == ARM::t2LDRDi8 ||
2254 Opcode == ARM::t2LDRD_PRE || Opcode == ARM::t2LDRD_POST ||
2255 Opcode == ARM::t2STRDi8 ||
2256 Opcode == ARM::t2STRD_PRE || Opcode == ARM::t2STRD_POST) {
2257 // Load/store dual.
2258 return DisassembleThumb2LdStDual(MI, Opcode, insn, NumOps, NumOpsAdded,
2259 B);
2260 }
2261 if (Opcode == ARM::t2TBB || Opcode == ARM::t2TBH) {
2262 // Table branch.
2263 return DisassembleThumb2TB(MI, Opcode, insn, NumOps, NumOpsAdded, B);
2264 }
2265 } else if (slice(op2, 6, 5) == 1) {
2266 // Data-processing (shifted register).
2267 return DisassembleThumb2DPSoReg(MI, Opcode, insn, NumOps, NumOpsAdded, B);
2268 }
2269
2270 // FIXME: A6.3.18 Coprocessor instructions
2271 // But see ThumbDisassembler::getInstruction().
2272
2273 break;
2274 case 2:
2275 if (op == 0) {
2276 if (slice(op2, 5, 5) == 0)
2277 // Data-processing (modified immediate)
2278 return DisassembleThumb2DPModImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2279 B);
2280 if (Thumb2SaturateOpcode(Opcode))
2281 return DisassembleThumb2Sat(MI, Opcode, insn, NumOpsAdded, B);
2282
2283 // Data-processing (plain binary immediate)
2284 return DisassembleThumb2DPBinImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2285 B);
2286 }
2287 // Branches and miscellaneous control on page A6-20.
2288 return DisassembleThumb2BrMiscCtrl(MI, Opcode, insn, NumOps, NumOpsAdded,
2289 B);
2290 case 3:
2291 switch (slice(op2, 6, 5)) {
2292 case 0:
2293 // Load/store instructions...
2294 if (slice(op2, 0, 0) == 0) {
2295 if (slice(op2, 4, 4) == 0) {
2296 // Store single data item on page A6-30
2297 return DisassembleThumb2LdSt(false, MI,Opcode,insn,NumOps,NumOpsAdded,
2298 B);
2299 } else {
2300 // FIXME: Advanced SIMD element or structure load/store instructions.
2301 // But see ThumbDisassembler::getInstruction().
2302 ;
2303 }
2304 } else {
2305 // Table A6-9 32-bit Thumb instruction encoding: Load byte|halfword|word
2306 return DisassembleThumb2LdSt(true, MI, Opcode, insn, NumOps,
2307 NumOpsAdded, B);
2308 }
2309 break;
2310 case 1:
2311 if (slice(op2, 4, 4) == 0) {
2312 // A6.3.12 Data-processing (register)
2313 return DisassembleThumb2DPReg(MI, Opcode, insn, NumOps, NumOpsAdded, B);
2314 } else if (slice(op2, 3, 3) == 0) {
2315 // A6.3.16 Multiply, multiply accumulate, and absolute difference
2316 return DisassembleThumb2Mul(MI, Opcode, insn, NumOps, NumOpsAdded, B);
2317 } else {
2318 // A6.3.17 Long multiply, long multiply accumulate, and divide
2319 return DisassembleThumb2LongMul(MI, Opcode, insn, NumOps, NumOpsAdded,
2320 B);
2321 }
2322 break;
2323 default:
2324 // FIXME: A6.3.18 Coprocessor instructions
2325 // But see ThumbDisassembler::getInstruction().
2326 ;
2327 break;
2328 }
2329
2330 break;
2331 default:
2332 assert(0 && "Thumb2 encoding error!");
2333 break;
2334 }
2335
2336 return false;
2337 }
2338
2339 static bool DisassembleThumbFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2340 unsigned short NumOps, unsigned &NumOpsAdded, BO Builder) {
2341
2342 uint16_t HalfWord = slice(insn, 31, 16);
2343
2344 if (HalfWord == 0) {
2345 // A6.2 16-bit Thumb instruction encoding
2346 // op = bits[15:10]
2347 uint16_t op = slice(insn, 15, 10);
2348 return DisassembleThumb1(op, MI, Opcode, insn, NumOps, NumOpsAdded,
2349 Builder);
2350 }
2351
2352 unsigned bits15_11 = slice(HalfWord, 15, 11);
2353
2354 // A6.1 Thumb instruction set encoding
2355 if (!(bits15_11 == 0x1D || bits15_11 == 0x1E || bits15_11 == 0x1F)) {
2356 assert("Bits[15:11] first halfword of Thumb2 instruction is out of range");
2357 return false;
2358 }
2359
2360 // A6.3 32-bit Thumb instruction encoding
2361
2362 uint16_t op1 = slice(HalfWord, 12, 11);
2363 uint16_t op2 = slice(HalfWord, 10, 4);
2364 uint16_t op = slice(insn, 15, 15);
2365
2366 return DisassembleThumb2(op1, op2, op, MI, Opcode, insn, NumOps, NumOpsAdded,
2367 Builder);
2368 }
STM8 backend for LLVM