1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE scalar FP Instructions
19 //===----------------------------------------------------------------------===//
21 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
22 // instruction selection into a branch sequence.
23 let Uses = [EFLAGS], usesCustomInserter = 1 in {
24 def CMOV_FR32 : I<0, Pseudo,
25 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
27 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
29 def CMOV_FR64 : I<0, Pseudo,
30 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
32 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
34 def CMOV_V4F32 : I<0, Pseudo,
35 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
36 "#CMOV_V4F32 PSEUDO!",
38 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
40 def CMOV_V2F64 : I<0, Pseudo,
41 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
42 "#CMOV_V2F64 PSEUDO!",
44 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
46 def CMOV_V2I64 : I<0, Pseudo,
47 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
48 "#CMOV_V2I64 PSEUDO!",
50 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
54 //===----------------------------------------------------------------------===//
55 // SSE 1 & 2 Instructions Classes
56 //===----------------------------------------------------------------------===//
58 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
59 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
60 RegisterClass RC, X86MemOperand x86memop,
62 let isCommutable = 1 in {
63 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
65 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
66 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
67 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
69 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
71 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
72 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
73 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
76 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
77 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
78 string asm, string SSEVer, string FPSizeStr,
79 Operand memopr, ComplexPattern mem_cpat,
81 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
83 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
84 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
85 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
86 !strconcat(SSEVer, !strconcat("_",
87 !strconcat(OpcodeStr, FPSizeStr))))
88 RC:$src1, RC:$src2))]>;
89 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
91 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
92 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
93 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
94 !strconcat(SSEVer, !strconcat("_",
95 !strconcat(OpcodeStr, FPSizeStr))))
96 RC:$src1, mem_cpat:$src2))]>;
99 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
100 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
101 RegisterClass RC, ValueType vt,
102 X86MemOperand x86memop, PatFrag mem_frag,
103 Domain d, bit Is2Addr = 1> {
104 let isCommutable = 1 in
105 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
107 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
108 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
109 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
111 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
113 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
114 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
115 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
118 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
119 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
120 string OpcodeStr, X86MemOperand x86memop,
121 list<dag> pat_rr, list<dag> pat_rm,
123 let isCommutable = 1 in
124 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
126 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
127 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
129 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
131 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
132 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
136 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
137 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
138 string asm, string SSEVer, string FPSizeStr,
139 X86MemOperand x86memop, PatFrag mem_frag,
140 Domain d, bit Is2Addr = 1> {
141 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
143 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
144 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
145 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
146 !strconcat(SSEVer, !strconcat("_",
147 !strconcat(OpcodeStr, FPSizeStr))))
148 RC:$src1, RC:$src2))], d>;
149 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
151 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
152 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
153 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
154 !strconcat(SSEVer, !strconcat("_",
155 !strconcat(OpcodeStr, FPSizeStr))))
156 RC:$src1, (mem_frag addr:$src2)))], d>;
159 //===----------------------------------------------------------------------===//
160 // SSE 1 & 2 - Move Instructions
161 //===----------------------------------------------------------------------===//
163 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
164 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
165 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
167 // Loading from memory automatically zeroing upper bits.
168 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
169 PatFrag mem_pat, string OpcodeStr> :
170 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
171 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
172 [(set RC:$dst, (mem_pat addr:$src))]>;
174 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
175 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
176 // is used instead. Register-to-register movss/movsd is not modeled as an
177 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
178 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
179 let isAsmParserOnly = 1 in {
180 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
181 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
182 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
183 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
185 let canFoldAsLoad = 1, isReMaterializable = 1 in {
186 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
188 let AddedComplexity = 20 in
189 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
193 let Constraints = "$src1 = $dst" in {
194 def MOVSSrr : sse12_move_rr<FR32, v4f32,
195 "movss\t{$src2, $dst|$dst, $src2}">, XS;
196 def MOVSDrr : sse12_move_rr<FR64, v2f64,
197 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
200 let canFoldAsLoad = 1, isReMaterializable = 1 in {
201 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
203 let AddedComplexity = 20 in
204 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
207 let AddedComplexity = 15 in {
208 // Extract the low 32-bit value from one vector and insert it into another.
209 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
210 (MOVSSrr (v4f32 VR128:$src1),
211 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
212 // Extract the low 64-bit value from one vector and insert it into another.
213 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
214 (MOVSDrr (v2f64 VR128:$src1),
215 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
218 // Implicitly promote a 32-bit scalar to a vector.
219 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
220 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
221 // Implicitly promote a 64-bit scalar to a vector.
222 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
223 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
225 let AddedComplexity = 20 in {
226 // MOVSSrm zeros the high parts of the register; represent this
227 // with SUBREG_TO_REG.
228 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
229 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
230 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
231 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
232 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
233 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
234 // MOVSDrm zeros the high parts of the register; represent this
235 // with SUBREG_TO_REG.
236 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
237 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
238 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
239 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
240 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
241 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
242 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
243 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
244 def : Pat<(v2f64 (X86vzload addr:$src)),
245 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
248 // Store scalar value to memory.
249 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
250 "movss\t{$src, $dst|$dst, $src}",
251 [(store FR32:$src, addr:$dst)]>;
252 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
253 "movsd\t{$src, $dst|$dst, $src}",
254 [(store FR64:$src, addr:$dst)]>;
256 let isAsmParserOnly = 1 in {
257 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
258 "movss\t{$src, $dst|$dst, $src}",
259 [(store FR32:$src, addr:$dst)]>, XS, VEX;
260 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
261 "movsd\t{$src, $dst|$dst, $src}",
262 [(store FR64:$src, addr:$dst)]>, XD, VEX;
265 // Extract and store.
266 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
269 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
270 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
273 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
275 // Move Aligned/Unaligned floating point values
276 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
277 X86MemOperand x86memop, PatFrag ld_frag,
278 string asm, Domain d,
279 bit IsReMaterializable = 1> {
280 let neverHasSideEffects = 1 in
281 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
282 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
283 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
284 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
285 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
286 [(set RC:$dst, (ld_frag addr:$src))], d>;
289 let isAsmParserOnly = 1 in {
290 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
291 "movaps", SSEPackedSingle>, VEX;
292 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
293 "movapd", SSEPackedDouble>, OpSize, VEX;
294 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
295 "movups", SSEPackedSingle>, VEX;
296 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
297 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
299 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
300 "movaps", SSEPackedSingle>, VEX;
301 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
302 "movapd", SSEPackedDouble>, OpSize, VEX;
303 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
304 "movups", SSEPackedSingle>, VEX;
305 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
306 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
308 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
309 "movaps", SSEPackedSingle>, TB;
310 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
311 "movapd", SSEPackedDouble>, TB, OpSize;
312 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
313 "movups", SSEPackedSingle>, TB;
314 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
315 "movupd", SSEPackedDouble, 0>, TB, OpSize;
317 let isAsmParserOnly = 1 in {
318 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
319 "movaps\t{$src, $dst|$dst, $src}",
320 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
321 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
322 "movapd\t{$src, $dst|$dst, $src}",
323 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
324 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
325 "movups\t{$src, $dst|$dst, $src}",
326 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
327 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
328 "movupd\t{$src, $dst|$dst, $src}",
329 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
330 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
331 "movaps\t{$src, $dst|$dst, $src}",
332 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
333 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
334 "movapd\t{$src, $dst|$dst, $src}",
335 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
336 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
337 "movups\t{$src, $dst|$dst, $src}",
338 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
339 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
340 "movupd\t{$src, $dst|$dst, $src}",
341 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
343 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
344 "movaps\t{$src, $dst|$dst, $src}",
345 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
346 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
347 "movapd\t{$src, $dst|$dst, $src}",
348 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
349 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
350 "movups\t{$src, $dst|$dst, $src}",
351 [(store (v4f32 VR128:$src), addr:$dst)]>;
352 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
353 "movupd\t{$src, $dst|$dst, $src}",
354 [(store (v2f64 VR128:$src), addr:$dst)]>;
356 // Intrinsic forms of MOVUPS/D load and store
357 let isAsmParserOnly = 1 in {
358 let canFoldAsLoad = 1, isReMaterializable = 1 in
359 def VMOVUPSrm_Int : VPSI<0x10, MRMSrcMem, (outs VR128:$dst),
361 "movups\t{$src, $dst|$dst, $src}",
362 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>, VEX;
363 def VMOVUPDrm_Int : VPDI<0x10, MRMSrcMem, (outs VR128:$dst),
365 "movupd\t{$src, $dst|$dst, $src}",
366 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>, VEX;
367 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
368 (ins f128mem:$dst, VR128:$src),
369 "movups\t{$src, $dst|$dst, $src}",
370 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
371 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
372 (ins f128mem:$dst, VR128:$src),
373 "movupd\t{$src, $dst|$dst, $src}",
374 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
376 let canFoldAsLoad = 1, isReMaterializable = 1 in
377 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
378 "movups\t{$src, $dst|$dst, $src}",
379 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
380 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
381 "movupd\t{$src, $dst|$dst, $src}",
382 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
384 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
385 "movups\t{$src, $dst|$dst, $src}",
386 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
387 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
388 "movupd\t{$src, $dst|$dst, $src}",
389 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
391 // Move Low/High packed floating point values
392 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
393 PatFrag mov_frag, string base_opc,
395 def PSrm : PI<opc, MRMSrcMem,
396 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
397 !strconcat(!strconcat(base_opc,"s"), asm_opr),
400 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
401 SSEPackedSingle>, TB;
403 def PDrm : PI<opc, MRMSrcMem,
404 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
405 !strconcat(!strconcat(base_opc,"d"), asm_opr),
406 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
407 (scalar_to_vector (loadf64 addr:$src2)))))],
408 SSEPackedDouble>, TB, OpSize;
411 let isAsmParserOnly = 1, AddedComplexity = 20 in {
412 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
413 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
414 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
415 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
417 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
418 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
419 "\t{$src2, $dst|$dst, $src2}">;
420 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
421 "\t{$src2, $dst|$dst, $src2}">;
424 let isAsmParserOnly = 1 in {
425 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
426 "movlps\t{$src, $dst|$dst, $src}",
427 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
428 (iPTR 0))), addr:$dst)]>, VEX;
429 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
430 "movlpd\t{$src, $dst|$dst, $src}",
431 [(store (f64 (vector_extract (v2f64 VR128:$src),
432 (iPTR 0))), addr:$dst)]>, VEX;
434 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
435 "movlps\t{$src, $dst|$dst, $src}",
436 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
437 (iPTR 0))), addr:$dst)]>;
438 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
439 "movlpd\t{$src, $dst|$dst, $src}",
440 [(store (f64 (vector_extract (v2f64 VR128:$src),
441 (iPTR 0))), addr:$dst)]>;
443 // v2f64 extract element 1 is always custom lowered to unpack high to low
444 // and extract element 0 so the non-store version isn't too horrible.
445 let isAsmParserOnly = 1 in {
446 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
447 "movhps\t{$src, $dst|$dst, $src}",
448 [(store (f64 (vector_extract
449 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
450 (undef)), (iPTR 0))), addr:$dst)]>,
452 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
453 "movhpd\t{$src, $dst|$dst, $src}",
454 [(store (f64 (vector_extract
455 (v2f64 (unpckh VR128:$src, (undef))),
456 (iPTR 0))), addr:$dst)]>,
459 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
460 "movhps\t{$src, $dst|$dst, $src}",
461 [(store (f64 (vector_extract
462 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
463 (undef)), (iPTR 0))), addr:$dst)]>;
464 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
465 "movhpd\t{$src, $dst|$dst, $src}",
466 [(store (f64 (vector_extract
467 (v2f64 (unpckh VR128:$src, (undef))),
468 (iPTR 0))), addr:$dst)]>;
470 let isAsmParserOnly = 1, AddedComplexity = 20 in {
471 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
472 (ins VR128:$src1, VR128:$src2),
473 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
475 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
477 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
478 (ins VR128:$src1, VR128:$src2),
479 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
481 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
484 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
485 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
486 (ins VR128:$src1, VR128:$src2),
487 "movlhps\t{$src2, $dst|$dst, $src2}",
489 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
490 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
491 (ins VR128:$src1, VR128:$src2),
492 "movhlps\t{$src2, $dst|$dst, $src2}",
494 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
497 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
498 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
499 let AddedComplexity = 20 in {
500 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
501 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
502 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
503 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
506 //===----------------------------------------------------------------------===//
507 // SSE 1 & 2 - Conversion Instructions
508 //===----------------------------------------------------------------------===//
510 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
511 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
513 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
514 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
515 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
516 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
519 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
520 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
521 string asm, Domain d> {
522 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
523 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
524 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
525 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
528 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
529 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
531 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
533 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
534 (ins DstRC:$src1, x86memop:$src), asm, []>;
537 let isAsmParserOnly = 1 in {
538 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
539 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
540 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
541 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
542 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
543 "cvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}">, XS,
545 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
546 "cvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}">, XD,
550 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
551 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
552 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
553 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
554 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
555 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
556 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
557 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
559 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
560 // and/or XMM operand(s).
561 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
562 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
563 string asm, Domain d> {
564 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
565 [(set DstRC:$dst, (Int SrcRC:$src))], d>;
566 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
567 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>;
570 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
571 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
573 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
574 [(set DstRC:$dst, (Int SrcRC:$src))]>;
575 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
576 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
579 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
580 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
581 PatFrag ld_frag, string asm, Domain d> {
582 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
583 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>;
584 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
585 (ins DstRC:$src1, x86memop:$src2), asm,
586 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>;
589 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
590 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
591 PatFrag ld_frag, string asm> {
592 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
593 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
594 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
595 (ins DstRC:$src1, x86memop:$src2), asm,
596 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
599 let isAsmParserOnly = 1 in {
600 defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
601 f32mem, load, "cvtss2si\t{$src, $dst|$dst, $src}">, XS,
603 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
604 f128mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD,
607 defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
608 f32mem, load, "cvtss2si\t{$src, $dst|$dst, $src}">, XS;
609 defm Int_CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
610 f128mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD;
613 let Constraints = "$src1 = $dst" in {
614 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
615 int_x86_sse_cvtsi2ss, i32mem, loadi32,
616 "cvtsi2ss\t{$src2, $dst|$dst, $src2}">, XS;
617 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
618 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
619 "cvtsi2ss\t{$src2, $dst|$dst, $src2}">, XD;
622 // Instructions below don't have an AVX form.
623 defm Int_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
624 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
625 SSEPackedSingle>, TB;
626 defm Int_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
627 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
628 SSEPackedDouble>, TB, OpSize;
629 defm Int_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
630 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
631 SSEPackedSingle>, TB;
632 defm Int_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
633 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
634 SSEPackedDouble>, TB, OpSize;
635 defm Int_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
636 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
637 SSEPackedDouble>, TB, OpSize;
638 let Constraints = "$src1 = $dst" in {
639 defm Int_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
640 int_x86_sse_cvtpi2ps,
641 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
642 SSEPackedSingle>, TB;
647 // Aliases for intrinsics
648 let isAsmParserOnly = 1, Pattern = []<dag> in {
649 defm Int_VCVTTSS2SI : sse12_cvt_sint_3addr<0x2C, VR128, GR32,
650 int_x86_sse_cvttss2si, f32mem, load,
651 "cvttss2si\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS;
652 defm Int_VCVTTSD2SI : sse12_cvt_sint_3addr<0x2C, VR128, GR32,
653 int_x86_sse2_cvttsd2si, f128mem, load,
654 "cvttss2si\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD;
656 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
657 f32mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
659 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
660 f128mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
663 let isAsmParserOnly = 1, Pattern = []<dag> in {
664 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
665 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
666 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load,
667 "cvtdq2ps\t{$src, $dst|$dst, $src}",
668 SSEPackedSingle>, TB, VEX;
669 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, f256mem, load,
670 "cvtdq2ps\t{$src, $dst|$dst, $src}",
671 SSEPackedSingle>, TB, VEX;
673 let Pattern = []<dag> in {
674 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
675 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
676 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load /*dummy*/,
677 "cvtdq2ps\t{$src, $dst|$dst, $src}",
678 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
683 // Convert scalar double to scalar single
684 let isAsmParserOnly = 1 in {
685 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
686 (ins FR64:$src1, FR64:$src2),
687 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
689 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
690 (ins FR64:$src1, f64mem:$src2),
691 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
692 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
694 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
695 "cvtsd2ss\t{$src, $dst|$dst, $src}",
696 [(set FR32:$dst, (fround FR64:$src))]>;
697 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
698 "cvtsd2ss\t{$src, $dst|$dst, $src}",
699 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
700 Requires<[HasSSE2, OptForSize]>;
702 let isAsmParserOnly = 1 in
703 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
704 int_x86_sse2_cvtsd2ss, f64mem, load,
705 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
707 let Constraints = "$src1 = $dst" in
708 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
709 int_x86_sse2_cvtsd2ss, f64mem, load,
710 "cvtsd2ss\t{$src2, $dst|$dst, $src2}">, XS;
712 // Convert scalar single to scalar double
713 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
714 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
715 (ins FR32:$src1, FR32:$src2),
716 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
717 []>, XS, Requires<[HasAVX]>, VEX_4V;
718 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
719 (ins FR32:$src1, f32mem:$src2),
720 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
721 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
723 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
724 "cvtss2sd\t{$src, $dst|$dst, $src}",
725 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
727 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
728 "cvtss2sd\t{$src, $dst|$dst, $src}",
729 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
730 Requires<[HasSSE2, OptForSize]>;
732 let isAsmParserOnly = 1 in {
733 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
734 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
735 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
736 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
737 VR128:$src2))]>, XS, VEX_4V,
739 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
740 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
741 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
742 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
743 (load addr:$src2)))]>, XS, VEX_4V,
746 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
747 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
748 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
749 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
750 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
753 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
754 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
755 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
756 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
757 (load addr:$src2)))]>, XS,
761 def : Pat<(extloadf32 addr:$src),
762 (CVTSS2SDrr (MOVSSrm addr:$src))>,
763 Requires<[HasSSE2, OptForSpeed]>;
765 // Convert doubleword to packed single/double fp
766 let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
767 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
768 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
769 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
770 TB, VEX, Requires<[HasAVX]>;
771 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
772 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
773 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
774 (bitconvert (memopv2i64 addr:$src))))]>,
775 TB, VEX, Requires<[HasAVX]>;
777 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
778 "cvtdq2ps\t{$src, $dst|$dst, $src}",
779 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
780 TB, Requires<[HasSSE2]>;
781 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
782 "cvtdq2ps\t{$src, $dst|$dst, $src}",
783 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
784 (bitconvert (memopv2i64 addr:$src))))]>,
785 TB, Requires<[HasSSE2]>;
787 // FIXME: why the non-intrinsic version is described as SSE3?
788 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
789 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
790 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
791 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
792 XS, VEX, Requires<[HasAVX]>;
793 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
794 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
795 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
796 (bitconvert (memopv2i64 addr:$src))))]>,
797 XS, VEX, Requires<[HasAVX]>;
799 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
800 "cvtdq2pd\t{$src, $dst|$dst, $src}",
801 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
802 XS, Requires<[HasSSE2]>;
803 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
804 "cvtdq2pd\t{$src, $dst|$dst, $src}",
805 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
806 (bitconvert (memopv2i64 addr:$src))))]>,
807 XS, Requires<[HasSSE2]>;
809 // Convert packed single/double fp to doubleword
810 let isAsmParserOnly = 1 in {
811 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
812 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
813 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
814 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
815 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
816 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
817 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
818 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
820 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
821 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
822 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
823 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
825 let isAsmParserOnly = 1 in {
826 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
827 "cvtps2dq\t{$src, $dst|$dst, $src}",
828 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
830 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
832 "cvtps2dq\t{$src, $dst|$dst, $src}",
833 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
834 (memop addr:$src)))]>, VEX;
836 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
837 "cvtps2dq\t{$src, $dst|$dst, $src}",
838 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
839 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
840 "cvtps2dq\t{$src, $dst|$dst, $src}",
841 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
842 (memop addr:$src)))]>;
844 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XD prefix
845 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
846 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
847 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
848 XD, VEX, Requires<[HasAVX]>;
849 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
850 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
851 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
852 (memop addr:$src)))]>,
853 XD, VEX, Requires<[HasAVX]>;
855 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
856 "cvtpd2dq\t{$src, $dst|$dst, $src}",
857 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
858 XD, Requires<[HasSSE2]>;
859 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
860 "cvtpd2dq\t{$src, $dst|$dst, $src}",
861 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
862 (memop addr:$src)))]>,
863 XD, Requires<[HasSSE2]>;
866 // Convert with truncation packed single/double fp to doubleword
867 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XS prefix
868 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
869 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
870 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
871 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
872 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
873 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
874 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
875 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
877 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
878 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
879 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
880 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
883 let isAsmParserOnly = 1 in {
884 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
885 "vcvttps2dq\t{$src, $dst|$dst, $src}",
887 (int_x86_sse2_cvttps2dq VR128:$src))]>,
888 XS, VEX, Requires<[HasAVX]>;
889 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
890 "vcvttps2dq\t{$src, $dst|$dst, $src}",
891 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
892 (memop addr:$src)))]>,
893 XS, VEX, Requires<[HasAVX]>;
895 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
896 "cvttps2dq\t{$src, $dst|$dst, $src}",
898 (int_x86_sse2_cvttps2dq VR128:$src))]>,
899 XS, Requires<[HasSSE2]>;
900 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
901 "cvttps2dq\t{$src, $dst|$dst, $src}",
902 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
903 (memop addr:$src)))]>,
904 XS, Requires<[HasSSE2]>;
906 let isAsmParserOnly = 1 in {
907 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
909 "cvttpd2dq\t{$src, $dst|$dst, $src}",
910 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
912 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
914 "cvttpd2dq\t{$src, $dst|$dst, $src}",
915 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
916 (memop addr:$src)))]>, VEX;
918 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
919 "cvttpd2dq\t{$src, $dst|$dst, $src}",
920 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
921 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
922 "cvttpd2dq\t{$src, $dst|$dst, $src}",
923 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
924 (memop addr:$src)))]>;
926 let isAsmParserOnly = 1 in {
927 // The assembler can recognize rr 256-bit instructions by seeing a ymm
928 // register, but the same isn't true when using memory operands instead.
929 // Provide other assembly rr and rm forms to address this explicitly.
930 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
931 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
932 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
933 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
936 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
937 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
938 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
939 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
942 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
943 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
944 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
945 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
948 // Convert packed single to packed double
949 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
950 // SSE2 instructions without OpSize prefix
951 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
952 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
953 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
954 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
955 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
956 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
957 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
958 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
960 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
961 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
962 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
963 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
965 let isAsmParserOnly = 1 in {
966 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
967 "cvtps2pd\t{$src, $dst|$dst, $src}",
968 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
969 VEX, Requires<[HasAVX]>;
970 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
971 "cvtps2pd\t{$src, $dst|$dst, $src}",
972 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
973 (load addr:$src)))]>,
974 VEX, Requires<[HasAVX]>;
976 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
977 "cvtps2pd\t{$src, $dst|$dst, $src}",
978 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
979 TB, Requires<[HasSSE2]>;
980 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
981 "cvtps2pd\t{$src, $dst|$dst, $src}",
982 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
983 (load addr:$src)))]>,
984 TB, Requires<[HasSSE2]>;
986 // Convert packed double to packed single
987 let isAsmParserOnly = 1 in {
988 // The assembler can recognize rr 256-bit instructions by seeing a ymm
989 // register, but the same isn't true when using memory operands instead.
990 // Provide other assembly rr and rm forms to address this explicitly.
991 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
992 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
993 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
994 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
997 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
998 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
999 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1000 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1003 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1004 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1005 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1006 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1008 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1009 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1010 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1011 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1014 let isAsmParserOnly = 1 in {
1015 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1016 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1017 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1018 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1020 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1021 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1022 (memop addr:$src)))]>;
1024 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1025 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1026 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1027 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1028 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1029 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1030 (memop addr:$src)))]>;
1032 //===----------------------------------------------------------------------===//
1033 // SSE 1 & 2 - Compare Instructions
1034 //===----------------------------------------------------------------------===//
1036 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1037 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1038 string asm, string asm_alt> {
1039 def rr : SIi8<0xC2, MRMSrcReg,
1040 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1043 def rm : SIi8<0xC2, MRMSrcMem,
1044 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1046 // Accept explicit immediate argument form instead of comparison code.
1047 let isAsmParserOnly = 1 in {
1048 def rr_alt : SIi8<0xC2, MRMSrcReg,
1049 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1052 def rm_alt : SIi8<0xC2, MRMSrcMem,
1053 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1058 let neverHasSideEffects = 1, isAsmParserOnly = 1 in {
1059 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1060 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1061 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1063 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1064 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1065 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1069 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1070 defm CMPSS : sse12_cmp_scalar<FR32, f32mem,
1071 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
1072 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}">, XS;
1073 defm CMPSD : sse12_cmp_scalar<FR64, f64mem,
1074 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1075 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}">, XD;
1078 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1079 Intrinsic Int, string asm> {
1080 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1081 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1082 [(set VR128:$dst, (Int VR128:$src1,
1083 VR128:$src, imm:$cc))]>;
1084 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1085 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1086 [(set VR128:$dst, (Int VR128:$src1,
1087 (load addr:$src), imm:$cc))]>;
1090 // Aliases to match intrinsics which expect XMM operand(s).
1091 let isAsmParserOnly = 1 in {
1092 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1093 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1095 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1096 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1099 let Constraints = "$src1 = $dst" in {
1100 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1101 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1102 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1103 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1107 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1108 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1109 ValueType vt, X86MemOperand x86memop,
1110 PatFrag ld_frag, string OpcodeStr, Domain d> {
1111 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1112 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1113 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1114 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1115 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1116 [(set EFLAGS, (OpNode (vt RC:$src1),
1117 (ld_frag addr:$src2)))], d>;
1120 let Defs = [EFLAGS] in {
1121 let isAsmParserOnly = 1 in {
1122 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1123 "ucomiss", SSEPackedSingle>, VEX;
1124 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1125 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1126 let Pattern = []<dag> in {
1127 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1128 "comiss", SSEPackedSingle>, VEX;
1129 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1130 "comisd", SSEPackedDouble>, OpSize, VEX;
1133 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1134 load, "ucomiss", SSEPackedSingle>, VEX;
1135 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1136 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1138 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1139 load, "comiss", SSEPackedSingle>, VEX;
1140 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1141 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1143 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1144 "ucomiss", SSEPackedSingle>, TB;
1145 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1146 "ucomisd", SSEPackedDouble>, TB, OpSize;
1148 let Pattern = []<dag> in {
1149 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1150 "comiss", SSEPackedSingle>, TB;
1151 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1152 "comisd", SSEPackedDouble>, TB, OpSize;
1155 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1156 load, "ucomiss", SSEPackedSingle>, TB;
1157 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1158 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1160 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1161 "comiss", SSEPackedSingle>, TB;
1162 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1163 "comisd", SSEPackedDouble>, TB, OpSize;
1164 } // Defs = [EFLAGS]
1166 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1167 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1168 Intrinsic Int, string asm, string asm_alt,
1170 def rri : PIi8<0xC2, MRMSrcReg,
1171 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1172 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1173 def rmi : PIi8<0xC2, MRMSrcMem,
1174 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1175 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1176 // Accept explicit immediate argument form instead of comparison code.
1177 let isAsmParserOnly = 1 in {
1178 def rri_alt : PIi8<0xC2, MRMSrcReg,
1179 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1181 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1182 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1187 let isAsmParserOnly = 1 in {
1188 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1189 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1190 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1191 SSEPackedSingle>, VEX_4V;
1192 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1193 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1194 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1195 SSEPackedDouble>, OpSize, VEX_4V;
1196 let Pattern = []<dag> in {
1197 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_sse_cmp_ps,
1198 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1199 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1200 SSEPackedSingle>, VEX_4V;
1201 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_sse2_cmp_pd,
1202 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1203 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1204 SSEPackedDouble>, OpSize, VEX_4V;
1207 let Constraints = "$src1 = $dst" in {
1208 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1209 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1210 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1211 SSEPackedSingle>, TB;
1212 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1213 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1214 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1215 SSEPackedDouble>, TB, OpSize;
1218 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1219 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1220 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1221 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1222 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1223 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1224 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1225 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1227 //===----------------------------------------------------------------------===//
1228 // SSE 1 & 2 - Shuffle Instructions
1229 //===----------------------------------------------------------------------===//
1231 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1232 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1233 ValueType vt, string asm, PatFrag mem_frag,
1234 Domain d, bit IsConvertibleToThreeAddress = 0> {
1235 def rmi : PIi8<0xC6, MRMSrcMem, (outs VR128:$dst),
1236 (ins VR128:$src1, f128mem:$src2, i8imm:$src3), asm,
1237 [(set VR128:$dst, (vt (shufp:$src3
1238 VR128:$src1, (mem_frag addr:$src2))))], d>;
1239 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1240 def rri : PIi8<0xC6, MRMSrcReg, (outs VR128:$dst),
1241 (ins VR128:$src1, VR128:$src2, i8imm:$src3), asm,
1243 (vt (shufp:$src3 VR128:$src1, VR128:$src2)))], d>;
1246 let isAsmParserOnly = 1 in {
1247 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1248 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1249 memopv4f32, SSEPackedSingle>, VEX_4V;
1250 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1251 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1252 memopv2f64, SSEPackedDouble>, OpSize, VEX_4V;
1255 let Constraints = "$src1 = $dst" in {
1256 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1257 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1258 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1260 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1261 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1262 memopv2f64, SSEPackedDouble>, TB, OpSize;
1265 //===----------------------------------------------------------------------===//
1266 // SSE 1 & 2 - Unpack Instructions
1267 //===----------------------------------------------------------------------===//
1269 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1270 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1271 PatFrag mem_frag, RegisterClass RC,
1272 X86MemOperand x86memop, string asm,
1274 def rr : PI<opc, MRMSrcReg,
1275 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1277 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1278 def rm : PI<opc, MRMSrcMem,
1279 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1281 (vt (OpNode RC:$src1,
1282 (mem_frag addr:$src2))))], d>;
1285 let AddedComplexity = 10 in {
1286 let isAsmParserOnly = 1 in {
1287 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1288 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1289 SSEPackedSingle>, VEX_4V;
1290 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1291 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1292 SSEPackedDouble>, OpSize, VEX_4V;
1293 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1294 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1295 SSEPackedSingle>, VEX_4V;
1296 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1297 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1298 SSEPackedDouble>, OpSize, VEX_4V;
1300 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1301 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1302 SSEPackedSingle>, VEX_4V;
1303 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1304 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1305 SSEPackedDouble>, OpSize, VEX_4V;
1306 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1307 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1308 SSEPackedSingle>, VEX_4V;
1309 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1310 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1311 SSEPackedDouble>, OpSize, VEX_4V;
1314 let Constraints = "$src1 = $dst" in {
1315 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1316 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1317 SSEPackedSingle>, TB;
1318 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1319 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1320 SSEPackedDouble>, TB, OpSize;
1321 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1322 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1323 SSEPackedSingle>, TB;
1324 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1325 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1326 SSEPackedDouble>, TB, OpSize;
1327 } // Constraints = "$src1 = $dst"
1328 } // AddedComplexity
1330 //===----------------------------------------------------------------------===//
1331 // SSE 1 & 2 - Extract Floating-Point Sign mask
1332 //===----------------------------------------------------------------------===//
1334 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1335 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1337 def rr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1338 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1339 [(set GR32:$dst, (Int RC:$src))], d>;
1343 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1344 SSEPackedSingle>, TB;
1345 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1346 SSEPackedDouble>, TB, OpSize;
1348 let isAsmParserOnly = 1 in {
1349 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1350 "movmskps", SSEPackedSingle>, VEX;
1351 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1352 "movmskpd", SSEPackedDouble>, OpSize,
1354 // FIXME: merge with multiclass above when the intrinsics come.
1355 def VMOVMSKPSYrr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
1356 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1357 def VMOVMSKPDYrr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
1358 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1362 //===----------------------------------------------------------------------===//
1363 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1364 //===----------------------------------------------------------------------===//
1366 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1367 // names that start with 'Fs'.
1369 // Alias instructions that map fld0 to pxor for sse.
1370 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1371 canFoldAsLoad = 1 in {
1372 // FIXME: Set encoding to pseudo!
1373 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1374 [(set FR32:$dst, fp32imm0)]>,
1375 Requires<[HasSSE1]>, TB, OpSize;
1376 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1377 [(set FR64:$dst, fpimm0)]>,
1378 Requires<[HasSSE2]>, TB, OpSize;
1381 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1382 // bits are disregarded.
1383 let neverHasSideEffects = 1 in {
1384 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1385 "movaps\t{$src, $dst|$dst, $src}", []>;
1386 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1387 "movapd\t{$src, $dst|$dst, $src}", []>;
1390 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1391 // bits are disregarded.
1392 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1393 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1394 "movaps\t{$src, $dst|$dst, $src}",
1395 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1396 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1397 "movapd\t{$src, $dst|$dst, $src}",
1398 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1401 //===----------------------------------------------------------------------===//
1402 // SSE 1 & 2 - Logical Instructions
1403 //===----------------------------------------------------------------------===//
1405 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1407 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1409 let isAsmParserOnly = 1 in {
1410 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
1411 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
1413 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
1414 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
1417 let Constraints = "$src1 = $dst" in {
1418 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
1419 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
1421 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
1422 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
1426 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1427 let mayLoad = 0 in {
1428 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1429 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1430 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1433 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1434 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
1436 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1438 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1439 SDNode OpNode, int HasPat = 0,
1440 list<list<dag>> Pattern = []> {
1441 let isAsmParserOnly = 1, Pattern = []<dag> in {
1442 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1443 !strconcat(OpcodeStr, "ps"), f128mem,
1444 !if(HasPat, Pattern[0], // rr
1445 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1447 !if(HasPat, Pattern[2], // rm
1448 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1449 (memopv2i64 addr:$src2)))]), 0>,
1452 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1453 !strconcat(OpcodeStr, "pd"), f128mem,
1454 !if(HasPat, Pattern[1], // rr
1455 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1458 !if(HasPat, Pattern[3], // rm
1459 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1460 (memopv2i64 addr:$src2)))]), 0>,
1463 let Constraints = "$src1 = $dst" in {
1464 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1465 !strconcat(OpcodeStr, "ps"), f128mem,
1466 !if(HasPat, Pattern[0], // rr
1467 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1469 !if(HasPat, Pattern[2], // rm
1470 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1471 (memopv2i64 addr:$src2)))])>, TB;
1473 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1474 !strconcat(OpcodeStr, "pd"), f128mem,
1475 !if(HasPat, Pattern[1], // rr
1476 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1479 !if(HasPat, Pattern[3], // rm
1480 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1481 (memopv2i64 addr:$src2)))])>,
1486 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
1488 let isAsmParserOnly = 1 in {
1489 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr> {
1490 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
1491 !strconcat(OpcodeStr, "ps"), f256mem, [], [], 0>, VEX_4V;
1493 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
1494 !strconcat(OpcodeStr, "pd"), f256mem, [], [], 0>, OpSize, VEX_4V;
1498 // AVX 256-bit packed logical ops forms
1499 defm VAND : sse12_fp_packed_logical_y<0x54, "and">;
1500 defm VOR : sse12_fp_packed_logical_y<0x56, "or">;
1501 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor">;
1502 let isCommutable = 0 in
1503 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn">;
1505 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1506 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1507 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1508 let isCommutable = 0 in
1509 defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
1511 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1512 (bc_v2i64 (v4i32 immAllOnesV))),
1515 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1516 (bc_v2i64 (v2f64 VR128:$src2))))],
1518 [(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
1519 (bc_v2i64 (v4i32 immAllOnesV))),
1520 (memopv2i64 addr:$src2))))],
1522 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1523 (memopv2i64 addr:$src2)))]]>;
1525 //===----------------------------------------------------------------------===//
1526 // SSE 1 & 2 - Arithmetic Instructions
1527 //===----------------------------------------------------------------------===//
1529 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
1532 /// In addition, we also have a special variant of the scalar form here to
1533 /// represent the associated intrinsic operation. This form is unlike the
1534 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1535 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1537 /// These three forms can each be reg+reg or reg+mem.
1539 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1541 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
1542 OpNode, FR32, f32mem, Is2Addr>, XS;
1543 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
1544 OpNode, FR64, f64mem, Is2Addr>, XD;
1547 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
1549 let mayLoad = 0 in {
1550 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
1551 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
1552 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
1553 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
1557 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
1559 let mayLoad = 0 in {
1560 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
1561 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1562 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
1563 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
1567 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
1569 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1570 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
1571 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1572 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
1575 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
1577 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1578 !strconcat(OpcodeStr, "ps"), "", "_ps", f128mem, memopv4f32,
1579 SSEPackedSingle, Is2Addr>, TB;
1581 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1582 !strconcat(OpcodeStr, "pd"), "2", "_pd", f128mem, memopv2f64,
1583 SSEPackedDouble, Is2Addr>, TB, OpSize;
1586 // Binary Arithmetic instructions
1587 let isAsmParserOnly = 1 in {
1588 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
1589 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
1590 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
1591 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
1592 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
1593 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
1595 let isCommutable = 0 in {
1596 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
1597 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
1598 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
1599 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
1600 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
1601 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
1602 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
1603 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
1604 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>, VEX_4V;
1605 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
1606 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
1607 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
1611 let Constraints = "$src1 = $dst" in {
1612 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
1613 basic_sse12_fp_binop_p<0x58, "add", fadd>,
1614 basic_sse12_fp_binop_s_int<0x58, "add">;
1615 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
1616 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
1617 basic_sse12_fp_binop_s_int<0x59, "mul">;
1619 let isCommutable = 0 in {
1620 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
1621 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
1622 basic_sse12_fp_binop_s_int<0x5C, "sub">;
1623 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
1624 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
1625 basic_sse12_fp_binop_s_int<0x5E, "div">;
1626 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
1627 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
1628 basic_sse12_fp_binop_s_int<0x5F, "max">,
1629 basic_sse12_fp_binop_p_int<0x5F, "max">;
1630 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
1631 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
1632 basic_sse12_fp_binop_s_int<0x5D, "min">,
1633 basic_sse12_fp_binop_p_int<0x5D, "min">;
1638 /// In addition, we also have a special variant of the scalar form here to
1639 /// represent the associated intrinsic operation. This form is unlike the
1640 /// plain scalar form, in that it takes an entire vector (instead of a
1641 /// scalar) and leaves the top elements undefined.
1643 /// And, we have a special variant form for a full-vector intrinsic form.
1645 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1646 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1647 SDNode OpNode, Intrinsic F32Int> {
1648 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1649 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1650 [(set FR32:$dst, (OpNode FR32:$src))]>;
1651 // For scalar unary operations, fold a load into the operation
1652 // only in OptForSize mode. It eliminates an instruction, but it also
1653 // eliminates a whole-register clobber (the load), so it introduces a
1654 // partial register update condition.
1655 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1656 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1657 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1658 Requires<[HasSSE1, OptForSize]>;
1659 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1660 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1661 [(set VR128:$dst, (F32Int VR128:$src))]>;
1662 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1663 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1664 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1667 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1668 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1669 SDNode OpNode, Intrinsic F32Int> {
1670 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1671 !strconcat(!strconcat("v", OpcodeStr),
1672 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1673 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1674 !strconcat(!strconcat("v", OpcodeStr),
1675 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1676 []>, XS, Requires<[HasAVX, OptForSize]>;
1677 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
1678 (ins VR128:$src1, VR128:$src2),
1679 !strconcat(!strconcat("v", OpcodeStr),
1680 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1681 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
1682 (ins VR128:$src1, ssmem:$src2),
1683 !strconcat(!strconcat("v", OpcodeStr),
1684 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1687 /// sse1_fp_unop_p - SSE1 unops in packed form.
1688 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1689 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1690 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1691 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1692 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1693 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1694 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1697 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
1698 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1699 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1700 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1701 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1702 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1703 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1704 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1707 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
1708 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1709 Intrinsic V4F32Int> {
1710 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1711 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1712 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1713 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1714 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1715 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1719 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1720 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1721 SDNode OpNode, Intrinsic F64Int> {
1722 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1723 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1724 [(set FR64:$dst, (OpNode FR64:$src))]>;
1725 // See the comments in sse1_fp_unop_s for why this is OptForSize.
1726 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1727 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1728 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1729 Requires<[HasSSE2, OptForSize]>;
1730 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1731 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1732 [(set VR128:$dst, (F64Int VR128:$src))]>;
1733 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1734 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1735 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1738 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1739 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1740 SDNode OpNode, Intrinsic F64Int> {
1741 def SDr : VSDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1742 !strconcat(OpcodeStr,
1743 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1744 def SDm : VSDI<opc, MRMSrcMem, (outs FR64:$dst),
1745 (ins FR64:$src1, f64mem:$src2),
1746 !strconcat(OpcodeStr,
1747 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1748 def SDr_Int : VSDI<opc, MRMSrcReg, (outs VR128:$dst),
1749 (ins VR128:$src1, VR128:$src2),
1750 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1752 def SDm_Int : VSDI<opc, MRMSrcMem, (outs VR128:$dst),
1753 (ins VR128:$src1, sdmem:$src2),
1754 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1758 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1759 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1761 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1762 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1763 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1764 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1765 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1766 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1769 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
1770 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1771 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1772 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1773 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
1774 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1775 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1776 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
1779 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
1780 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1781 Intrinsic V2F64Int> {
1782 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1783 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1784 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1785 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1786 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1787 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1790 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
1792 defm VSQRT : sse1_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
1793 sse2_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1796 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
1797 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
1798 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1799 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1802 // Reciprocal approximations. Note that these typically require refinement
1803 // in order to obtain suitable precision.
1804 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "rsqrt", X86frsqrt,
1805 int_x86_sse_rsqrt_ss>, VEX_4V;
1806 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
1807 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>, VEX;
1809 defm VRCP : sse1_fp_unop_s_avx<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
1811 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
1812 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>, VEX;
1816 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
1817 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
1818 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
1819 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1820 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
1821 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
1823 // Reciprocal approximations. Note that these typically require refinement
1824 // in order to obtain suitable precision.
1825 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
1826 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
1827 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
1828 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
1829 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
1830 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
1832 // There is no f64 version of the reciprocal approximation instructions.
1834 //===----------------------------------------------------------------------===//
1835 // SSE 1 & 2 - Non-temporal stores
1836 //===----------------------------------------------------------------------===//
1838 let isAsmParserOnly = 1 in {
1839 def VMOVNTPSmr_Int : VPSI<0x2B, MRMDestMem, (outs),
1840 (ins i128mem:$dst, VR128:$src),
1841 "movntps\t{$src, $dst|$dst, $src}",
1842 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>, VEX;
1843 def VMOVNTPDmr_Int : VPDI<0x2B, MRMDestMem, (outs),
1844 (ins i128mem:$dst, VR128:$src),
1845 "movntpd\t{$src, $dst|$dst, $src}",
1846 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>, VEX;
1848 let ExeDomain = SSEPackedInt in
1849 def VMOVNTDQmr_Int : VPDI<0xE7, MRMDestMem, (outs),
1850 (ins f128mem:$dst, VR128:$src),
1851 "movntdq\t{$src, $dst|$dst, $src}",
1852 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>, VEX;
1854 let AddedComplexity = 400 in { // Prefer non-temporal versions
1855 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
1856 (ins f128mem:$dst, VR128:$src),
1857 "movntps\t{$src, $dst|$dst, $src}",
1858 [(alignednontemporalstore (v4f32 VR128:$src),
1860 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
1861 (ins f128mem:$dst, VR128:$src),
1862 "movntpd\t{$src, $dst|$dst, $src}",
1863 [(alignednontemporalstore (v2f64 VR128:$src),
1865 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
1866 (ins f128mem:$dst, VR128:$src),
1867 "movntdq\t{$src, $dst|$dst, $src}",
1868 [(alignednontemporalstore (v2f64 VR128:$src),
1870 let ExeDomain = SSEPackedInt in
1871 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
1872 (ins f128mem:$dst, VR128:$src),
1873 "movntdq\t{$src, $dst|$dst, $src}",
1874 [(alignednontemporalstore (v4f32 VR128:$src),
1877 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
1878 (ins f256mem:$dst, VR256:$src),
1879 "movntps\t{$src, $dst|$dst, $src}",
1880 [(alignednontemporalstore (v8f32 VR256:$src),
1882 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
1883 (ins f256mem:$dst, VR256:$src),
1884 "movntpd\t{$src, $dst|$dst, $src}",
1885 [(alignednontemporalstore (v4f64 VR256:$src),
1887 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
1888 (ins f256mem:$dst, VR256:$src),
1889 "movntdq\t{$src, $dst|$dst, $src}",
1890 [(alignednontemporalstore (v4f64 VR256:$src),
1892 let ExeDomain = SSEPackedInt in
1893 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
1894 (ins f256mem:$dst, VR256:$src),
1895 "movntdq\t{$src, $dst|$dst, $src}",
1896 [(alignednontemporalstore (v8f32 VR256:$src),
1901 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1902 "movntps\t{$src, $dst|$dst, $src}",
1903 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1904 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1905 "movntpd\t{$src, $dst|$dst, $src}",
1906 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
1908 let ExeDomain = SSEPackedInt in
1909 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1910 "movntdq\t{$src, $dst|$dst, $src}",
1911 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
1913 let AddedComplexity = 400 in { // Prefer non-temporal versions
1914 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1915 "movntps\t{$src, $dst|$dst, $src}",
1916 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1917 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1918 "movntpd\t{$src, $dst|$dst, $src}",
1919 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
1921 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1922 "movntdq\t{$src, $dst|$dst, $src}",
1923 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1925 let ExeDomain = SSEPackedInt in
1926 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1927 "movntdq\t{$src, $dst|$dst, $src}",
1928 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1930 // There is no AVX form for instructions below this point
1931 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1932 "movnti\t{$src, $dst|$dst, $src}",
1933 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1934 TB, Requires<[HasSSE2]>;
1936 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1937 "movnti\t{$src, $dst|$dst, $src}",
1938 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
1939 TB, Requires<[HasSSE2]>;
1942 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1943 "movnti\t{$src, $dst|$dst, $src}",
1944 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
1945 TB, Requires<[HasSSE2]>;
1947 //===----------------------------------------------------------------------===//
1948 // SSE 1 & 2 - Misc Instructions (No AVX form)
1949 //===----------------------------------------------------------------------===//
1951 // Prefetch intrinsic.
1952 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1953 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1954 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1955 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1956 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1957 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1958 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1959 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1961 // Load, store, and memory fence
1962 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
1963 TB, Requires<[HasSSE1]>;
1965 // Alias instructions that map zero vector to pxor / xorp* for sse.
1966 // We set canFoldAsLoad because this can be converted to a constant-pool
1967 // load of an all-zeros value if folding it would be beneficial.
1968 // FIXME: Change encoding to pseudo!
1969 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
1970 isCodeGenOnly = 1 in {
1971 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1972 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1973 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1974 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
1975 let ExeDomain = SSEPackedInt in
1976 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
1977 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1980 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
1981 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
1982 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
1984 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1985 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1987 //===----------------------------------------------------------------------===//
1988 // SSE 1 & 2 - Load/Store XCSR register
1989 //===----------------------------------------------------------------------===//
1991 let isAsmParserOnly = 1 in {
1992 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1993 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
1994 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
1995 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
1998 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1999 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2000 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2001 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2003 //===---------------------------------------------------------------------===//
2004 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2005 //===---------------------------------------------------------------------===//
2006 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2008 let isAsmParserOnly = 1 in {
2009 let neverHasSideEffects = 1 in
2010 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2011 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2012 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2013 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2015 let canFoldAsLoad = 1, mayLoad = 1 in {
2016 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2017 "movdqa\t{$src, $dst|$dst, $src}",
2018 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>,
2020 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2021 "vmovdqu\t{$src, $dst|$dst, $src}",
2022 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2023 XS, VEX, Requires<[HasAVX]>;
2026 let mayStore = 1 in {
2027 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2028 (ins i128mem:$dst, VR128:$src),
2029 "movdqa\t{$src, $dst|$dst, $src}",
2030 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>, VEX;
2031 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2032 "vmovdqu\t{$src, $dst|$dst, $src}",
2033 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2034 XS, VEX, Requires<[HasAVX]>;
2038 let neverHasSideEffects = 1 in
2039 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2040 "movdqa\t{$src, $dst|$dst, $src}", []>;
2042 let canFoldAsLoad = 1, mayLoad = 1 in {
2043 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2044 "movdqa\t{$src, $dst|$dst, $src}",
2045 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2046 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2047 "movdqu\t{$src, $dst|$dst, $src}",
2048 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2049 XS, Requires<[HasSSE2]>;
2052 let mayStore = 1 in {
2053 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2054 "movdqa\t{$src, $dst|$dst, $src}",
2055 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2056 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2057 "movdqu\t{$src, $dst|$dst, $src}",
2058 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2059 XS, Requires<[HasSSE2]>;
2062 // Intrinsic forms of MOVDQU load and store
2063 let isAsmParserOnly = 1 in {
2064 let canFoldAsLoad = 1 in
2065 def VMOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2066 "vmovdqu\t{$src, $dst|$dst, $src}",
2067 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2068 XS, VEX, Requires<[HasAVX]>;
2069 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2070 "vmovdqu\t{$src, $dst|$dst, $src}",
2071 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2072 XS, VEX, Requires<[HasAVX]>;
2075 let canFoldAsLoad = 1 in
2076 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2077 "movdqu\t{$src, $dst|$dst, $src}",
2078 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2079 XS, Requires<[HasSSE2]>;
2080 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2081 "movdqu\t{$src, $dst|$dst, $src}",
2082 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2083 XS, Requires<[HasSSE2]>;
2085 } // ExeDomain = SSEPackedInt
2087 //===---------------------------------------------------------------------===//
2088 // SSE2 - Packed Integer Arithmetic Instructions
2089 //===---------------------------------------------------------------------===//
2091 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2093 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2094 bit IsCommutable = 0, bit Is2Addr = 1> {
2095 let isCommutable = IsCommutable in
2096 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2097 (ins VR128:$src1, VR128:$src2),
2099 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2100 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2101 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2102 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2103 (ins VR128:$src1, i128mem:$src2),
2105 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2106 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2107 [(set VR128:$dst, (IntId VR128:$src1,
2108 (bitconvert (memopv2i64 addr:$src2))))]>;
2111 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2112 string OpcodeStr, Intrinsic IntId,
2113 Intrinsic IntId2, bit Is2Addr = 1> {
2114 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2115 (ins VR128:$src1, VR128:$src2),
2117 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2118 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2119 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2120 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2121 (ins VR128:$src1, i128mem:$src2),
2123 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2124 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2125 [(set VR128:$dst, (IntId VR128:$src1,
2126 (bitconvert (memopv2i64 addr:$src2))))]>;
2127 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2128 (ins VR128:$src1, i32i8imm:$src2),
2130 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2131 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2132 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2135 /// PDI_binop_rm - Simple SSE2 binary operator.
2136 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2137 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2138 let isCommutable = IsCommutable in
2139 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2140 (ins VR128:$src1, VR128:$src2),
2142 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2143 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2144 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2145 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2146 (ins VR128:$src1, i128mem:$src2),
2148 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2149 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2150 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2151 (bitconvert (memopv2i64 addr:$src2)))))]>;
2154 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2156 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2157 /// to collapse (bitconvert VT to VT) into its operand.
2159 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2160 bit IsCommutable = 0, bit Is2Addr = 1> {
2161 let isCommutable = IsCommutable in
2162 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2163 (ins VR128:$src1, VR128:$src2),
2165 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2166 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2167 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2168 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2169 (ins VR128:$src1, i128mem:$src2),
2171 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2172 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2173 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2176 } // ExeDomain = SSEPackedInt
2178 // 128-bit Integer Arithmetic
2180 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2181 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2182 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2183 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2184 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2185 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2186 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2187 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2188 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2189 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2192 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2194 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2196 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2198 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2200 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2202 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2204 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2206 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2208 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2210 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2212 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2214 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2216 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2218 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2220 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2222 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2224 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2226 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2228 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2232 let Constraints = "$src1 = $dst" in {
2233 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2234 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2235 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2236 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2237 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2238 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2239 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2240 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2241 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2244 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2245 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2246 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2247 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2248 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2249 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2250 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2251 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2252 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2253 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2254 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2255 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2256 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2257 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2258 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2259 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2260 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2261 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2262 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2264 } // Constraints = "$src1 = $dst"
2266 //===---------------------------------------------------------------------===//
2267 // SSE2 - Packed Integer Logical Instructions
2268 //===---------------------------------------------------------------------===//
2270 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2271 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2272 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2274 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2275 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2277 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2278 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2281 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2282 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2284 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2285 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2287 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2288 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2291 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2292 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2294 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2295 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2298 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2299 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2300 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2302 let ExeDomain = SSEPackedInt in {
2303 let neverHasSideEffects = 1 in {
2304 // 128-bit logical shifts.
2305 def VPSLLDQri : PDIi8<0x73, MRM7r,
2306 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2307 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2309 def VPSRLDQri : PDIi8<0x73, MRM3r,
2310 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2311 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2313 // PSRADQri doesn't exist in SSE[1-3].
2315 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2316 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2317 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2318 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2319 VR128:$src2)))]>, VEX_4V;
2321 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2322 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2323 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2324 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2325 (memopv2i64 addr:$src2))))]>,
2330 let Constraints = "$src1 = $dst" in {
2331 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2332 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2333 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2334 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2335 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2336 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2338 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2339 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2340 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2341 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2342 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2343 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2345 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2346 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2347 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2348 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2350 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2351 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2352 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2354 let ExeDomain = SSEPackedInt in {
2355 let neverHasSideEffects = 1 in {
2356 // 128-bit logical shifts.
2357 def PSLLDQri : PDIi8<0x73, MRM7r,
2358 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2359 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2360 def PSRLDQri : PDIi8<0x73, MRM3r,
2361 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2362 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2363 // PSRADQri doesn't exist in SSE[1-3].
2365 def PANDNrr : PDI<0xDF, MRMSrcReg,
2366 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2367 "pandn\t{$src2, $dst|$dst, $src2}",
2368 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2371 def PANDNrm : PDI<0xDF, MRMSrcMem,
2372 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2373 "pandn\t{$src2, $dst|$dst, $src2}",
2374 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2375 (memopv2i64 addr:$src2))))]>;
2377 } // Constraints = "$src1 = $dst"
2379 let Predicates = [HasSSE2] in {
2380 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2381 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2382 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2383 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2384 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2385 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2386 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2387 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2388 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2389 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2391 // Shift up / down and insert zero's.
2392 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2393 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2394 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2395 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2398 //===---------------------------------------------------------------------===//
2399 // SSE2 - Packed Integer Comparison Instructions
2400 //===---------------------------------------------------------------------===//
2402 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2403 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2405 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2407 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2409 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2411 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2413 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2417 let Constraints = "$src1 = $dst" in {
2418 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2419 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2420 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2421 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2422 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2423 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2424 } // Constraints = "$src1 = $dst"
2426 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2427 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2428 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2429 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2430 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2431 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2432 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2433 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2434 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2435 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2436 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2437 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2439 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2440 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2441 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2442 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2443 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2444 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2445 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2446 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2447 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2448 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2449 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2450 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2452 //===---------------------------------------------------------------------===//
2453 // SSE2 - Packed Integer Pack Instructions
2454 //===---------------------------------------------------------------------===//
2456 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2457 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2459 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2461 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2465 let Constraints = "$src1 = $dst" in {
2466 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2467 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2468 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2469 } // Constraints = "$src1 = $dst"
2471 //===---------------------------------------------------------------------===//
2472 // SSE2 - Packed Integer Shuffle Instructions
2473 //===---------------------------------------------------------------------===//
2475 let ExeDomain = SSEPackedInt in {
2476 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2478 def ri : Ii8<0x70, MRMSrcReg,
2479 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2480 !strconcat(OpcodeStr,
2481 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2482 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2484 def mi : Ii8<0x70, MRMSrcMem,
2485 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2486 !strconcat(OpcodeStr,
2487 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2488 [(set VR128:$dst, (vt (pshuf_frag:$src2
2489 (bc_frag (memopv2i64 addr:$src1)),
2492 } // ExeDomain = SSEPackedInt
2494 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2495 let AddedComplexity = 5 in
2496 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2499 // SSE2 with ImmT == Imm8 and XS prefix.
2500 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2503 // SSE2 with ImmT == Imm8 and XD prefix.
2504 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2508 let Predicates = [HasSSE2] in {
2509 let AddedComplexity = 5 in
2510 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2512 // SSE2 with ImmT == Imm8 and XS prefix.
2513 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2515 // SSE2 with ImmT == Imm8 and XD prefix.
2516 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2519 //===---------------------------------------------------------------------===//
2520 // SSE2 - Packed Integer Unpack Instructions
2521 //===---------------------------------------------------------------------===//
2523 let ExeDomain = SSEPackedInt in {
2524 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2525 PatFrag unp_frag, PatFrag bc_frag, bit Is2Addr = 1> {
2526 def rr : PDI<opc, MRMSrcReg,
2527 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2529 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2530 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2531 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2532 def rm : PDI<opc, MRMSrcMem,
2533 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2535 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2536 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2537 [(set VR128:$dst, (unp_frag VR128:$src1,
2538 (bc_frag (memopv2i64
2542 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2543 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, unpckl, bc_v16i8,
2545 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, unpckl, bc_v8i16,
2547 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, unpckl, bc_v4i32,
2550 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2551 /// knew to collapse (bitconvert VT to VT) into its operand.
2552 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2553 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2554 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2556 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>, VEX_4V;
2557 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2558 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2559 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2561 (v2i64 (unpckl VR128:$src1,
2562 (memopv2i64 addr:$src2))))]>, VEX_4V;
2564 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, unpckh, bc_v16i8,
2566 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, unpckh, bc_v8i16,
2568 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, unpckh, bc_v4i32,
2571 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2572 /// knew to collapse (bitconvert VT to VT) into its operand.
2573 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2574 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2575 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2577 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>, VEX_4V;
2578 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2579 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2580 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2582 (v2i64 (unpckh VR128:$src1,
2583 (memopv2i64 addr:$src2))))]>, VEX_4V;
2586 let Constraints = "$src1 = $dst" in {
2587 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2588 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2589 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2591 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2592 /// knew to collapse (bitconvert VT to VT) into its operand.
2593 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2594 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2595 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2597 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2598 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2599 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2600 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2602 (v2i64 (unpckl VR128:$src1,
2603 (memopv2i64 addr:$src2))))]>;
2605 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2606 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2607 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2609 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2610 /// knew to collapse (bitconvert VT to VT) into its operand.
2611 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2612 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2613 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2615 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2616 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2617 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2618 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2620 (v2i64 (unpckh VR128:$src1,
2621 (memopv2i64 addr:$src2))))]>;
2624 } // ExeDomain = SSEPackedInt
2626 //===---------------------------------------------------------------------===//
2627 // SSE2 - Packed Integer Extract and Insert
2628 //===---------------------------------------------------------------------===//
2630 let ExeDomain = SSEPackedInt in {
2631 multiclass sse2_pinsrw<bit Is2Addr = 1> {
2632 def rri : Ii8<0xC4, MRMSrcReg,
2633 (outs VR128:$dst), (ins VR128:$src1,
2634 GR32:$src2, i32i8imm:$src3),
2636 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2637 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2639 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2640 def rmi : Ii8<0xC4, MRMSrcMem,
2641 (outs VR128:$dst), (ins VR128:$src1,
2642 i16mem:$src2, i32i8imm:$src3),
2644 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2645 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2647 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2652 let isAsmParserOnly = 1, Predicates = [HasAVX] in
2653 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
2654 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2655 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2656 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2657 imm:$src2))]>, OpSize, VEX;
2658 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2659 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2660 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2661 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2665 let isAsmParserOnly = 1, Predicates = [HasAVX] in
2666 defm PINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
2668 let Constraints = "$src1 = $dst" in
2669 defm VPINSRW : sse2_pinsrw, TB, OpSize;
2671 } // ExeDomain = SSEPackedInt
2673 //===---------------------------------------------------------------------===//
2674 // SSE2 - Packed Mask Creation
2675 //===---------------------------------------------------------------------===//
2677 let ExeDomain = SSEPackedInt in {
2679 let isAsmParserOnly = 1 in
2680 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2681 "pmovmskb\t{$src, $dst|$dst, $src}",
2682 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2683 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2684 "pmovmskb\t{$src, $dst|$dst, $src}",
2685 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2687 } // ExeDomain = SSEPackedInt
2689 //===---------------------------------------------------------------------===//
2690 // SSE2 - Conditional Store
2691 //===---------------------------------------------------------------------===//
2693 let ExeDomain = SSEPackedInt in {
2695 let isAsmParserOnly = 1 in {
2697 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
2698 (ins VR128:$src, VR128:$mask),
2699 "maskmovdqu\t{$mask, $src|$src, $mask}",
2700 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
2702 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
2703 (ins VR128:$src, VR128:$mask),
2704 "maskmovdqu\t{$mask, $src|$src, $mask}",
2705 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
2709 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2710 "maskmovdqu\t{$mask, $src|$src, $mask}",
2711 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2713 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2714 "maskmovdqu\t{$mask, $src|$src, $mask}",
2715 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2717 } // ExeDomain = SSEPackedInt
2719 //===---------------------------------------------------------------------===//
2720 // SSE2 - Move Doubleword
2721 //===---------------------------------------------------------------------===//
2723 // Move Int Doubleword to Packed Double Int
2724 let isAsmParserOnly = 1 in {
2725 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2726 "movd\t{$src, $dst|$dst, $src}",
2728 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
2729 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2730 "movd\t{$src, $dst|$dst, $src}",
2732 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
2735 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2736 "movd\t{$src, $dst|$dst, $src}",
2738 (v4i32 (scalar_to_vector GR32:$src)))]>;
2739 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2740 "movd\t{$src, $dst|$dst, $src}",
2742 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2745 // Move Int Doubleword to Single Scalar
2746 let isAsmParserOnly = 1 in {
2747 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2748 "movd\t{$src, $dst|$dst, $src}",
2749 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
2751 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2752 "movd\t{$src, $dst|$dst, $src}",
2753 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
2756 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2757 "movd\t{$src, $dst|$dst, $src}",
2758 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2760 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2761 "movd\t{$src, $dst|$dst, $src}",
2762 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2764 // Move Packed Doubleword Int to Packed Double Int
2765 let isAsmParserOnly = 1 in {
2766 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2767 "movd\t{$src, $dst|$dst, $src}",
2768 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2770 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
2771 (ins i32mem:$dst, VR128:$src),
2772 "movd\t{$src, $dst|$dst, $src}",
2773 [(store (i32 (vector_extract (v4i32 VR128:$src),
2774 (iPTR 0))), addr:$dst)]>, VEX;
2776 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2777 "movd\t{$src, $dst|$dst, $src}",
2778 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2780 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2781 "movd\t{$src, $dst|$dst, $src}",
2782 [(store (i32 (vector_extract (v4i32 VR128:$src),
2783 (iPTR 0))), addr:$dst)]>;
2785 // Move Scalar Single to Double Int
2786 let isAsmParserOnly = 1 in {
2787 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2788 "movd\t{$src, $dst|$dst, $src}",
2789 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
2790 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2791 "movd\t{$src, $dst|$dst, $src}",
2792 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
2794 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2795 "movd\t{$src, $dst|$dst, $src}",
2796 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2797 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2798 "movd\t{$src, $dst|$dst, $src}",
2799 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2801 // movd / movq to XMM register zero-extends
2802 let AddedComplexity = 15, isAsmParserOnly = 1 in {
2803 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2804 "movd\t{$src, $dst|$dst, $src}",
2805 [(set VR128:$dst, (v4i32 (X86vzmovl
2806 (v4i32 (scalar_to_vector GR32:$src)))))]>,
2808 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2809 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2810 [(set VR128:$dst, (v2i64 (X86vzmovl
2811 (v2i64 (scalar_to_vector GR64:$src)))))]>,
2814 let AddedComplexity = 15 in {
2815 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2816 "movd\t{$src, $dst|$dst, $src}",
2817 [(set VR128:$dst, (v4i32 (X86vzmovl
2818 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2819 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2820 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2821 [(set VR128:$dst, (v2i64 (X86vzmovl
2822 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2825 let AddedComplexity = 20 in {
2826 let isAsmParserOnly = 1 in
2827 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2828 "movd\t{$src, $dst|$dst, $src}",
2830 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2831 (loadi32 addr:$src))))))]>,
2833 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2834 "movd\t{$src, $dst|$dst, $src}",
2836 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2837 (loadi32 addr:$src))))))]>;
2839 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2840 (MOVZDI2PDIrm addr:$src)>;
2841 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2842 (MOVZDI2PDIrm addr:$src)>;
2843 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2844 (MOVZDI2PDIrm addr:$src)>;
2847 //===---------------------------------------------------------------------===//
2848 // SSE2 - Move Quadword
2849 //===---------------------------------------------------------------------===//
2851 // Move Quadword Int to Packed Quadword Int
2852 let isAsmParserOnly = 1 in
2853 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2854 "vmovq\t{$src, $dst|$dst, $src}",
2856 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2857 VEX, Requires<[HasAVX]>;
2858 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2859 "movq\t{$src, $dst|$dst, $src}",
2861 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2862 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
2864 // Move Packed Quadword Int to Quadword Int
2865 let isAsmParserOnly = 1 in
2866 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2867 "movq\t{$src, $dst|$dst, $src}",
2868 [(store (i64 (vector_extract (v2i64 VR128:$src),
2869 (iPTR 0))), addr:$dst)]>, VEX;
2870 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2871 "movq\t{$src, $dst|$dst, $src}",
2872 [(store (i64 (vector_extract (v2i64 VR128:$src),
2873 (iPTR 0))), addr:$dst)]>;
2875 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2876 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
2878 // Store / copy lower 64-bits of a XMM register.
2879 let isAsmParserOnly = 1 in
2880 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2881 "movq\t{$src, $dst|$dst, $src}",
2882 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
2883 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2884 "movq\t{$src, $dst|$dst, $src}",
2885 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2887 let AddedComplexity = 20, isAsmParserOnly = 1 in
2888 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2889 "vmovq\t{$src, $dst|$dst, $src}",
2891 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2892 (loadi64 addr:$src))))))]>,
2893 XS, VEX, Requires<[HasAVX]>;
2895 let AddedComplexity = 20 in {
2896 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2897 "movq\t{$src, $dst|$dst, $src}",
2899 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2900 (loadi64 addr:$src))))))]>,
2901 XS, Requires<[HasSSE2]>;
2903 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2904 (MOVZQI2PQIrm addr:$src)>;
2905 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2906 (MOVZQI2PQIrm addr:$src)>;
2907 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2910 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2911 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2912 let isAsmParserOnly = 1, AddedComplexity = 15 in
2913 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2914 "vmovq\t{$src, $dst|$dst, $src}",
2915 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2916 XS, VEX, Requires<[HasAVX]>;
2917 let AddedComplexity = 15 in
2918 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2919 "movq\t{$src, $dst|$dst, $src}",
2920 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2921 XS, Requires<[HasSSE2]>;
2923 let AddedComplexity = 20, isAsmParserOnly = 1 in
2924 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2925 "vmovq\t{$src, $dst|$dst, $src}",
2926 [(set VR128:$dst, (v2i64 (X86vzmovl
2927 (loadv2i64 addr:$src))))]>,
2928 XS, VEX, Requires<[HasAVX]>;
2929 let AddedComplexity = 20 in {
2930 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2931 "movq\t{$src, $dst|$dst, $src}",
2932 [(set VR128:$dst, (v2i64 (X86vzmovl
2933 (loadv2i64 addr:$src))))]>,
2934 XS, Requires<[HasSSE2]>;
2936 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2937 (MOVZPQILo2PQIrm addr:$src)>;
2940 // Instructions to match in the assembler
2941 let isAsmParserOnly = 1 in {
2942 // This instructions is in fact an alias to movd with 64 bit dst
2943 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2944 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
2945 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2946 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
2949 // Instructions for the disassembler
2950 // xr = XMM register
2953 let isAsmParserOnly = 1 in
2954 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2955 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
2956 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2957 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2959 //===---------------------------------------------------------------------===//
2960 // SSE2 - Misc Instructions
2961 //===---------------------------------------------------------------------===//
2964 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2965 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2966 TB, Requires<[HasSSE2]>;
2968 // Load, store, and memory fence
2969 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
2970 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2971 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
2972 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2974 // Pause. This "instruction" is encoded as "rep; nop", so even though it
2975 // was introduced with SSE2, it's backward compatible.
2976 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
2978 //TODO: custom lower this so as to never even generate the noop
2979 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2981 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2982 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2983 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2986 // Alias instructions that map zero vector to pxor / xorp* for sse.
2987 // We set canFoldAsLoad because this can be converted to a constant-pool
2988 // load of an all-ones value if folding it would be beneficial.
2989 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2990 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
2991 // FIXME: Change encoding to pseudo.
2992 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
2993 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2995 //===---------------------------------------------------------------------===//
2996 // SSE3 - Conversion Instructions
2997 //===---------------------------------------------------------------------===//
2999 // Convert Packed Double FP to Packed DW Integers
3000 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3001 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3002 // register, but the same isn't true when using memory operands instead.
3003 // Provide other assembly rr and rm forms to address this explicitly.
3004 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3005 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3006 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3007 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3010 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3011 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3012 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3013 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3016 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3017 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3018 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3019 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3022 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3023 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3024 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3025 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3027 // Convert Packed DW Integers to Packed Double FP
3028 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3029 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3030 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3031 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3032 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3033 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3034 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3035 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3036 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3039 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3040 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3041 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3042 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3044 //===---------------------------------------------------------------------===//
3045 // SSE3 - Move Instructions
3046 //===---------------------------------------------------------------------===//
3048 // Replicate Single FP
3049 multiclass sse3_replicate_sfp<bits<8> op, PatFrag rep_frag, string OpcodeStr> {
3050 def rr : S3SI<op, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3051 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3052 [(set VR128:$dst, (v4f32 (rep_frag
3053 VR128:$src, (undef))))]>;
3054 def rm : S3SI<op, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3055 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3056 [(set VR128:$dst, (rep_frag
3057 (memopv4f32 addr:$src), (undef)))]>;
3060 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3061 defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
3062 defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
3064 defm MOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "movshdup">;
3065 defm MOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "movsldup">;
3067 // Replicate Double FP
3068 multiclass sse3_replicate_dfp<string OpcodeStr> {
3069 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3070 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3071 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3072 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3073 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3075 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3079 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3080 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3081 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3083 // Move Unaligned Integer
3084 let isAsmParserOnly = 1 in
3085 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3086 "vlddqu\t{$src, $dst|$dst, $src}",
3087 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3088 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3089 "lddqu\t{$src, $dst|$dst, $src}",
3090 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3092 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3094 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3096 // Several Move patterns
3097 let AddedComplexity = 5 in {
3098 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3099 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3100 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3101 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3102 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3103 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3104 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3105 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3108 // vector_shuffle v1, <undef> <1, 1, 3, 3>
3109 let AddedComplexity = 15 in
3110 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
3111 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3112 let AddedComplexity = 20 in
3113 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3114 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
3116 // vector_shuffle v1, <undef> <0, 0, 2, 2>
3117 let AddedComplexity = 15 in
3118 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
3119 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3120 let AddedComplexity = 20 in
3121 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3122 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
3124 //===---------------------------------------------------------------------===//
3125 // SSE3 - Arithmetic
3126 //===---------------------------------------------------------------------===//
3128 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
3129 X86MemOperand x86memop, bit Is2Addr = 1> {
3130 def rr : I<0xD0, MRMSrcReg,
3131 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3133 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3134 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3135 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
3136 def rm : I<0xD0, MRMSrcMem,
3137 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3139 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3140 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3141 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
3144 let isAsmParserOnly = 1, Predicates = [HasAVX],
3145 ExeDomain = SSEPackedDouble in {
3146 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
3147 f128mem, 0>, XD, VEX_4V;
3148 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
3149 f128mem, 0>, OpSize, VEX_4V;
3150 let Pattern = []<dag> in {
3151 defm VADDSUBPSY : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR256,
3152 f256mem, 0>, XD, VEX_4V;
3153 defm VADDSUBPDY : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR256,
3154 f256mem, 0>, OpSize, VEX_4V;
3157 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3158 ExeDomain = SSEPackedDouble in {
3159 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
3161 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
3162 f128mem>, TB, OpSize;
3165 //===---------------------------------------------------------------------===//
3166 // SSE3 Instructions
3167 //===---------------------------------------------------------------------===//
3170 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3171 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3172 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3174 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3175 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3176 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3178 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3180 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3181 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3182 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3184 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3185 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3186 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3188 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3189 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3190 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3192 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3194 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3195 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3196 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3199 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3200 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
3201 int_x86_sse3_hadd_ps, 0>, VEX_4V;
3202 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
3203 int_x86_sse3_hadd_pd, 0>, VEX_4V;
3204 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
3205 int_x86_sse3_hsub_ps, 0>, VEX_4V;
3206 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
3207 int_x86_sse3_hsub_pd, 0>, VEX_4V;
3208 let Pattern = []<dag> in {
3209 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
3210 int_x86_sse3_hadd_ps, 0>, VEX_4V;
3211 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
3212 int_x86_sse3_hadd_pd, 0>, VEX_4V;
3213 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
3214 int_x86_sse3_hsub_ps, 0>, VEX_4V;
3215 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
3216 int_x86_sse3_hsub_pd, 0>, VEX_4V;
3220 let Constraints = "$src1 = $dst" in {
3221 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
3222 int_x86_sse3_hadd_ps>;
3223 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
3224 int_x86_sse3_hadd_pd>;
3225 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
3226 int_x86_sse3_hsub_ps>;
3227 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
3228 int_x86_sse3_hsub_pd>;
3231 //===---------------------------------------------------------------------===//
3232 // SSSE3 - Packed Absolute Instructions
3233 //===---------------------------------------------------------------------===//
3235 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3236 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3237 PatFrag mem_frag64, PatFrag mem_frag128,
3238 Intrinsic IntId64, Intrinsic IntId128> {
3239 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
3240 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3241 [(set VR64:$dst, (IntId64 VR64:$src))]>;
3243 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
3244 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3246 (IntId64 (bitconvert (mem_frag64 addr:$src))))]>;
3248 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3250 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3251 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3254 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3256 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3259 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3262 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3263 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv8i8, memopv16i8,
3264 int_x86_ssse3_pabs_b,
3265 int_x86_ssse3_pabs_b_128>, VEX;
3266 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv4i16, memopv8i16,
3267 int_x86_ssse3_pabs_w,
3268 int_x86_ssse3_pabs_w_128>, VEX;
3269 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv2i32, memopv4i32,
3270 int_x86_ssse3_pabs_d,
3271 int_x86_ssse3_pabs_d_128>, VEX;
3274 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv8i8, memopv16i8,
3275 int_x86_ssse3_pabs_b,
3276 int_x86_ssse3_pabs_b_128>;
3277 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv4i16, memopv8i16,
3278 int_x86_ssse3_pabs_w,
3279 int_x86_ssse3_pabs_w_128>;
3280 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv2i32, memopv4i32,
3281 int_x86_ssse3_pabs_d,
3282 int_x86_ssse3_pabs_d_128>;
3284 //===---------------------------------------------------------------------===//
3285 // SSSE3 - Packed Binary Operator Instructions
3286 //===---------------------------------------------------------------------===//
3288 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3289 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3290 PatFrag mem_frag64, PatFrag mem_frag128,
3291 Intrinsic IntId64, Intrinsic IntId128,
3293 let isCommutable = 1 in
3294 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
3295 (ins VR64:$src1, VR64:$src2),
3297 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3298 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3299 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>;
3300 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
3301 (ins VR64:$src1, i64mem:$src2),
3303 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3304 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3306 (IntId64 VR64:$src1,
3307 (bitconvert (memopv8i8 addr:$src2))))]>;
3309 let isCommutable = 1 in
3310 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3311 (ins VR128:$src1, VR128:$src2),
3313 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3314 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3315 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3317 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3318 (ins VR128:$src1, i128mem:$src2),
3320 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3321 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3323 (IntId128 VR128:$src1,
3324 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3327 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3328 let isCommutable = 0 in {
3329 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv4i16, memopv8i16,
3330 int_x86_ssse3_phadd_w,
3331 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3332 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv2i32, memopv4i32,
3333 int_x86_ssse3_phadd_d,
3334 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3335 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv4i16, memopv8i16,
3336 int_x86_ssse3_phadd_sw,
3337 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3338 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv4i16, memopv8i16,
3339 int_x86_ssse3_phsub_w,
3340 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3341 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv2i32, memopv4i32,
3342 int_x86_ssse3_phsub_d,
3343 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3344 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv4i16, memopv8i16,
3345 int_x86_ssse3_phsub_sw,
3346 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3347 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv8i8, memopv16i8,
3348 int_x86_ssse3_pmadd_ub_sw,
3349 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3350 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv8i8, memopv16i8,
3351 int_x86_ssse3_pshuf_b,
3352 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3353 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv8i8, memopv16i8,
3354 int_x86_ssse3_psign_b,
3355 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3356 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv4i16, memopv8i16,
3357 int_x86_ssse3_psign_w,
3358 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3359 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv2i32, memopv4i32,
3360 int_x86_ssse3_psign_d,
3361 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3363 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv4i16, memopv8i16,
3364 int_x86_ssse3_pmul_hr_sw,
3365 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3368 // None of these have i8 immediate fields.
3369 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3370 let isCommutable = 0 in {
3371 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv4i16, memopv8i16,
3372 int_x86_ssse3_phadd_w,
3373 int_x86_ssse3_phadd_w_128>;
3374 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv2i32, memopv4i32,
3375 int_x86_ssse3_phadd_d,
3376 int_x86_ssse3_phadd_d_128>;
3377 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv4i16, memopv8i16,
3378 int_x86_ssse3_phadd_sw,
3379 int_x86_ssse3_phadd_sw_128>;
3380 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv4i16, memopv8i16,
3381 int_x86_ssse3_phsub_w,
3382 int_x86_ssse3_phsub_w_128>;
3383 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv2i32, memopv4i32,
3384 int_x86_ssse3_phsub_d,
3385 int_x86_ssse3_phsub_d_128>;
3386 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv4i16, memopv8i16,
3387 int_x86_ssse3_phsub_sw,
3388 int_x86_ssse3_phsub_sw_128>;
3389 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv8i8, memopv16i8,
3390 int_x86_ssse3_pmadd_ub_sw,
3391 int_x86_ssse3_pmadd_ub_sw_128>;
3392 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv8i8, memopv16i8,
3393 int_x86_ssse3_pshuf_b,
3394 int_x86_ssse3_pshuf_b_128>;
3395 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv8i8, memopv16i8,
3396 int_x86_ssse3_psign_b,
3397 int_x86_ssse3_psign_b_128>;
3398 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv4i16, memopv8i16,
3399 int_x86_ssse3_psign_w,
3400 int_x86_ssse3_psign_w_128>;
3401 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv2i32, memopv4i32,
3402 int_x86_ssse3_psign_d,
3403 int_x86_ssse3_psign_d_128>;
3405 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv4i16, memopv8i16,
3406 int_x86_ssse3_pmul_hr_sw,
3407 int_x86_ssse3_pmul_hr_sw_128>;
3410 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3411 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3412 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3413 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3415 //===---------------------------------------------------------------------===//
3416 // SSSE3 - Packed Align Instruction Patterns
3417 //===---------------------------------------------------------------------===//
3419 multiclass sse3_palign<string asm, bit Is2Addr = 1> {
3420 def R64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
3421 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
3423 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3425 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3427 def R64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
3428 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
3430 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3432 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3435 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3436 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3438 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3440 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3442 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3443 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3445 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3447 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3451 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3452 defm VPALIGN : sse3_palign<"vpalignr", 0>, VEX_4V;
3453 let Constraints = "$src1 = $dst" in
3454 defm PALIGN : sse3_palign<"palignr">;
3456 let AddedComplexity = 5 in {
3458 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
3459 (PALIGNR64rr VR64:$src2, VR64:$src1,
3460 (SHUFFLE_get_palign_imm VR64:$src3))>,
3461 Requires<[HasSSSE3]>;
3462 def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
3463 (PALIGNR64rr VR64:$src2, VR64:$src1,
3464 (SHUFFLE_get_palign_imm VR64:$src3))>,
3465 Requires<[HasSSSE3]>;
3466 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
3467 (PALIGNR64rr VR64:$src2, VR64:$src1,
3468 (SHUFFLE_get_palign_imm VR64:$src3))>,
3469 Requires<[HasSSSE3]>;
3470 def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
3471 (PALIGNR64rr VR64:$src2, VR64:$src1,
3472 (SHUFFLE_get_palign_imm VR64:$src3))>,
3473 Requires<[HasSSSE3]>;
3475 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
3476 (PALIGNR128rr VR128:$src2, VR128:$src1,
3477 (SHUFFLE_get_palign_imm VR128:$src3))>,
3478 Requires<[HasSSSE3]>;
3479 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
3480 (PALIGNR128rr VR128:$src2, VR128:$src1,
3481 (SHUFFLE_get_palign_imm VR128:$src3))>,
3482 Requires<[HasSSSE3]>;
3483 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
3484 (PALIGNR128rr VR128:$src2, VR128:$src1,
3485 (SHUFFLE_get_palign_imm VR128:$src3))>,
3486 Requires<[HasSSSE3]>;
3487 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
3488 (PALIGNR128rr VR128:$src2, VR128:$src1,
3489 (SHUFFLE_get_palign_imm VR128:$src3))>,
3490 Requires<[HasSSSE3]>;
3493 //===---------------------------------------------------------------------===//
3494 // SSSE3 Misc Instructions
3495 //===---------------------------------------------------------------------===//
3497 // Thread synchronization
3498 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
3499 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
3500 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
3501 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
3503 //===---------------------------------------------------------------------===//
3504 // Non-Instruction Patterns
3505 //===---------------------------------------------------------------------===//
3507 // extload f32 -> f64. This matches load+fextend because we have a hack in
3508 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3510 // Since these loads aren't folded into the fextend, we have to match it
3512 let Predicates = [HasSSE2] in
3513 def : Pat<(fextend (loadf32 addr:$src)),
3514 (CVTSS2SDrm addr:$src)>;
3517 let Predicates = [HasSSE2] in {
3518 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3519 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3520 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3521 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3522 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3523 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3524 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3525 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3526 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3527 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3528 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3529 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3530 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3531 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3532 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3533 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3534 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3535 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3536 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3537 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3538 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3539 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3540 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3541 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3542 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3543 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3544 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3545 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3546 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3547 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3550 // Move scalar to XMM zero-extended
3551 // movd to XMM register zero-extends
3552 let AddedComplexity = 15 in {
3553 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3554 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3555 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3556 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3557 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3558 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3559 (MOVSSrr (v4f32 (V_SET0PS)),
3560 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3561 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3562 (MOVSSrr (v4i32 (V_SET0PI)),
3563 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3566 // Splat v2f64 / v2i64
3567 let AddedComplexity = 10 in {
3568 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3569 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3570 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3571 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3572 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3573 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3574 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3575 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3578 // Special unary SHUFPSrri case.
3579 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3580 (SHUFPSrri VR128:$src1, VR128:$src1,
3581 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3582 let AddedComplexity = 5 in
3583 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3584 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3585 Requires<[HasSSE2]>;
3586 // Special unary SHUFPDrri case.
3587 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3588 (SHUFPDrri VR128:$src1, VR128:$src1,
3589 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3590 Requires<[HasSSE2]>;
3591 // Special unary SHUFPDrri case.
3592 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3593 (SHUFPDrri VR128:$src1, VR128:$src1,
3594 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3595 Requires<[HasSSE2]>;
3596 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3597 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3598 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3599 Requires<[HasSSE2]>;
3601 // Special binary v4i32 shuffle cases with SHUFPS.
3602 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3603 (SHUFPSrri VR128:$src1, VR128:$src2,
3604 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3605 Requires<[HasSSE2]>;
3606 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3607 (SHUFPSrmi VR128:$src1, addr:$src2,
3608 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3609 Requires<[HasSSE2]>;
3610 // Special binary v2i64 shuffle cases using SHUFPDrri.
3611 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3612 (SHUFPDrri VR128:$src1, VR128:$src2,
3613 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3614 Requires<[HasSSE2]>;
3616 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3617 let AddedComplexity = 15 in {
3618 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3619 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3620 Requires<[OptForSpeed, HasSSE2]>;
3621 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3622 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3623 Requires<[OptForSpeed, HasSSE2]>;
3625 let AddedComplexity = 10 in {
3626 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3627 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3628 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3629 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3630 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3631 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3632 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3633 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3636 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3637 let AddedComplexity = 15 in {
3638 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3639 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3640 Requires<[OptForSpeed, HasSSE2]>;
3641 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3642 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3643 Requires<[OptForSpeed, HasSSE2]>;
3645 let AddedComplexity = 10 in {
3646 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3647 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3648 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3649 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3650 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3651 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3652 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3653 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3656 let AddedComplexity = 20 in {
3657 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3658 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3659 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3661 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3662 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3663 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3665 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3666 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3667 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3668 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3669 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3672 let AddedComplexity = 20 in {
3673 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3674 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3675 (MOVLPSrm VR128:$src1, addr:$src2)>;
3676 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3677 (MOVLPDrm VR128:$src1, addr:$src2)>;
3678 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3679 (MOVLPSrm VR128:$src1, addr:$src2)>;
3680 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3681 (MOVLPDrm VR128:$src1, addr:$src2)>;
3684 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3685 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3686 (MOVLPSmr addr:$src1, VR128:$src2)>;
3687 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3688 (MOVLPDmr addr:$src1, VR128:$src2)>;
3689 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3691 (MOVLPSmr addr:$src1, VR128:$src2)>;
3692 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3693 (MOVLPDmr addr:$src1, VR128:$src2)>;
3695 let AddedComplexity = 15 in {
3696 // Setting the lowest element in the vector.
3697 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3698 (MOVSSrr (v4i32 VR128:$src1),
3699 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3700 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3701 (MOVSDrr (v2i64 VR128:$src1),
3702 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3704 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3705 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3706 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3707 Requires<[HasSSE2]>;
3708 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3709 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3710 Requires<[HasSSE2]>;
3713 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3714 // fall back to this for SSE1)
3715 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3716 (SHUFPSrri VR128:$src2, VR128:$src1,
3717 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3719 // Set lowest element and zero upper elements.
3720 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3721 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3723 // Some special case pandn patterns.
3724 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3726 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3727 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3729 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3730 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3732 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3734 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3735 (memop addr:$src2))),
3736 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3737 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3738 (memop addr:$src2))),
3739 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3740 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3741 (memop addr:$src2))),
3742 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3744 // vector -> vector casts
3745 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3746 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3747 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3748 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3749 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3750 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3751 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3752 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3754 // Use movaps / movups for SSE integer load / store (one byte shorter).
3755 def : Pat<(alignedloadv4i32 addr:$src),
3756 (MOVAPSrm addr:$src)>;
3757 def : Pat<(loadv4i32 addr:$src),
3758 (MOVUPSrm addr:$src)>;
3759 def : Pat<(alignedloadv2i64 addr:$src),
3760 (MOVAPSrm addr:$src)>;
3761 def : Pat<(loadv2i64 addr:$src),
3762 (MOVUPSrm addr:$src)>;
3764 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3765 (MOVAPSmr addr:$dst, VR128:$src)>;
3766 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3767 (MOVAPSmr addr:$dst, VR128:$src)>;
3768 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3769 (MOVAPSmr addr:$dst, VR128:$src)>;
3770 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3771 (MOVAPSmr addr:$dst, VR128:$src)>;
3772 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3773 (MOVUPSmr addr:$dst, VR128:$src)>;
3774 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3775 (MOVUPSmr addr:$dst, VR128:$src)>;
3776 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3777 (MOVUPSmr addr:$dst, VR128:$src)>;
3778 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3779 (MOVUPSmr addr:$dst, VR128:$src)>;
3781 //===----------------------------------------------------------------------===//
3782 // SSE4.1 - Packed Move with Sign/Zero Extend
3783 //===----------------------------------------------------------------------===//
3785 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3786 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3787 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3788 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3790 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3791 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3793 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3797 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3798 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
3800 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
3802 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
3804 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
3806 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
3808 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
3812 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3813 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3814 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3815 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3816 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3817 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3819 // Common patterns involving scalar load.
3820 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3821 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3822 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3823 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3825 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3826 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3827 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3828 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3830 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3831 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3832 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3833 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3835 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3836 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3837 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3838 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3840 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3841 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3842 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3843 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3845 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3846 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3847 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3848 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3851 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3852 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3853 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3854 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3856 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3857 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3859 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3863 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3864 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
3866 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
3868 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
3870 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
3874 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3875 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3876 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3877 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3879 // Common patterns involving scalar load
3880 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3881 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3882 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3883 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3885 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3886 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3887 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3888 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3891 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3892 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3893 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3894 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3896 // Expecting a i16 load any extended to i32 value.
3897 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3898 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3899 [(set VR128:$dst, (IntId (bitconvert
3900 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3904 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3905 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
3907 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
3910 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3911 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3913 // Common patterns involving scalar load
3914 def : Pat<(int_x86_sse41_pmovsxbq
3915 (bitconvert (v4i32 (X86vzmovl
3916 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3917 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3919 def : Pat<(int_x86_sse41_pmovzxbq
3920 (bitconvert (v4i32 (X86vzmovl
3921 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3922 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3924 //===----------------------------------------------------------------------===//
3925 // SSE4.1 - Extract Instructions
3926 //===----------------------------------------------------------------------===//
3928 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3929 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3930 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3931 (ins VR128:$src1, i32i8imm:$src2),
3932 !strconcat(OpcodeStr,
3933 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3934 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3936 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3937 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3938 !strconcat(OpcodeStr,
3939 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3942 // There's an AssertZext in the way of writing the store pattern
3943 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3946 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3947 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
3949 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3952 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3953 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3954 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3955 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3956 !strconcat(OpcodeStr,
3957 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3960 // There's an AssertZext in the way of writing the store pattern
3961 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3964 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3965 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
3967 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3970 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3971 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3972 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3973 (ins VR128:$src1, i32i8imm:$src2),
3974 !strconcat(OpcodeStr,
3975 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3977 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3978 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3979 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3980 !strconcat(OpcodeStr,
3981 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3982 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3983 addr:$dst)]>, OpSize;
3986 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3987 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
3989 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3991 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3992 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
3993 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
3994 (ins VR128:$src1, i32i8imm:$src2),
3995 !strconcat(OpcodeStr,
3996 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3998 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
3999 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4000 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4001 !strconcat(OpcodeStr,
4002 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4003 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4004 addr:$dst)]>, OpSize, REX_W;
4007 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4008 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4010 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4012 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4014 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4015 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4016 (ins VR128:$src1, i32i8imm:$src2),
4017 !strconcat(OpcodeStr,
4018 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4020 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4022 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4023 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4024 !strconcat(OpcodeStr,
4025 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4026 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4027 addr:$dst)]>, OpSize;
4030 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4031 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4032 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4034 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4035 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4038 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4039 Requires<[HasSSE41]>;
4041 //===----------------------------------------------------------------------===//
4042 // SSE4.1 - Insert Instructions
4043 //===----------------------------------------------------------------------===//
4045 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4046 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4047 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4049 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4051 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4053 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4054 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4055 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4057 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4059 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4061 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4062 imm:$src3))]>, OpSize;
4065 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4066 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4067 let Constraints = "$src1 = $dst" in
4068 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4070 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4071 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4072 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4074 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4076 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4078 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4080 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4081 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4083 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4085 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4087 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4088 imm:$src3)))]>, OpSize;
4091 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4092 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4093 let Constraints = "$src1 = $dst" in
4094 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4096 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4097 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4098 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4100 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4102 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4104 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4106 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4107 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4109 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4111 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4113 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4114 imm:$src3)))]>, OpSize;
4117 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4118 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4119 let Constraints = "$src1 = $dst" in
4120 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4122 // insertps has a few different modes, there's the first two here below which
4123 // are optimized inserts that won't zero arbitrary elements in the destination
4124 // vector. The next one matches the intrinsic and could zero arbitrary elements
4125 // in the target vector.
4126 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4127 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4128 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4130 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4132 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4134 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4136 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4137 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
4139 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4141 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4143 (X86insrtps VR128:$src1,
4144 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4145 imm:$src3))]>, OpSize;
4148 let Constraints = "$src1 = $dst" in
4149 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4150 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4151 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4153 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4154 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
4156 //===----------------------------------------------------------------------===//
4157 // SSE4.1 - Round Instructions
4158 //===----------------------------------------------------------------------===//
4160 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
4163 Intrinsic V2F64Int> {
4164 // Intrinsic operation, reg.
4165 // Vector intrinsic operation, reg
4166 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
4167 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4168 !strconcat(OpcodeStr,
4169 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4170 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
4173 // Vector intrinsic operation, mem
4174 def PSm_Int : Ii8<opcps, MRMSrcMem,
4175 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
4176 !strconcat(OpcodeStr,
4177 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4179 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
4181 Requires<[HasSSE41]>;
4183 // Vector intrinsic operation, reg
4184 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
4185 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4186 !strconcat(OpcodeStr,
4187 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4188 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
4191 // Vector intrinsic operation, mem
4192 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
4193 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
4194 !strconcat(OpcodeStr,
4195 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4197 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
4201 multiclass sse41_fp_unop_rm_avx<bits<8> opcps, bits<8> opcpd,
4203 // Intrinsic operation, reg.
4204 // Vector intrinsic operation, reg
4205 def PSr : SS4AIi8<opcps, MRMSrcReg,
4206 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4207 !strconcat(OpcodeStr,
4208 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4211 // Vector intrinsic operation, mem
4212 def PSm : Ii8<opcps, MRMSrcMem,
4213 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
4214 !strconcat(OpcodeStr,
4215 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4216 []>, TA, OpSize, Requires<[HasSSE41]>;
4218 // Vector intrinsic operation, reg
4219 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4220 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4221 !strconcat(OpcodeStr,
4222 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4225 // Vector intrinsic operation, mem
4226 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4227 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
4228 !strconcat(OpcodeStr,
4229 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4233 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4236 Intrinsic F64Int, bit Is2Addr = 1> {
4237 // Intrinsic operation, reg.
4238 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
4239 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4241 !strconcat(OpcodeStr,
4242 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4243 !strconcat(OpcodeStr,
4244 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4245 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4248 // Intrinsic operation, mem.
4249 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
4250 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4252 !strconcat(OpcodeStr,
4253 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4254 !strconcat(OpcodeStr,
4255 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4257 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4260 // Intrinsic operation, reg.
4261 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
4262 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4264 !strconcat(OpcodeStr,
4265 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4266 !strconcat(OpcodeStr,
4267 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4268 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4271 // Intrinsic operation, mem.
4272 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
4273 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4275 !strconcat(OpcodeStr,
4276 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4277 !strconcat(OpcodeStr,
4278 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4280 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4284 multiclass sse41_fp_binop_rm_avx<bits<8> opcss, bits<8> opcsd,
4286 // Intrinsic operation, reg.
4287 def SSr : SS4AIi8<opcss, MRMSrcReg,
4288 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4289 !strconcat(OpcodeStr,
4290 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4293 // Intrinsic operation, mem.
4294 def SSm : SS4AIi8<opcss, MRMSrcMem,
4295 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4296 !strconcat(OpcodeStr,
4297 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4300 // Intrinsic operation, reg.
4301 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4302 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4303 !strconcat(OpcodeStr,
4304 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4307 // Intrinsic operation, mem.
4308 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4309 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4310 !strconcat(OpcodeStr,
4311 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4315 // FP round - roundss, roundps, roundsd, roundpd
4316 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4318 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround",
4319 int_x86_sse41_round_ps, int_x86_sse41_round_pd>,
4321 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4322 int_x86_sse41_round_ss, int_x86_sse41_round_sd,
4324 // Instructions for the assembler
4325 defm VROUND : sse41_fp_unop_rm_avx<0x08, 0x09, "vround">, VEX;
4326 defm VROUND : sse41_fp_binop_rm_avx<0x0A, 0x0B, "vround">, VEX_4V;
4329 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
4330 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4331 let Constraints = "$src1 = $dst" in
4332 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4333 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4335 //===----------------------------------------------------------------------===//
4336 // SSE4.1 - Misc Instructions
4337 //===----------------------------------------------------------------------===//
4339 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4340 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4341 Intrinsic IntId128> {
4342 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4344 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4345 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4346 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4348 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4351 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4354 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4355 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4356 int_x86_sse41_phminposuw>, VEX;
4357 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4358 int_x86_sse41_phminposuw>;
4360 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4361 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4362 Intrinsic IntId128, bit Is2Addr = 1> {
4363 let isCommutable = 1 in
4364 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4365 (ins VR128:$src1, VR128:$src2),
4367 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4368 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4369 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4370 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4371 (ins VR128:$src1, i128mem:$src2),
4373 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4374 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4376 (IntId128 VR128:$src1,
4377 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4380 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4381 let isCommutable = 0 in
4382 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4384 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4386 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4388 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4390 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4392 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4394 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4396 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4398 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4400 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4402 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4406 let Constraints = "$src1 = $dst" in {
4407 let isCommutable = 0 in
4408 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4409 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4410 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4411 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4412 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4413 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4414 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4415 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4416 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4417 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4418 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4421 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4422 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4423 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4424 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4426 /// SS48I_binop_rm - Simple SSE41 binary operator.
4427 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4428 ValueType OpVT, bit Is2Addr = 1> {
4429 let isCommutable = 1 in
4430 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4431 (ins VR128:$src1, VR128:$src2),
4433 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4434 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4435 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4437 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4438 (ins VR128:$src1, i128mem:$src2),
4440 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4441 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4442 [(set VR128:$dst, (OpNode VR128:$src1,
4443 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
4447 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4448 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
4449 let Constraints = "$src1 = $dst" in
4450 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
4452 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
4453 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
4454 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
4455 X86MemOperand x86memop, bit Is2Addr = 1> {
4456 let isCommutable = 1 in
4457 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
4458 (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4460 !strconcat(OpcodeStr,
4461 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4462 !strconcat(OpcodeStr,
4463 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4464 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
4466 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
4467 (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4469 !strconcat(OpcodeStr,
4470 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4471 !strconcat(OpcodeStr,
4472 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4475 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
4479 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4480 let isCommutable = 0 in {
4481 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4482 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4483 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4484 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4485 let Pattern = []<dag> in {
4486 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4487 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4488 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4489 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4491 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
4492 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4493 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
4494 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4496 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4497 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4498 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
4499 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4500 let Pattern = []<dag> in
4501 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4502 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4505 let Constraints = "$src1 = $dst" in {
4506 let isCommutable = 0 in {
4507 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
4508 VR128, memopv16i8, i128mem>;
4509 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
4510 VR128, memopv16i8, i128mem>;
4511 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
4512 VR128, memopv16i8, i128mem>;
4513 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
4514 VR128, memopv16i8, i128mem>;
4516 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
4517 VR128, memopv16i8, i128mem>;
4518 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
4519 VR128, memopv16i8, i128mem>;
4522 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
4523 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4524 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
4525 RegisterClass RC, X86MemOperand x86memop> {
4526 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
4527 (ins RC:$src1, RC:$src2, RC:$src3),
4528 !strconcat(OpcodeStr,
4529 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4530 [], SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4532 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
4533 (ins RC:$src1, x86memop:$src2, RC:$src3),
4534 !strconcat(OpcodeStr,
4535 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4536 [], SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4540 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem>;
4541 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem>;
4542 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem>;
4543 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem>;
4545 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem>;
4547 /// SS41I_ternary_int - SSE 4.1 ternary operator
4548 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4549 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4550 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4551 (ins VR128:$src1, VR128:$src2),
4552 !strconcat(OpcodeStr,
4553 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
4554 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4557 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4558 (ins VR128:$src1, i128mem:$src2),
4559 !strconcat(OpcodeStr,
4560 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
4563 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
4567 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
4568 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
4569 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
4571 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4572 // the intel intrinsic that corresponds to this.
4573 let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX] in {
4574 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4575 "vptest\t{$src2, $src1|$src1, $src2}",
4576 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
4578 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
4579 "vptest\t{$src2, $src1|$src1, $src2}",
4580 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
4584 let Defs = [EFLAGS] in {
4585 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4586 "ptest \t{$src2, $src1|$src1, $src2}",
4587 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
4589 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
4590 "ptest \t{$src2, $src1|$src1, $src2}",
4591 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
4595 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4596 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4597 "vmovntdqa\t{$src, $dst|$dst, $src}",
4598 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4600 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4601 "movntdqa\t{$src, $dst|$dst, $src}",
4602 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4605 //===----------------------------------------------------------------------===//
4606 // SSE4.2 - Compare Instructions
4607 //===----------------------------------------------------------------------===//
4609 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
4610 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
4611 Intrinsic IntId128, bit Is2Addr = 1> {
4612 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4613 (ins VR128:$src1, VR128:$src2),
4615 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4616 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4617 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4619 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
4620 (ins VR128:$src1, i128mem:$src2),
4622 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4623 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4625 (IntId128 VR128:$src1,
4626 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4629 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4630 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
4632 let Constraints = "$src1 = $dst" in
4633 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
4635 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
4636 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
4637 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
4638 (PCMPGTQrm VR128:$src1, addr:$src2)>;
4640 //===----------------------------------------------------------------------===//
4641 // SSE4.2 - String/text Processing Instructions
4642 //===----------------------------------------------------------------------===//
4644 // Packed Compare Implicit Length Strings, Return Mask
4645 let Defs = [EFLAGS], usesCustomInserter = 1 in {
4646 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
4647 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4648 "#PCMPISTRM128rr PSEUDO!",
4649 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
4650 imm:$src3))]>, OpSize;
4651 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
4652 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4653 "#PCMPISTRM128rm PSEUDO!",
4654 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
4655 VR128:$src1, (load addr:$src2), imm:$src3))]>, OpSize;
4658 let Defs = [XMM0, EFLAGS], isAsmParserOnly = 1,
4659 Predicates = [HasAVX] in {
4660 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4661 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4662 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4663 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4664 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4665 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4668 let Defs = [XMM0, EFLAGS] in {
4669 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4670 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4671 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4672 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4673 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4674 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4677 // Packed Compare Explicit Length Strings, Return Mask
4678 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
4679 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
4680 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4681 "#PCMPESTRM128rr PSEUDO!",
4683 (int_x86_sse42_pcmpestrm128
4684 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
4686 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
4687 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4688 "#PCMPESTRM128rm PSEUDO!",
4689 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4690 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
4694 let isAsmParserOnly = 1, Predicates = [HasAVX],
4695 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4696 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4697 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4698 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4699 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4700 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4701 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4704 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4705 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4706 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4707 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4708 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4709 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4710 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4713 // Packed Compare Implicit Length Strings, Return Index
4714 let Defs = [ECX, EFLAGS] in {
4715 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
4716 def rr : SS42AI<0x63, MRMSrcReg, (outs),
4717 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4718 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
4719 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
4720 (implicit EFLAGS)]>, OpSize;
4721 def rm : SS42AI<0x63, MRMSrcMem, (outs),
4722 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4723 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
4724 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
4725 (implicit EFLAGS)]>, OpSize;
4729 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4730 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
4732 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
4734 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
4736 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
4738 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
4740 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
4744 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
4745 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
4746 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
4747 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
4748 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
4749 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
4751 // Packed Compare Explicit Length Strings, Return Index
4752 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
4753 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
4754 def rr : SS42AI<0x61, MRMSrcReg, (outs),
4755 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4756 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
4757 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
4758 (implicit EFLAGS)]>, OpSize;
4759 def rm : SS42AI<0x61, MRMSrcMem, (outs),
4760 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4761 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
4763 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
4764 (implicit EFLAGS)]>, OpSize;
4768 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4769 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
4771 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
4773 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
4775 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
4777 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
4779 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
4783 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
4784 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
4785 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
4786 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
4787 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
4788 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
4790 //===----------------------------------------------------------------------===//
4791 // SSE4.2 - CRC Instructions
4792 //===----------------------------------------------------------------------===//
4794 // No CRC instructions have AVX equivalents
4796 // crc intrinsic instruction
4797 // This set of instructions are only rm, the only difference is the size
4799 let Constraints = "$src1 = $dst" in {
4800 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
4801 (ins GR32:$src1, i8mem:$src2),
4802 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4804 (int_x86_sse42_crc32_8 GR32:$src1,
4805 (load addr:$src2)))]>;
4806 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
4807 (ins GR32:$src1, GR8:$src2),
4808 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4810 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
4811 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
4812 (ins GR32:$src1, i16mem:$src2),
4813 "crc32{w} \t{$src2, $src1|$src1, $src2}",
4815 (int_x86_sse42_crc32_16 GR32:$src1,
4816 (load addr:$src2)))]>,
4818 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
4819 (ins GR32:$src1, GR16:$src2),
4820 "crc32{w} \t{$src2, $src1|$src1, $src2}",
4822 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
4824 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
4825 (ins GR32:$src1, i32mem:$src2),
4826 "crc32{l} \t{$src2, $src1|$src1, $src2}",
4828 (int_x86_sse42_crc32_32 GR32:$src1,
4829 (load addr:$src2)))]>;
4830 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
4831 (ins GR32:$src1, GR32:$src2),
4832 "crc32{l} \t{$src2, $src1|$src1, $src2}",
4834 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
4835 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
4836 (ins GR64:$src1, i8mem:$src2),
4837 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4839 (int_x86_sse42_crc64_8 GR64:$src1,
4840 (load addr:$src2)))]>,
4842 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
4843 (ins GR64:$src1, GR8:$src2),
4844 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4846 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
4848 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
4849 (ins GR64:$src1, i64mem:$src2),
4850 "crc32{q} \t{$src2, $src1|$src1, $src2}",
4852 (int_x86_sse42_crc64_64 GR64:$src1,
4853 (load addr:$src2)))]>,
4855 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
4856 (ins GR64:$src1, GR64:$src2),
4857 "crc32{q} \t{$src2, $src1|$src1, $src2}",
4859 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
4863 //===----------------------------------------------------------------------===//
4864 // AES-NI Instructions
4865 //===----------------------------------------------------------------------===//
4867 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
4868 Intrinsic IntId128, bit Is2Addr = 1> {
4869 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
4870 (ins VR128:$src1, VR128:$src2),
4872 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4873 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4874 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4876 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
4877 (ins VR128:$src1, i128mem:$src2),
4879 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4880 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4882 (IntId128 VR128:$src1,
4883 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4886 // Perform One Round of an AES Encryption/Decryption Flow
4887 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
4888 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
4889 int_x86_aesni_aesenc, 0>, VEX_4V;
4890 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
4891 int_x86_aesni_aesenclast, 0>, VEX_4V;
4892 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
4893 int_x86_aesni_aesdec, 0>, VEX_4V;
4894 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
4895 int_x86_aesni_aesdeclast, 0>, VEX_4V;
4898 let Constraints = "$src1 = $dst" in {
4899 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
4900 int_x86_aesni_aesenc>;
4901 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
4902 int_x86_aesni_aesenclast>;
4903 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
4904 int_x86_aesni_aesdec>;
4905 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
4906 int_x86_aesni_aesdeclast>;
4909 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
4910 (AESENCrr VR128:$src1, VR128:$src2)>;
4911 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
4912 (AESENCrm VR128:$src1, addr:$src2)>;
4913 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
4914 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
4915 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
4916 (AESENCLASTrm VR128:$src1, addr:$src2)>;
4917 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
4918 (AESDECrr VR128:$src1, VR128:$src2)>;
4919 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
4920 (AESDECrm VR128:$src1, addr:$src2)>;
4921 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
4922 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
4923 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
4924 (AESDECLASTrm VR128:$src1, addr:$src2)>;
4926 // Perform the AES InvMixColumn Transformation
4927 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
4928 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
4930 "vaesimc\t{$src1, $dst|$dst, $src1}",
4932 (int_x86_aesni_aesimc VR128:$src1))]>,
4934 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
4935 (ins i128mem:$src1),
4936 "vaesimc\t{$src1, $dst|$dst, $src1}",
4938 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
4941 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
4943 "aesimc\t{$src1, $dst|$dst, $src1}",
4945 (int_x86_aesni_aesimc VR128:$src1))]>,
4947 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
4948 (ins i128mem:$src1),
4949 "aesimc\t{$src1, $dst|$dst, $src1}",
4951 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
4954 // AES Round Key Generation Assist
4955 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
4956 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
4957 (ins VR128:$src1, i8imm:$src2),
4958 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4960 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
4962 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
4963 (ins i128mem:$src1, i8imm:$src2),
4964 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4966 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
4970 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
4971 (ins VR128:$src1, i8imm:$src2),
4972 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4974 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
4976 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
4977 (ins i128mem:$src1, i8imm:$src2),
4978 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4980 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
4984 //===----------------------------------------------------------------------===//
4986 //===----------------------------------------------------------------------===//
4988 let isAsmParserOnly = 1 in {
4990 // Load from memory and broadcast to all elements of the destination operand
4991 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
4992 X86MemOperand x86memop> :
4993 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4994 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>, VEX;
4996 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem>;
4997 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem>;
4998 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem>;
4999 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem>;
5001 // Insert packed floating-point values
5002 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5003 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5004 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5006 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5007 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5008 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5011 // Extract packed floating-point values
5012 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5013 (ins VR256:$src1, i8imm:$src2),
5014 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5016 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5017 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5018 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5021 // Conditional SIMD Packed Loads and Stores
5022 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr> {
5023 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
5024 (ins VR128:$src1, f128mem:$src2),
5025 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5027 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
5028 (ins VR256:$src1, f256mem:$src2),
5029 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5031 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
5032 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
5033 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5035 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
5036 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
5037 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5041 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps">;
5042 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd">;
5044 // Permute Floating-Point Values
5045 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
5046 RegisterClass RC, X86MemOperand x86memop> {
5047 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
5048 (ins RC:$src1, RC:$src2),
5049 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5051 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
5052 (ins RC:$src1, x86memop:$src2),
5053 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5055 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
5056 (ins RC:$src1, i8imm:$src2),
5057 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5059 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
5060 (ins x86memop:$src1, i8imm:$src2),
5061 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5065 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem>;
5066 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem>;
5067 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem>;
5068 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem>;
5070 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
5071 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5072 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5074 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
5075 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
5076 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5079 } // isAsmParserOnly